Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu LtdfiledCriticalFujitsu Ltd
Priority to JP4871585ApriorityCriticalpatent/JPS61210461A/ja
Publication of JPS61210461ApublicationCriticalpatent/JPS61210461A/ja
Publication of JPH0378661B2publicationCriticalpatent/JPH0378661B2/ja
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor
Microcomputer equipped with DMA controller allowed to continue to perform data transfer operations even after completion of a current data transfer operation