JPS61208854A - Ansistor equipped with internal impedance matching circuit - Google Patents

Ansistor equipped with internal impedance matching circuit

Info

Publication number
JPS61208854A
JPS61208854A JP5090685A JP5090685A JPS61208854A JP S61208854 A JPS61208854 A JP S61208854A JP 5090685 A JP5090685 A JP 5090685A JP 5090685 A JP5090685 A JP 5090685A JP S61208854 A JPS61208854 A JP S61208854A
Authority
JP
Japan
Prior art keywords
impedance matching
circuit
conductor
dielectric substrate
matching circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5090685A
Other languages
Japanese (ja)
Inventor
Hiroyuki Anraku
安楽　広之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5090685A priority Critical patent/JPS61208854A/en
Publication of JPS61208854A publication Critical patent/JPS61208854A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To improve the linearity of input/output characteristics, by providing the impedance matching circuit of thin film constituted on the dielectric substrate and shielding electromagnetically the impedance matching circuit with the conductive cap stuck to the grounded conductor on the side surface of the dielectric substrate. CONSTITUTION:The transmission line formed with the thin film and the impedance matching circuit 2 constituted of the open stub, etc. are formed on the dielectric substrate 1. The whole part of the circuit 2 except the input and output terminals is covered with a conductive cap 3 made of metal, etc. At the contact part with the circuit 2 and its neighboring part, the cap 3 covers the circuit 2 through the insulative dielectric material 5 such as Teflon, etc., so that the circuit 2 and the cap 3 never directly contact with each other. the conductor 4c on the upper surface of the dielectric substrate 1 is electrically connected to the whole surface conductor 4a on the back side through the conductor 4b on the side surface of the dielectric substrate 1, and the cap 3 is soldered to the conductor 4c. Thus, the satisfactory input/output impedance and the RF characteristics are obtained, and especially the linearity can be effectively improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロ波高出力トランジスタ、特にその内部
に設けられる内部インピーダンス整合回路（以下ＩＭＮ
と略す）ＶＣｌＴｈするものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microwave high output transistor, particularly an internal impedance matching circuit (hereinafter referred to as IMN) provided inside the transistor.
(abbreviated as )VClTh.

〔従来の技術〕[Conventional technology]

第６図に従来のＩＭＮの一例の平面図を示す。 FIG. 6 shows a plan view of an example of a conventional IMN.

第７図はそのＡ−Ａ’断面図である。アルミナセラミッ
クなどの［Ｃ体基板２１上に薄膜で形成された伝送線路
オープンスタブなどからなるインピーダンス整合用回路
２２が構成されている。裏面には金楓導体２３が全面に
蒸着されている。FIG. 7 is a sectional view taken along the line AA'. An impedance matching circuit 22 is constructed of a transmission line open stub formed of a thin film on a C body substrate 21 made of alumina ceramic or the like. A gold maple conductor 23 is deposited on the entire back surface.

第８図は半導体素子用容器（以下パッケージと略す）へ
の前記１ＭＮ基板の搭載例の平面図である。また、第９
図は第８図のＢ−Ｂ／断面図である。第６図、第７図に
示したＩＭＮ基板２５ａ。FIG. 8 is a plan view of an example of mounting the 1MN substrate on a semiconductor element container (hereinafter abbreviated as package). Also, the 9th
The figure is a BB/sectional view of FIG. IMN board 25a shown in FIGS. 6 and 7.

２５ｂ及びマイクロ波高出力トランジスタ２６をパッケ
ージ２４上に搭載している。入出力のリード端子２７と
ＩＭＮ基板２５ａ、２５ｂとの間及びＩＭＮ基板２５ａ
　、２５ｂとマイクロ波トランジスタ２６との間は、ボ
ンディング用ワイヤ２９で接続されている。また、リー
ド端子２７とパッケージ２４（本実施例では金属導体で
形成されている）との間は、アルミナセラミックやガラ
ス質の絶縁物２８で電気的に絶縁されている。25b and a microwave high output transistor 26 are mounted on the package 24. Between the input/output lead terminals 27 and the IMN boards 25a and 25b, and the IMN board 25a
, 25b and the microwave transistor 26 are connected by a bonding wire 29. Further, the lead terminal 27 and the package 24 (made of a metal conductor in this embodiment) are electrically insulated by an insulator 28 made of alumina ceramic or glass.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のＩＭＮはＩＭＮ基板５ａ、５ｂ上のイン
ピーダンス整合用回路２２がパッケージ２４内でむき出
しになっておシ、入力側ＩＭＮ基板２５ａと出力１１１
１ＭＮ基板２５ｂとの間の電磁波の放射や電磁誘導など
による電磁気的影響（以下カップリングと略す）は避け
られず、このことがパッケージの外部から見た入出力イ
ンピーダンスの悪化また、ＲＦ％性のうち特に、入出力
特性の線形性に悪影響を及ぼすという欠点があった。In the conventional IMN described above, the impedance matching circuit 22 on the IMN boards 5a and 5b is exposed inside the package 24, and the input side IMN board 25a and the output 111 are exposed.
Electromagnetic effects (hereinafter referred to as coupling) due to electromagnetic wave radiation and electromagnetic induction between the 1MN board 25b and the Among these, there was a particular drawback in that it adversely affected the linearity of input/output characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれは、パッケージ内に設けられた内部インピ
ーダンス整合回路は誘電体基板上に構成された薄膜回路
のインピーダンス整合回路を有し、誘電体基板表面の側
部には側面を通して接地された接地導体を有し、この接
地導体に接着された導電性のふたでインピーダンス整合
回路を電磁気的に遮へいした構造を有している。According to the present invention, the internal impedance matching circuit provided in the package has a thin film impedance matching circuit configured on a dielectric substrate, and the side of the surface of the dielectric substrate is grounded through the side surface. It has a structure in which the impedance matching circuit is electromagnetically shielded by a conductive lid bonded to the ground conductor.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の平面図であ）、第２図は
そのＡ−Ａ’断面図であシ、また、第３図は第１図のａ
−ａ’断面図である。FIG. 1 is a plan view of one embodiment of the present invention), FIG. 2 is a cross-sectional view taken along line A-A', and FIG.
-a' sectional view.

誘電体基板１上には、薄膜で形成された伝送線路及びオ
ープンスタブなどからなるインピーダンス整合用の回路
２が構成されている。回路２の入出力端以外の部分は、
金属など導電製のふた３がかぶせられている。このふた
３は回路２との接触部分及びその付近では、テフロンな
ど絶縁性のある誘電体５を介して回路２をおおっておシ
、回路２とふ７’Ｃ３が直接に接触しない構造になって
いる。On the dielectric substrate 1, an impedance matching circuit 2 is constructed, which includes a transmission line formed of a thin film, an open stub, and the like. The parts other than the input and output terminals of circuit 2 are
A lid 3 made of conductive material such as metal is covered. This lid 3 covers the circuit 2 through an insulating dielectric material 5 such as Teflon at the contact part with the circuit 2 and its vicinity, and has a structure that prevents direct contact between the circuit 2 and the lid 7'C3. ing.

また、誘電体基板１の上面（回路２と同一面）上の導体
４ｃは誘電体基板１の物面の導体４ｂを通じて裏面の全
面導体４ａと電気的に接続されており、ふた３は導体４
ｃ上に１０−付けされている。Further, the conductor 4c on the upper surface of the dielectric substrate 1 (same surface as the circuit 2) is electrically connected to the full-surface conductor 4a on the back surface through the conductor 4b on the object surface of the dielectric substrate 1, and the lid 3 is connected to the conductor 4a on the back surface.
10- is added on c.

これによシふた３は、接地されていることになる。This means that the lid 3 is grounded.

また、誘電体基板１に面において回路２と導体４Ｃは電
気的に絶縁されている。Furthermore, the circuit 2 and the conductor 4C are electrically insulated from each other on the dielectric substrate 1.

第４図は、本発明の一実施例のパッケージへの搭載例の
平面図であ勺、第５図はそのＢ−Ｂ／断面図である。前
記ＩＭＮ基板の実施例５ａ、６ｂ及びマイクロ波高出力
トランジスタ７をパッケージ８上に搭載している。パッ
ケージのリード端子９とＩＭＮ基板５ａ、５ｂとの間及
びＩＭＮ基板６ａ、６ｂとマイクロ波高出力トランジス
タ７との間はポンディング用ワイヤ１０で電気的に接続
されている。FIG. 4 is a plan view of an example of mounting an embodiment of the present invention on a package, and FIG. 5 is a BB/sectional view thereof. Examples 5a and 6b of the IMN substrate and the microwave high output transistor 7 are mounted on a package 8. A bonding wire 10 is electrically connected between the lead terminal 9 of the package and the IMN substrates 5a, 5b, and between the IMN substrates 6a, 6b and the microwave high output transistor 7.

前述のような構造をもつＩＭＮ基板６ａ、６ｂは、回路
２がふた３及び誘電体基板１で電磁気的に遮へいされて
いるため、ＩＭＮ基板６ａ、６ｂの外部からの電磁気的
な影響を最少限に抑えることが可能となる。特に１入出
力ＩＭＮ基板５ａ。In the IMN boards 6a and 6b having the above-described structure, the circuit 2 is electromagnetically shielded by the lid 3 and the dielectric substrate 1, so that the electromagnetic influence from the outside of the IMN boards 6a and 6b is minimized. It is possible to suppress the Especially the 1 input/output IMN board 5a.

６ｂ相互の電磁気的影響を最少限に抑えることＫよシ、
パッケージの外から見た入出力インピーダンス及びＲＦ
％性のうち線形性の改善に効果がある。6b To minimize mutual electromagnetic influence,
Input/output impedance and RF seen from outside the package
It is effective in improving linearity among percentage characteristics.

〔発明の効果〕〔Effect of the invention〕

以上説明したように１本発明は、ＩＭＮ基板外部からの
ＩＭＮ基板上の回路への電磁気的影響を、Ｉ−ＭＮ基板
上の回路を金属など導体でつくられたふたをかぶせるこ
とにより最少限に抑えられ、良好な入出力イン、ピーダ
ンス及びＲＦ特性のうち特に線形性の改善に効果を上げ
ることができる。As explained above, the present invention minimizes the electromagnetic influence on the circuits on the IMN board from outside the IMN board by covering the circuits on the I-MN board with a lid made of a conductor such as metal. Among the input/output input, pedance, and RF characteristics, it is particularly effective in improving linearity.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に用いる内部インピーダンス
整合回路基板の平面図、第２図はその人＋　Ａ　／断面
図、第３図はａ−ａ′断面図である。 第４図は本発明の一実施例を示した平面図で、第５図は
そのＢ−Ｂ／断面図である。第６図は従来の内部インピ
ーダンス整合回路基板の平面図、第７図社そのＡ−Ａ’
断面図である。第８図は従来のマイクロ波高出力トラン
ジスタの平面図で、第９図はそのＢ−Ｂ／断面図である
。 １・・・・・・誘電体基板、２・・・・・・薄膜回路（
インピーダンス整合用回路）、３・・・・・・シールド
用導電性ふ７’ｃ、４ａ・・・・・・金属導体（裏面）
、４ｂ・・・・・・金属導体（表面）、５・・・・・・
誘電体、６　ａ　ｔ　６　ｂ・・・・・・内部インピー
ダンス整合用回路基板、７・・・・・・マイクロ波高出
力トランジスタ、８・・・・・・半導体容器、９・・・
・・・リード端子、１０・・・・・・ボンディング用ワ
イヤ、１１・・・・・・絶縁物、２１・・・・・・誘電
体基板、２２・・・・・・薄膜回路（インピーダンス整
合用回路）、２３・・・・・・金属導体、２４・・・・
・・半導体容器、２５ａ、２５ｂ・・・・・・内部イン
ピーダンス整合用回路基板、２６・・・・・・マイクロ
波高出力トランジスタ、２７・・・・・・リード端子、
２８・・・・・・絶縁物、２９・・・・・・ボンディン
グ用ワイヤ。 革１Ｍ 茅４　ｍFIG. 1 is a plan view of an internal impedance matching circuit board used in an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line A-A, and FIG. 3 is a cross-sectional view taken along line a-a'. FIG. 4 is a plan view showing one embodiment of the present invention, and FIG. 5 is a BB/sectional view thereof. Figure 6 is a plan view of a conventional internal impedance matching circuit board, Figure 7 is A-A'
FIG. FIG. 8 is a plan view of a conventional microwave high output transistor, and FIG. 9 is a BB/sectional view thereof. 1... Dielectric substrate, 2... Thin film circuit (
Impedance matching circuit), 3... Conductive wire for shielding 7'c, 4a... Metal conductor (back side)
, 4b...metal conductor (surface), 5...
Dielectric, 6 a t 6 b... Internal impedance matching circuit board, 7... Microwave high output transistor, 8... Semiconductor container, 9...
... Lead terminal, 10 ... Bonding wire, 11 ... Insulator, 21 ... Dielectric substrate, 22 ... Thin film circuit (impedance matching circuit), 23...metal conductor, 24...
... Semiconductor container, 25a, 25b ... Internal impedance matching circuit board, 26 ... Microwave high output transistor, 27 ... Lead terminal,
28... Insulator, 29... Bonding wire. Leather 1m, grass 4m

Claims (1)

【特許請求の範囲】[Claims] 裏面が全面導体となっている誘電体基板上にインピーダ
ンス整合用の薄膜回路が形成され、前記薄膜回路の上を
おおうように、導電性のふたがかぶせられており、前記
導電性ふたは接地されている内部インピーダンス整合回
路を備えたことを特徴とする内部インピーダンス整合回
路付トランジスタ。A thin film circuit for impedance matching is formed on a dielectric substrate whose back surface is entirely conductive, and a conductive lid is placed over the thin film circuit, and the conductive lid is grounded. A transistor with an internal impedance matching circuit, characterized in that it is equipped with an internal impedance matching circuit.
JP5090685A 1985-03-14 1985-03-14 Ansistor equipped with internal impedance matching circuit Pending JPS61208854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5090685A JPS61208854A (en) 1985-03-14 1985-03-14 Ansistor equipped with internal impedance matching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5090685A JPS61208854A (en) 1985-03-14 1985-03-14 Ansistor equipped with internal impedance matching circuit

Publications (1)

Publication Number Publication Date
JPS61208854A true JPS61208854A (en) 1986-09-17

Family

ID=12871805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5090685A Pending JPS61208854A (en) 1985-03-14 1985-03-14 Ansistor equipped with internal impedance matching circuit

Country Status (1)

Country Link
JP (1) JPS61208854A (en)

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