WO2019207657A1 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

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Publication number
WO2019207657A1
WO2019207657A1 PCT/JP2018/016665 JP2018016665W WO2019207657A1 WO 2019207657 A1 WO2019207657 A1 WO 2019207657A1 JP 2018016665 W JP2018016665 W JP 2018016665W WO 2019207657 A1 WO2019207657 A1 WO 2019207657A1
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Prior art keywords
insulating layer
semiconductor device
conductor film
ground
semiconductor
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PCT/JP2018/016665
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French (fr)
Japanese (ja)
Inventor
高橋　貴紀
良洋 塚原
加藤　隆幸
勝巳 宮脇
慶一 川嶋
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三菱電機株式会社
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Priority to PCT/JP2018/016665 priority Critical patent/WO2019207657A1/en
Publication of WO2019207657A1 publication Critical patent/WO2019207657A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • Patent Document 1 discloses a semiconductor device having a fan-out terminal structure in which an arrangement region of external connection electrodes is larger than a planar size of a semiconductor structure.
  • the semiconductor structure is mounted on the upper surface of the lower insulating film, and the sealing film is formed on the upper surface of the semiconductor structure.
  • a sealing film such as a mold resin has a property of passing electromagnetic waves.
  • FOWLP Fe Out Wafer Level Package
  • Patent Document 1 As a method for providing an electromagnetic shield, it is conceivable to solder a shield part manufactured by pressing from a conductor plate around the package of the substrate after the package is mounted on the substrate. As another method, it is conceivable that the shield component is mechanically brought into contact with the contact mounted on the substrate.
  • the shield component when a plurality of parts are close to each other, it may be difficult to attach the shield part. Further, the mounting area may be increased due to the shield component.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device and a method of manufacturing the semiconductor device that can easily form an electromagnetic shield.
  • a semiconductor device includes an insulating layer, a semiconductor chip provided on the upper surface of the insulating layer, an upper surface and a side surface of the semiconductor chip, and a portion of the upper surface of the insulating layer exposed from the semiconductor chip.
  • a conductive film covering the upper surface of the conductive film, a conductive bump provided on the back surface of the insulating layer, a grounding bump provided on the back surface of the insulating layer, and the insulating layer A first contact connecting the semiconductor chip and the conductive bump, and a ground contact connecting the conductive film and the ground bump through the insulating layer from the upper surface to the back surface.
  • the conductor film covers the upper surface of the insulating layer to the end.
  • a method of manufacturing a semiconductor device includes mounting a plurality of semiconductor chips on an upper surface of an insulating layer, and exposing a top surface and side surfaces of the plurality of semiconductor chips and an upper surface of the insulating layer from the semiconductor chip.
  • a conductor film the upper surface of the conductor film is covered with a sealing body, the insulating layer is penetrated from the upper surface to the back surface, and a plurality of second chips connected to the plurality of semiconductor chips on the upper surface side of the insulating layer.
  • an electromagnetic shield is formed by covering the semiconductor chip and the insulating layer with a conductor film.
  • the sealing body covers the conductor film. For this reason, it is not necessary to form an electromagnetic shield after chip separation, and the electromagnetic shield can be easily formed.
  • the semiconductor chip and the insulating layer are covered with a conductor film, and after forming an electromagnetic shield, the conductor film is covered with a sealing body. For this reason, it is not necessary to form an electromagnetic shield after chip separation, and the electromagnetic shield can be easily formed.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is a figure which shows the state which covered the several semiconductor chip with the conductor film. It is a figure which shows the state which covered the upper surface of the conductor film with the sealing body. It is a figure which shows the state which removed the base board. It is a figure which shows the state which formed the 1st contact and the contact for grounding. It is a figure which shows the state which formed the terminal wiring and the wiring for grounding. It is a figure which shows the state which formed the conductive bump and the bump for grounding. It is a figure explaining a cutting process. 4 is a cross-sectional view of a semiconductor device according to a comparative example of the first embodiment. FIG. FIG. FIG.
  • FIG. 10 is a bottom view of a semiconductor device according to a first modification example of the first embodiment.
  • FIG. 10 is a bottom view of a semiconductor device according to a second modification example of the first embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 6 is a bottom view of a semiconductor device according to a second embodiment.
  • a semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
  • the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
  • FIG. 1 is a cross-sectional view of the semiconductor device 100 according to the first embodiment.
  • the semiconductor device 100 is FOWLP.
  • the semiconductor device 100 includes an insulating layer 10.
  • a plurality of semiconductor chips 12 are provided on the upper surface of the insulating layer 10.
  • the semiconductor device 100 may include one or more semiconductor chips 12.
  • the area of the region where the semiconductor chip 12 is mounted is smaller than the area of the package.
  • the electrical contacts of the semiconductor chip 12 are extended from the semiconductor chip 12 onto the package.
  • a conductor film 14 is provided on the plurality of semiconductor chips 12.
  • the conductor film 14 covers the upper surface and side surfaces of the semiconductor chip 12 and the portion of the upper surface of the insulating layer 10 exposed from the semiconductor chip 12.
  • the conductor film 14 covers the upper surface of the insulating layer 10 to the end.
  • the entire area of the upper surface of the insulating layer 10 exposed from the semiconductor chip 12 is covered with the conductor film 14.
  • the entire surface of the semiconductor chip 12 other than the surface having electrical contacts is covered with the conductor film 14.
  • the upper surface of the conductor film 14 is covered with the sealing body 16.
  • the sealing body 16 is formed from mold resin. By sealing the package with the sealing body 16, the strength of the package can be maintained.
  • the sealing body 16 constitutes the body of the package.
  • the back side of the insulating layer 10 is a mounting surface on which electrical contacts of the package are provided.
  • the semiconductor device 100 includes a first contact 18 that penetrates the insulating layer 10 from the top surface to the back surface. The upper end of the first contact 18 is connected to the back electrode of the semiconductor chip 12.
  • the semiconductor device 100 also includes a ground contact 20 that penetrates the insulating layer 10 from the upper surface to the back surface. The upper end of the ground contact 20 is connected to the conductor film 14.
  • the first contact 18 and the ground contact 20 are provided to form an electrical contact between the semiconductor chip 12 and the external substrate.
  • Conductive bumps 26 and grounding bumps 28 are provided on the back surface of the insulating layer 10.
  • the conductive bumps 26 and the ground bumps 28 are solder bumps that connect the package and the external substrate.
  • An under bump metal 24 is provided on the conductive bump 26.
  • Terminal wiring 22 is provided on the under bump metal 24. The upper surface of the terminal wiring 22 is connected to the lower end of the first contact 18. As described above, the first contact 18 connects the semiconductor chip 12 and the conductive bump 26 via the terminal wiring 22 and the under bump metal 24.
  • the under bump metal 24 is provided on the ground bump 28.
  • a ground wiring 21 is provided on the under bump metal 24.
  • the upper surface of the ground wiring 21 is connected to the lower end of the ground contact 20. In this way, the ground contact 20 connects the conductor film 14 and the ground bump 28 via the ground wiring 21 and the under bump metal 24.
  • the semiconductor device 100 also includes a ground terminal contact 19 that penetrates the insulating layer 10 from the upper surface to the back surface.
  • the upper end of the ground terminal contact 19 is connected to the ground electrode of the semiconductor chip 12.
  • the lower end of the ground terminal contact 19 is connected to the ground bump 28 via the ground wiring 21 and the under bump metal 24.
  • the ground bump 28 is electrically connected to the ground terminal of the semiconductor chip 12.
  • the conductor film 14 is connected to the grounding electrode of the semiconductor chip 12 through the grounding contact 20, the grounding wiring 21 and the grounding terminal contact 19.
  • FIG. 2 is a view showing a state in which a plurality of semiconductor chips 12 are covered with a conductor film 14.
  • the conductor film 14 is formed, for example, by vapor deposition, plating, or pasting.
  • FIG. 3 is a view showing a state in which the upper surface of the conductor film 14 is covered with the sealing body 16.
  • the mold resin covers the entire region opposite to the mounting surface of the package.
  • the base plate 30 is removed.
  • FIG. 4 is a view showing a state in which the base plate 30 is removed.
  • FIG. 5 is a diagram showing a state in which the first contact 18 and the ground contact 20 are formed.
  • the plurality of first contacts 18 are formed so as to penetrate the insulating layer 10 from the top surface to the back surface and be connected to the plurality of semiconductor chips 12 on the top surface side of the insulating layer 10.
  • the plurality of grounding contacts 20 are formed so as to penetrate the insulating layer 10 from the upper surface to the rear surface and be connected to the conductor film 14 on the upper surface side of the insulating layer 10.
  • FIG. 6 is a diagram showing a state in which the terminal wiring 22 and the grounding wiring 21 are formed.
  • an inter-chip wiring that connects the plurality of semiconductor chips 12 may be formed.
  • FIG. 7 is a diagram showing a state in which the conductive bumps 26 and the ground bumps 28 are formed.
  • FIG. 8 is a diagram illustrating the cutting process.
  • the sealing body 16, the conductor film 14, and the insulating layer 10 are cut between the plurality of semiconductor chips 12.
  • the cutting is performed by, for example, a dicer. Thereby, the semiconductor device 100 is separated into pieces.
  • the entire region of the upper surface of the insulating layer 10 exposed from the semiconductor chip 12 is covered with the conductor film 14.
  • the conductor film 14 covers the upper surface of the insulating layer 10 to the end.
  • the conductor film 14 is exposed from the side surface of the package. In the package, the entire region above the portion of the side surface where the conductor film 14 is exposed and the entire upper surface are formed from the sealing body 16.
  • a fixing material may be provided on the base plate 30 instead of the insulating layer 10.
  • the fixing material is a material that can fix the semiconductor chip 12.
  • the fixing material is also removed.
  • the insulating layer 10 is formed on the back surfaces of the semiconductor chip 12 and the conductor film 14.
  • FIG. 9 is a cross-sectional view of a semiconductor device 800 according to a comparative example of the first embodiment.
  • the semiconductor device 800 is not provided with the conductor film 14, the ground contact 20, the ground wiring 21, the ground terminal contact 19, and the ground bump 28.
  • Other configurations are the same as those of the semiconductor device 100 of the present embodiment.
  • As a method of providing an electromagnetic shield in the semiconductor device 800 it is conceivable to attach a shield part outside the package or form a metal film outside the package after the cutting process.
  • the conductor film 14 serves as an electromagnetic shield.
  • the ground bump 28 is connected to the ground terminal of the external substrate, whereby the conductor film 14 formed around the semiconductor chip 12 is grounded. At this time, the potential of the conductor film 14 is grounded to the GND potential of the semiconductor chip 12 or the external substrate. For this reason, even if electromagnetic waves are irradiated from the outside, it can suppress that the electric potential around the semiconductor chip 12 fluctuates. Therefore, it is possible to prevent the circuit inside the semiconductor chip 12 from being affected by external electromagnetic waves.
  • the electromagnetic wave generated by the semiconductor chip 12 can be prevented from leaking to the outside because the potential of the conductor film 14 is grounded to the GND potential. Therefore, the electromagnetic waves generated by the semiconductor chip 12 can be prevented from affecting the external circuit.
  • each semiconductor chip 12 the entire upper surface and side surfaces of each semiconductor chip 12 are covered with the conductor film 14. For this reason, a higher electromagnetic shielding effect can be expected than a structure in which a shield part or a metal film is provided outside the package. In addition, the influence of electromagnetic waves between the plurality of semiconductor chips 12 in the semiconductor device 100 can be suppressed.
  • the conductor film 14 may be formed over the entire area on the insulating layer 10 and the semiconductor chip 12 before the cutting step. Therefore, an electromagnetic shield can be easily formed. For this reason, manufacturing cost can be suppressed. Further, it is not necessary to add a process for forming an electromagnetic shield after the cutting process. Therefore, it is possible to maintain the merit of FOWLP that the productivity is improved by forming the package structure in the wafer state.
  • the manufacturing method of the present embodiment is the same as the manufacturing process of the semiconductor device 800 according to the comparative example except that the conductive film 14 is formed. For this reason, FOWLP having a shield structure can be realized at low cost.
  • the electromagnetic shield is formed by the conductor film 14 inside the package, it is not necessary to attach a shield component to the outside of the package. Therefore, it is possible to improve the degree of freedom of component placement on the mounting board. In addition, the mounting board can be reduced in size.
  • the conductive film 14 is provided between the semiconductor chip 12 and the sealing body 16 so that an electromagnetic shield is formed. Since the conductor film 14 is covered with the sealing body 16, the conductor film 14 can be protected from scratches during handling. Accordingly, it is possible to prevent a decrease in shielding performance due to damage to the conductor film 14.
  • the upper surface and side surfaces of the semiconductor chip 12 and the upper surface of the insulating layer 10 may be partially exposed from the conductor film 14.
  • the conductive bumps 26 and the ground bumps 28 are not limited to solder bumps, and may be gold bumps.
  • the sealing body 16 may be conductive.
  • a conductive sealing body may affect high frequency characteristics. For this reason, a conductive sealing body is often not suitable for a package that handles high frequencies.
  • the sealing body 16 can be formed of a conductive material.
  • conductive materials have low thermal resistance and high heat dissipation performance. Therefore, both high heat dissipation performance and good high frequency characteristics can be achieved.
  • the sealing body may absorb radio waves.
  • a material that absorbs radio waves may affect high-frequency characteristics, and thus is often not suitable for use in a sealed body.
  • the sealing body 16 since the electrical property of the sealing body 16 is shielded by the conductor film 14, the influence on the high frequency characteristic of the sealing body 16 can be suppressed. Therefore, the sealing body 16 can be formed of a material that absorbs radio waves. Thereby, FOWLP with higher shield performance can be obtained.
  • ground bump 28 and the ground terminal of the semiconductor chip 12 may not be electrically connected.
  • the ground contact 20 and the ground terminal of the semiconductor chip 12 are separated on the package.
  • the grounding contact 20 and the grounding terminal of the semiconductor chip 12 are electrically connected to each other on the mounting board. According to this configuration, even when the number of grounding contacts 20 cannot be sufficiently secured and the impedance cannot be lowered sufficiently, or when the sensitivity of the grounding terminal of the semiconductor chip 12 is very high, etc., good shielding characteristics. You can also get
  • FIG. 10 is a bottom view of the semiconductor device 200 according to the first modification of the first embodiment.
  • FIG. 10 is a view of the semiconductor device 200 as viewed from the mounting surface side.
  • the semiconductor device 200 is different from the semiconductor device 100 in the arrangement of the plurality of conductive bumps 26 and the plurality of ground bumps 28.
  • the plurality of ground bumps 28 are provided on the outer periphery of the package.
  • the plurality of conductive bumps 26 are provided at the center of the package.
  • the plurality of ground bumps 28 surround the plurality of conductive bumps 26.
  • a plurality of grounding contacts 20 are provided on the outer periphery of the package.
  • the plurality of grounding contacts 20 and the plurality of grounding bumps 28 are alternately arranged on the outer periphery of the package. Note that, on the mounting surface side of the semiconductor device 200, the plurality of ground contacts 20 are covered with the ground wiring 221. In FIG. 10, the position of the ground contact 20 is shown for convenience.
  • the ground wiring 221 surrounds the plurality of conductive bumps 26 at the outer peripheral portion of the package.
  • the plurality of conductive bumps 26 include signal bumps 26a to which high-frequency signals are input or output.
  • the signal bump 26a is connected to the ground contact 20 by a matching circuit.
  • a plurality of semiconductor chips 12 are provided at the center of the package.
  • the ground wiring 221, the ground bump 28, and the ground contact 20 surround a region where the semiconductor chip 12 is provided.
  • the plurality of grounding contacts 20, the plurality of grounding bumps 28, and the grounding wiring 221 are laid out so as to surround the semiconductor chip 12 and the signal bumps 26a.
  • the semiconductor chip 12 and the signal bump 26 a are separated from the outside by a ground wiring 221. Thereby, the shielding effect can be further improved.
  • FIG. 11 is a bottom view of the semiconductor device 300 according to the second modification of the first embodiment.
  • the ground wiring 321 may be interrupted at the outer periphery of the package according to the required performance of the electromagnetic shield.
  • a signal bump 26a is disposed in a portion where the ground wiring 321 is interrupted.
  • FIG. FIG. 12 is a cross-sectional view of the semiconductor device 400 according to the second embodiment.
  • the conductor film 14 has an insulating layer covering portion 14 a that covers the upper surface of the insulating layer 10 between the plurality of semiconductor chips 12.
  • the insulating layer covering portion 14 a is in contact with the upper surface of the insulating layer 10.
  • an inter-chip wiring 423 a is provided directly below the insulating layer covering portion 14 a.
  • the semiconductor device 400 includes a plurality of second contacts 425 that penetrate the insulating layer 10 from the top surface to the back surface.
  • the plurality of second contacts 425 connect the inter-chip wiring 423a and the plurality of semiconductor chips 12, respectively.
  • the plurality of semiconductor chips 12 are connected to the plurality of second contacts 425 by inter-chip wiring 423a.
  • the plurality of second contacts 425 and the inter-chip wiring 423 a connect the signal output terminal of one semiconductor chip 12 and the signal input terminal of the other semiconductor chip 12.
  • the inter-chip wiring 423a serves as a high-frequency signal line.
  • the interchip wiring 423a, the insulating layer 10, and the conductor film 14 form a microstrip line.
  • FIG. 13 is a bottom view of the semiconductor device 400 according to the second embodiment.
  • the ground wiring 221, the ground bump 28, and the ground contact 20 are provided so as to surround the plurality of semiconductor chips 12.
  • the plurality of semiconductor chips 12 are connected to each other by the wiring 423b.
  • the wiring 423 b is connected to the ground contact 20.
  • the plurality of semiconductor chips 12 are covered with the insulating layer 10.
  • the position of the semiconductor chip 12 is shown for convenience.
  • the conductive bumps 26 are omitted.
  • the width of the interchip wiring 423a is set so that the interchip wiring 423a, the insulating layer 10, and the conductor film 14 form a microstrip line.
  • the signal line width of the inter-chip wiring 423a is set to an optimum value according to the thickness of the insulating layer 10 and the dielectric constant.
  • the wiring thickness is determined in consideration of the current capacity and the like according to the package wiring design rules.
  • the microstrip line is formed using the conductor film 14 which is an electromagnetic shield. Thereby, it is possible to configure a transmission line having a suitable characteristic impedance. Therefore, wiring loss between chips can be suppressed and the performance of the semiconductor device 400 can be improved.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device according to the present invention includes: an insulating layer; a semiconductor chip provided on the top surface of the insulating layer; a conductor film that covers the top surface and side surfaces of the semiconductor chip and a portion of the top surface of the insulating layer that is exposed from the semiconductor chip; a seal that covers the top surface of the conductor film; a conductive bump that is provided on the rear surface of the insulating layer; a ground bump that is provided on the rear surface of the insulating layer; a first contact that passes through the insulating layer from the top surface to the rear surface and connects the semiconductor chip to the conductive bump; and a ground contact that passes through the insulating layer from the top surface to the rear surface and connects the conductor film to the ground bump. The conductor film covers the top surface of the insulating layer to the edges.

Description

半導体装置および半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　この発明は、半導体装置および半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
　特許文献１には、外部接続用電極の配置領域が半導体構成体の平面サイズよりも大きいファンアウト端子構造を有する半導体装置が開示されている。この半導体装置では、下層絶縁膜の上面に半導体構成体が搭載され、半導体構成体の上面に封止膜が形成される。 Patent Document 1 discloses a semiconductor device having a fan-out terminal structure in which an arrangement region of external connection electrodes is larger than a planar size of a semiconductor structure. In this semiconductor device, the semiconductor structure is mounted on the upper surface of the lower insulating film, and the sealing film is formed on the upper surface of the semiconductor structure.
日本特開２０１１－６６４５４号公報Japanese Unexamined Patent Publication No. 2011-66454
　一般に、モールド樹脂等の封止膜は電磁波を通過させる特性がある。このため、特許文献１に示されるようなＦＯＷＬＰ（Ｆａｎ　Ｏｕｔ　Ｗａｆｅｒ　Ｌｅｖｅｌ　Ｐａｃｋａｇｅ）に対し、電磁シールドを設ける必要が生じる場合がある。電磁シールドを設ける方法として、パッケージを基板に実装した後に、基板のパッケージ周辺に導体板からプレス等で製造したシールド部品をはんだ付けすることが考えられる。また、別の方法として、基板上に実装された接点に、シールド部品を機械的に接触させることが考えられる。しかし上記の方法では、複数の部品が近接する場合に、シールド部品を取り付けることが困難となる可能性がある。また、シールド部品により実装面積が大きくなるおそれがある。 Generally, a sealing film such as a mold resin has a property of passing electromagnetic waves. For this reason, it may be necessary to provide an electromagnetic shield for FOWLP (Fan Out Wafer Level Package) as shown in Patent Document 1. As a method for providing an electromagnetic shield, it is conceivable to solder a shield part manufactured by pressing from a conductor plate around the package of the substrate after the package is mounted on the substrate. As another method, it is conceivable that the shield component is mechanically brought into contact with the contact mounted on the substrate. However, in the above method, when a plurality of parts are close to each other, it may be difficult to attach the shield part. Further, the mounting area may be increased due to the shield component.
　この問題を解決する方法として、パッケージの周囲に導体膜を形成し、半導体部品単体でシールド構造を実現することが考えられる。しかし、この方法ではチップ個片化後に追加の金属膜形成工程が必要となる。このため、ウエハ状態でパッケージ構造を形成することにより生産性を向上できるＦＯＷＬＰのメリットが阻害される。また、製造コストが増大する可能性がある。また、薄い金属膜で形成されたシールド構造では、ハンドリング時の傷によりシールド性能が低下するおそれがある。また、シールドの接地用電極がパッケージ外周部に限られるため、十分なシールド性能が得られない可能性がある。 As a method for solving this problem, it is conceivable to form a conductor film around the package and realize a shield structure with a single semiconductor component. However, this method requires an additional metal film forming step after chip separation. For this reason, the merit of FOWLP which can improve productivity by forming a package structure in a wafer state is hindered. In addition, the manufacturing cost may increase. Further, in a shield structure formed of a thin metal film, the shield performance may be deteriorated due to scratches during handling. Further, since the shield grounding electrode is limited to the outer periphery of the package, there is a possibility that sufficient shielding performance cannot be obtained.
　本発明は上述の問題を解決するためになされたものであり、その目的は、容易に電磁シールドを形成できる半導体装置および半導体装置の製造方法を得ることである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device and a method of manufacturing the semiconductor device that can easily form an electromagnetic shield.
　本願の発明に係る半導体装置は、絶縁層と、該絶縁層の上面に設けられた半導体チップと、該半導体チップの上面および側面と、該絶縁層の上面のうち該半導体チップから露出した部分と、を覆う導体膜と、該導体膜の上面を覆う封止体と、該絶縁層の裏面に設けられた導電性バンプと、該絶縁層の裏面に設けられた接地用バンプと、該絶縁層を上面から裏面に貫通し、該半導体チップと該導電性バンプとを接続する第１コンタクトと、該絶縁層を上面から裏面に貫通し、該導体膜と該接地用バンプとを接続する接地用コンタクトと、を備え、該導体膜は、該絶縁層の上面を端部まで覆う。 A semiconductor device according to the present invention includes an insulating layer, a semiconductor chip provided on the upper surface of the insulating layer, an upper surface and a side surface of the semiconductor chip, and a portion of the upper surface of the insulating layer exposed from the semiconductor chip. A conductive film covering the upper surface of the conductive film, a conductive bump provided on the back surface of the insulating layer, a grounding bump provided on the back surface of the insulating layer, and the insulating layer A first contact connecting the semiconductor chip and the conductive bump, and a ground contact connecting the conductive film and the ground bump through the insulating layer from the upper surface to the back surface. And the conductor film covers the upper surface of the insulating layer to the end.
　本願の発明に係る半導体装置の製造方法は、絶縁層の上面に複数の半導体チップを搭載し、該複数の半導体チップの上面および側面と、該絶縁層の上面のうち該半導体チップから露出した部分と、を導体膜で覆い、該導体膜の上面を封止体で覆い、該絶縁層を上面から裏面まで貫通し、該絶縁層の上面側で該複数の半導体チップと接続される複数の第１コンタクトを形成し、該絶縁層を上面から裏面まで貫通し、記絶縁層の上面側で該導体膜と接続される複数の接地用コンタクトを形成し、該絶縁層の裏面に、該複数の第１コンタクトと接続される複数の導電性バンプを形成し、該絶縁層の裏面に、該複数の接地用コンタクトと接続される複数の接地用バンプを形成し、該複数の導電性バンプと該複数の接地用バンプを形成した後に、該封止体と、該導体膜と、該絶縁層と、を該複数の半導体チップの間で切断する。 A method of manufacturing a semiconductor device according to the present invention includes mounting a plurality of semiconductor chips on an upper surface of an insulating layer, and exposing a top surface and side surfaces of the plurality of semiconductor chips and an upper surface of the insulating layer from the semiconductor chip. Are covered with a conductor film, the upper surface of the conductor film is covered with a sealing body, the insulating layer is penetrated from the upper surface to the back surface, and a plurality of second chips connected to the plurality of semiconductor chips on the upper surface side of the insulating layer. Forming one contact, penetrating the insulating layer from the top surface to the back surface, forming a plurality of ground contacts connected to the conductor film on the top surface side of the insulating layer, and forming the plurality of contacts on the back surface of the insulating layer; A plurality of conductive bumps connected to the first contact are formed, and a plurality of ground bumps connected to the plurality of ground contacts are formed on the back surface of the insulating layer. After forming a plurality of grounding bumps, And body, and the conductor film, cutting the insulating layer, a between the plurality of semiconductor chips.
　本願の発明に係る半導体装置では、半導体チップと絶縁層を導体膜で覆うことで、電磁シールドを形成する。封止体は導体膜を覆う。このため、チップ個片化後に電磁シールドを形成する必要がなく、容易に電磁シールドを形成できる。
　本願の発明に係る半導体装置の製造方法では、半導体チップと絶縁層を導体膜で覆い、電磁シールドを形成した後に、封止体で導体膜を覆う。このため、チップ個片化後に電磁シールドを形成する必要がなく、容易に電磁シールドを形成できる。 In the semiconductor device according to the present invention, an electromagnetic shield is formed by covering the semiconductor chip and the insulating layer with a conductor film. The sealing body covers the conductor film. For this reason, it is not necessary to form an electromagnetic shield after chip separation, and the electromagnetic shield can be easily formed.
In the method for manufacturing a semiconductor device according to the present invention, the semiconductor chip and the insulating layer are covered with a conductor film, and after forming an electromagnetic shield, the conductor film is covered with a sealing body. For this reason, it is not necessary to form an electromagnetic shield after chip separation, and the electromagnetic shield can be easily formed.
実施の形態１に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment. 複数の半導体チップを導体膜で覆った状態を示す図である。It is a figure which shows the state which covered the several semiconductor chip with the conductor film. 導体膜の上面を封止体で覆った状態を示す図である。It is a figure which shows the state which covered the upper surface of the conductor film with the sealing body. ベース板を除去した状態を示す図である。It is a figure which shows the state which removed the base board. 第１コンタクトと接地用コンタクトを形成した状態を示す図である。It is a figure which shows the state which formed the 1st contact and the contact for grounding. 端子配線と接地用配線を形成した状態を示す図である。It is a figure which shows the state which formed the terminal wiring and the wiring for grounding. 導電性バンプと接地用バンプを形成した状態を示す図である。It is a figure which shows the state which formed the conductive bump and the bump for grounding. 切断工程を説明する図である。It is a figure explaining a cutting process. 実施の形態１の比較例に係る半導体装置の断面図である。4 is a cross-sectional view of a semiconductor device according to a comparative example of the first embodiment. FIG. 実施の形態１の第１の変形例に係る半導体装置の下面図である。FIG. 10 is a bottom view of a semiconductor device according to a first modification example of the first embodiment. 実施の形態１の第２の変形例に係る半導体装置の下面図である。FIG. 10 is a bottom view of a semiconductor device according to a second modification example of the first embodiment. 実施の形態２に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment. 実施の形態２に係る半導体装置の下面図である。FIG. 6 is a bottom view of a semiconductor device according to a second embodiment.
　本発明の実施の形態に係る半導体装置および半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
実施の形態１．
　図１は、実施の形態１に係る半導体装置１００の断面図である。半導体装置１００は、ＦＯＷＬＰである。半導体装置１００は、絶縁層１０を備える。絶縁層１０の上面には、複数の半導体チップ１２が設けられる。半導体装置１００が備える半導体チップ１２は１つ以上であれば良い。半導体装置１００は、パッケージの面積よりも半導体チップ１２が搭載される領域の面積が小さい。半導体チップ１２の電気的接点は、半導体チップ１２からパッケージ上に拡張して配置される。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 is FOWLP. The semiconductor device 100 includes an insulating layer 10. A plurality of semiconductor chips 12 are provided on the upper surface of the insulating layer 10. The semiconductor device 100 may include one or more semiconductor chips 12. In the semiconductor device 100, the area of the region where the semiconductor chip 12 is mounted is smaller than the area of the package. The electrical contacts of the semiconductor chip 12 are extended from the semiconductor chip 12 onto the package.
　複数の半導体チップ１２の上には導体膜１４が設けられる。導体膜１４は、半導体チップ１２の上面および側面と、絶縁層１０の上面のうち半導体チップ１２から露出した部分とを覆う。導体膜１４は、絶縁層１０の上面を端部まで覆う。絶縁層１０の上面のうち半導体チップ１２から露出した部分の全域は、導体膜１４に覆われる。また、半導体チップ１２の電気的接点を有する面以外の全面が導体膜１４に覆われる。 A conductor film 14 is provided on the plurality of semiconductor chips 12. The conductor film 14 covers the upper surface and side surfaces of the semiconductor chip 12 and the portion of the upper surface of the insulating layer 10 exposed from the semiconductor chip 12. The conductor film 14 covers the upper surface of the insulating layer 10 to the end. The entire area of the upper surface of the insulating layer 10 exposed from the semiconductor chip 12 is covered with the conductor film 14. The entire surface of the semiconductor chip 12 other than the surface having electrical contacts is covered with the conductor film 14.
　導体膜１４の上面は封止体１６に覆われる。封止体１６は、モールド樹脂から形成される。封止体１６でパッケージが封止されることで、パッケージの強度を維持できる。封止体１６は、パッケージのボディを構成する。 The upper surface of the conductor film 14 is covered with the sealing body 16. The sealing body 16 is formed from mold resin. By sealing the package with the sealing body 16, the strength of the package can be maintained. The sealing body 16 constitutes the body of the package.
　絶縁層１０の裏面側は、パッケージの電気的な接点が設けられる実装面となる。半導体装置１００は、絶縁層１０を上面から裏面に貫通する第１コンタクト１８を備える。第１コンタクト１８の上端は、半導体チップ１２の裏面電極と接続される。また、半導体装置１００は、絶縁層１０を上面から裏面に貫通する接地用コンタクト２０を備える。接地用コンタクト２０の上端は、導体膜１４と接続される。第１コンタクト１８と接地用コンタクト２０は、半導体チップ１２と外部基板との電気的な接点を形成するために設けられる。 The back side of the insulating layer 10 is a mounting surface on which electrical contacts of the package are provided. The semiconductor device 100 includes a first contact 18 that penetrates the insulating layer 10 from the top surface to the back surface. The upper end of the first contact 18 is connected to the back electrode of the semiconductor chip 12. The semiconductor device 100 also includes a ground contact 20 that penetrates the insulating layer 10 from the upper surface to the back surface. The upper end of the ground contact 20 is connected to the conductor film 14. The first contact 18 and the ground contact 20 are provided to form an electrical contact between the semiconductor chip 12 and the external substrate.
　絶縁層１０の裏面には導電性バンプ２６と、接地用バンプ２８とが設けられる。導電性バンプ２６と接地用バンプ２８は、パッケージと外部基板との接続を行なうはんだバンプである。導電性バンプ２６の上には、アンダーバンプメタル２４が設けられる。アンダーバンプメタル２４の上には端子配線２２が設けられる。端子配線２２の上面は、第１コンタクト１８の下端と接続される。このように、第１コンタクト１８は、端子配線２２とアンダーバンプメタル２４を介して、半導体チップ１２と導電性バンプ２６とを接続している。 Conductive bumps 26 and grounding bumps 28 are provided on the back surface of the insulating layer 10. The conductive bumps 26 and the ground bumps 28 are solder bumps that connect the package and the external substrate. An under bump metal 24 is provided on the conductive bump 26. Terminal wiring 22 is provided on the under bump metal 24. The upper surface of the terminal wiring 22 is connected to the lower end of the first contact 18. As described above, the first contact 18 connects the semiconductor chip 12 and the conductive bump 26 via the terminal wiring 22 and the under bump metal 24.
　接地用バンプ２８の上には、アンダーバンプメタル２４が設けられる。アンダーバンプメタル２４の上には接地用配線２１が設けられる。接地用配線２１の上面は、接地用コンタクト２０の下端と接続される。このように、接地用コンタクト２０は、接地用配線２１とアンダーバンプメタル２４を介して、導体膜１４と接地用バンプ２８とを接続している。 The under bump metal 24 is provided on the ground bump 28. A ground wiring 21 is provided on the under bump metal 24. The upper surface of the ground wiring 21 is connected to the lower end of the ground contact 20. In this way, the ground contact 20 connects the conductor film 14 and the ground bump 28 via the ground wiring 21 and the under bump metal 24.
　また、半導体装置１００は、絶縁層１０を上面から裏面に貫通する接地端子用コンタクト１９を備える。接地端子用コンタクト１９の上端は、半導体チップ１２の接地用電極と接続される。接地端子用コンタクト１９の下端は、接地用配線２１とアンダーバンプメタル２４を介して、接地用バンプ２８と接続される。このように、接地用バンプ２８は、半導体チップ１２の接地用端子と電気的に接続されている。また、導体膜１４は、接地用コンタクト２０、接地用配線２１および接地端子用コンタクト１９を介して、半導体チップ１２の接地用電極と接続される。 The semiconductor device 100 also includes a ground terminal contact 19 that penetrates the insulating layer 10 from the upper surface to the back surface. The upper end of the ground terminal contact 19 is connected to the ground electrode of the semiconductor chip 12. The lower end of the ground terminal contact 19 is connected to the ground bump 28 via the ground wiring 21 and the under bump metal 24. As described above, the ground bump 28 is electrically connected to the ground terminal of the semiconductor chip 12. The conductor film 14 is connected to the grounding electrode of the semiconductor chip 12 through the grounding contact 20, the grounding wiring 21 and the grounding terminal contact 19.
　次に、半導体装置１００の製造方法を説明する。図２～８は、本実施の形態に係る半導体装置１００の製造方法を説明する図である。まず、ベース板３０の上に絶縁層１０を形成する。次に、絶縁層１０の上面に複数の半導体チップ１２を搭載する。次に、複数の半導体チップ１２の上面および側面と、絶縁層１０の上面のうち半導体チップ１２から露出した部分とを導体膜１４で覆う。図２は、複数の半導体チップ１２を導体膜１４で覆った状態を示す図である。導体膜１４は、例えば蒸着、めっきまたは貼り付けにより形成する。 Next, a method for manufacturing the semiconductor device 100 will be described. 2 to 8 are diagrams for explaining a method of manufacturing the semiconductor device 100 according to the present embodiment. First, the insulating layer 10 is formed on the base plate 30. Next, a plurality of semiconductor chips 12 are mounted on the upper surface of the insulating layer 10. Next, the conductor film 14 covers the top and side surfaces of the plurality of semiconductor chips 12 and the portion of the top surface of the insulating layer 10 exposed from the semiconductor chip 12. FIG. 2 is a view showing a state in which a plurality of semiconductor chips 12 are covered with a conductor film 14. The conductor film 14 is formed, for example, by vapor deposition, plating, or pasting.
　次に、導体膜１４の上面を封止体１６で覆う。図３は、導体膜１４の上面を封止体１６で覆った状態を示す図である。このとき、モールド樹脂はパッケージの実装面と反対側の全域を覆う。次に、ベース板３０を取り除く。図４は、ベース板３０を除去した状態を示す図である。 Next, the upper surface of the conductor film 14 is covered with a sealing body 16. FIG. 3 is a view showing a state in which the upper surface of the conductor film 14 is covered with the sealing body 16. At this time, the mold resin covers the entire region opposite to the mounting surface of the package. Next, the base plate 30 is removed. FIG. 4 is a view showing a state in which the base plate 30 is removed.
　次に、複数の第１コンタクト１８と複数の接地用コンタクト２０を形成する。図５は、第１コンタクト１８と接地用コンタクト２０を形成した状態を示す図である。複数の第１コンタクト１８は、絶縁層１０を上面から裏面まで貫通し、絶縁層１０の上面側で複数の半導体チップ１２と接続されるように形成される。また、複数の接地用コンタクト２０は、絶縁層１０を上面から裏面まで貫通し、絶縁層１０の上面側で導体膜１４と接続されるように形成される。 Next, a plurality of first contacts 18 and a plurality of ground contacts 20 are formed. FIG. 5 is a diagram showing a state in which the first contact 18 and the ground contact 20 are formed. The plurality of first contacts 18 are formed so as to penetrate the insulating layer 10 from the top surface to the back surface and be connected to the plurality of semiconductor chips 12 on the top surface side of the insulating layer 10. The plurality of grounding contacts 20 are formed so as to penetrate the insulating layer 10 from the upper surface to the rear surface and be connected to the conductor film 14 on the upper surface side of the insulating layer 10.
　次に、複数の第１コンタクト１８と複数の接地用コンタクト２０の下に複数の端子配線２２と複数の接地用配線２１を形成する。図６は端子配線２２と接地用配線２１を形成した状態を示す図である。ここでは、複数の半導体チップ１２の間を接続するチップ間配線を形成しても良い。 Next, a plurality of terminal wirings 22 and a plurality of grounding wirings 21 are formed under the plurality of first contacts 18 and the plurality of grounding contacts 20. FIG. 6 is a diagram showing a state in which the terminal wiring 22 and the grounding wiring 21 are formed. Here, an inter-chip wiring that connects the plurality of semiconductor chips 12 may be formed.
　次に、複数の端子配線２２と複数の接地用配線２１の下に、複数のアンダーバンプメタルを形成する。さらに、複数のアンダーバンプメタルの下に、複数の導電性バンプ２６と複数の接地用バンプ２８を形成する。図７は、導電性バンプ２６と接地用バンプ２８を形成した状態を示す図である。 Next, a plurality of under bump metals are formed under the plurality of terminal wires 22 and the plurality of ground wires 21. Further, a plurality of conductive bumps 26 and a plurality of ground bumps 28 are formed under the plurality of under bump metals. FIG. 7 is a diagram showing a state in which the conductive bumps 26 and the ground bumps 28 are formed.
　次に、切断工程を実施する。図８は、切断工程を説明する図である。ここでは、複数の導電性バンプ２６と複数の接地用バンプ２８を形成した後に、封止体１６と、導体膜１４と、絶縁層１０とを複数の半導体チップ１２の間で切断する。切断は、例えばダイサーにより行われる。これにより、半導体装置１００が個片化される。 Next, a cutting process is performed. FIG. 8 is a diagram illustrating the cutting process. Here, after forming the plurality of conductive bumps 26 and the plurality of ground bumps 28, the sealing body 16, the conductor film 14, and the insulating layer 10 are cut between the plurality of semiconductor chips 12. The cutting is performed by, for example, a dicer. Thereby, the semiconductor device 100 is separated into pieces.
　本実施の形態では、絶縁層１０の上面のうち半導体チップ１２から露出した部分の全域が導体膜１４で覆われる。このため、個片化された半導体装置１００では、導体膜１４が絶縁層１０の上面を端部まで覆う。また、導体膜１４は、パッケージの側面から露出する。パッケージは、側面のうち導体膜１４が露出した部分よりも上方の全域と、上面の全域とが封止体１６から形成される。 In the present embodiment, the entire region of the upper surface of the insulating layer 10 exposed from the semiconductor chip 12 is covered with the conductor film 14. For this reason, in the separated semiconductor device 100, the conductor film 14 covers the upper surface of the insulating layer 10 to the end. The conductor film 14 is exposed from the side surface of the package. In the package, the entire region above the portion of the side surface where the conductor film 14 is exposed and the entire upper surface are formed from the sealing body 16.
　なお、図２において、ベース板３０の上に絶縁層１０の代わりに固定材を設けても良い。固定材は、半導体チップ１２を固定できる材料である。この場合、ベース板３０を取り除く際に、固定材も取り除く。さらに、固定材を取り除いた後に半導体チップ１２および導体膜１４の裏面に絶縁層１０を形成する。 In FIG. 2, a fixing material may be provided on the base plate 30 instead of the insulating layer 10. The fixing material is a material that can fix the semiconductor chip 12. In this case, when removing the base plate 30, the fixing material is also removed. Further, after removing the fixing material, the insulating layer 10 is formed on the back surfaces of the semiconductor chip 12 and the conductor film 14.
　図９は、実施の形態１の比較例に係る半導体装置８００の断面図である。半導体装置８００は、導体膜１４、接地用コンタクト２０、接地用配線２１、接地端子用コンタクト１９および接地用バンプ２８が設けられていない。その他の構成は、本実施の形態の半導体装置１００と同じである。半導体装置８００に電磁シールドを設ける方法として、パッケージの外側にシールド部品を取り付けるか、切断工程の後にパッケージの外側に金属膜を形成することが考えられる。 FIG. 9 is a cross-sectional view of a semiconductor device 800 according to a comparative example of the first embodiment. The semiconductor device 800 is not provided with the conductor film 14, the ground contact 20, the ground wiring 21, the ground terminal contact 19, and the ground bump 28. Other configurations are the same as those of the semiconductor device 100 of the present embodiment. As a method of providing an electromagnetic shield in the semiconductor device 800, it is conceivable to attach a shield part outside the package or form a metal film outside the package after the cutting process.
　これに対し、本実施の形態では導体膜１４が電磁シールドとなる。本実施の形態では、接地用バンプ２８が外部基板の接地用端子と接続されることで、半導体チップ１２周辺に形成された導体膜１４が接地される。このとき、導体膜１４の電位は、半導体チップ１２または外部基板のＧＮＤ電位に接地される。このため、外部から電磁波が照射されても、半導体チップ１２の周辺の電位が変動することを抑制できる。従って、半導体チップ１２の内部の回路が、外部からの電磁波の影響を受けることを防止できる。 In contrast, in the present embodiment, the conductor film 14 serves as an electromagnetic shield. In the present embodiment, the ground bump 28 is connected to the ground terminal of the external substrate, whereby the conductor film 14 formed around the semiconductor chip 12 is grounded. At this time, the potential of the conductor film 14 is grounded to the GND potential of the semiconductor chip 12 or the external substrate. For this reason, even if electromagnetic waves are irradiated from the outside, it can suppress that the electric potential around the semiconductor chip 12 fluctuates. Therefore, it is possible to prevent the circuit inside the semiconductor chip 12 from being affected by external electromagnetic waves.
　同様に、半導体チップ１２が発生させる電磁波も、導体膜１４の電位がＧＮＤ電位に接地されていることで、外部に漏れることを防止できる。従って、半導体チップ１２が発生させる電磁波が、外部の回路に影響を及ぼすことを防止できる。 Similarly, the electromagnetic wave generated by the semiconductor chip 12 can be prevented from leaking to the outside because the potential of the conductor film 14 is grounded to the GND potential. Therefore, the electromagnetic waves generated by the semiconductor chip 12 can be prevented from affecting the external circuit.
　また、本実施の形態では、各々の半導体チップ１２の上面と側面の全域が導体膜１４に覆われる。このため、パッケージの外側にシールド部品または金属膜が設けられる構造よりも、高い電磁シールドの効果を期待できる。また、半導体装置１００内の複数の半導体チップ１２間での電磁波の影響も抑制できる。 In the present embodiment, the entire upper surface and side surfaces of each semiconductor chip 12 are covered with the conductor film 14. For this reason, a higher electromagnetic shielding effect can be expected than a structure in which a shield part or a metal film is provided outside the package. In addition, the influence of electromagnetic waves between the plurality of semiconductor chips 12 in the semiconductor device 100 can be suppressed.
　さらに、導体膜１４は、切断工程の前に絶縁層１０と半導体チップ１２の上の全域に形成されれば良い。従って、電磁シールドを容易に形成できる。このため、製造コストを抑制できる。また、切断工程の後に電磁シールドの形成のための工程を追加する必要が無い。従って、ウエハ状態でパッケージ構造を形成することで生産性を高めるというＦＯＷＬＰのメリットを維持できる。 Furthermore, the conductor film 14 may be formed over the entire area on the insulating layer 10 and the semiconductor chip 12 before the cutting step. Therefore, an electromagnetic shield can be easily formed. For this reason, manufacturing cost can be suppressed. Further, it is not necessary to add a process for forming an electromagnetic shield after the cutting process. Therefore, it is possible to maintain the merit of FOWLP that the productivity is improved by forming the package structure in the wafer state.
　また、本実施の形態の製造方法は、導体膜１４を形成することを除けば、比較例に係る半導体装置８００の製造工程と変わらない。このため、低コストでシールド構造を有するＦＯＷＬＰを実現できる。 In addition, the manufacturing method of the present embodiment is the same as the manufacturing process of the semiconductor device 800 according to the comparative example except that the conductive film 14 is formed. For this reason, FOWLP having a shield structure can be realized at low cost.
　また、本実施の形態ではパッケージ内部の導体膜１４により電磁シールドが形成されるため、パッケージの外側にシールド部品を取り付けなくても良い。従って、実装先の基板での部品配置の自由度を向上できる。また、実装先の基板を小型化できる。 In the present embodiment, since the electromagnetic shield is formed by the conductor film 14 inside the package, it is not necessary to attach a shield component to the outside of the package. Therefore, it is possible to improve the degree of freedom of component placement on the mounting board. In addition, the mounting board can be reduced in size.
　また、本実施の形態では、導体膜１４が半導体チップ１２と封止体１６の間に設けられることで、電磁シールドが形成される。導体膜１４は封止体１６で覆われているため、ハンドリング時の傷等から導体膜１４を保護できる。従って、導体膜１４の損傷によるシールド性能の低下を防止できる。 Further, in the present embodiment, the conductive film 14 is provided between the semiconductor chip 12 and the sealing body 16 so that an electromagnetic shield is formed. Since the conductor film 14 is covered with the sealing body 16, the conductor film 14 can be protected from scratches during handling. Accordingly, it is possible to prevent a decrease in shielding performance due to damage to the conductor film 14.
　本実施の形態の変形例として、半導体チップ１２の上面および側面と、絶縁層１０の上面は、一部が導体膜１４から露出していても良い。また、導電性バンプ２６と接地用バンプ２８ははんだバンプに限らず、金バンプでも良い。 As a modification of the present embodiment, the upper surface and side surfaces of the semiconductor chip 12 and the upper surface of the insulating layer 10 may be partially exposed from the conductor film 14. The conductive bumps 26 and the ground bumps 28 are not limited to solder bumps, and may be gold bumps.
　また、封止体１６は導電性であっても良い。一般に、導電性の封止体は高周波特性に影響を及ぼすことがある。このため、導電性の封止体は、高周波を扱うパッケージに適さないことが多い。これに対し、本実施の形態では、導体膜１４により封止体１６の電気特性がシールドされるため、封止体１６の高周波特性への影響を抑制できる。従って、封止体１６を導電性材料で形成できる。一般に、導電性材料は熱抵抗が低く、放熱性能が高い。従って、高い放熱性能と良好な高周波特性を両立できる。 Further, the sealing body 16 may be conductive. In general, a conductive sealing body may affect high frequency characteristics. For this reason, a conductive sealing body is often not suitable for a package that handles high frequencies. On the other hand, in this Embodiment, since the electrical property of the sealing body 16 is shielded by the conductor film 14, the influence on the high frequency characteristic of the sealing body 16 can be suppressed. Therefore, the sealing body 16 can be formed of a conductive material. In general, conductive materials have low thermal resistance and high heat dissipation performance. Therefore, both high heat dissipation performance and good high frequency characteristics can be achieved.
　また、封止体は電波を吸収しても良い。一般に、電波を吸収する素材は高周波特性に影響を及ぼすことがあるため、封止体への使用に適さないことが多い。これに対し、本実施の形態では、導体膜１４により封止体１６の電気特性がシールドされるため、封止体１６の高周波特性への影響を抑制できる。従って、封止体１６を、電波を吸収する材料で形成できる。これにより、さらに高いシールド性能のＦＯＷＬＰを得ることができる。 Also, the sealing body may absorb radio waves. In general, a material that absorbs radio waves may affect high-frequency characteristics, and thus is often not suitable for use in a sealed body. On the other hand, in this Embodiment, since the electrical property of the sealing body 16 is shielded by the conductor film 14, the influence on the high frequency characteristic of the sealing body 16 can be suppressed. Therefore, the sealing body 16 can be formed of a material that absorbs radio waves. Thereby, FOWLP with higher shield performance can be obtained.
　また、接地用バンプ２８と、半導体チップ１２の接地用端子は、電気的に接続されていなくても良い。この場合、接地用コンタクト２０と半導体チップ１２の接地用端子をパッケージ上では分離しておく。また、実装先の基板において、接地用コンタクト２０と、半導体チップ１２の接地用端子とを電気的に接続する。この構成によれば、接地用コンタクト２０の数が十分確保できずインピーダンスを十分に低く出来ない場合、または、半導体チップ１２の接地用端子の感度が非常に高い場合等にも、良好なシールド特性を得ることもできる。 Further, the ground bump 28 and the ground terminal of the semiconductor chip 12 may not be electrically connected. In this case, the ground contact 20 and the ground terminal of the semiconductor chip 12 are separated on the package. In addition, the grounding contact 20 and the grounding terminal of the semiconductor chip 12 are electrically connected to each other on the mounting board. According to this configuration, even when the number of grounding contacts 20 cannot be sufficiently secured and the impedance cannot be lowered sufficiently, or when the sensitivity of the grounding terminal of the semiconductor chip 12 is very high, etc., good shielding characteristics. You can also get
　図１０は、実施の形態１の第１の変形例に係る半導体装置２００の下面図である。図１０は、半導体装置２００を実装面側から見た図である。半導体装置２００は、複数の導電性バンプ２６と複数の接地用バンプ２８の配置が半導体装置１００と異なる。複数の接地用バンプ２８はパッケージの外周部に設けられる。複数の導電性バンプ２６はパッケージの中央部に設けられる。複数の接地用バンプ２８は、複数の導電性バンプ２６を囲む。 FIG. 10 is a bottom view of the semiconductor device 200 according to the first modification of the first embodiment. FIG. 10 is a view of the semiconductor device 200 as viewed from the mounting surface side. The semiconductor device 200 is different from the semiconductor device 100 in the arrangement of the plurality of conductive bumps 26 and the plurality of ground bumps 28. The plurality of ground bumps 28 are provided on the outer periphery of the package. The plurality of conductive bumps 26 are provided at the center of the package. The plurality of ground bumps 28 surround the plurality of conductive bumps 26.
　また、複数の接地用コンタクト２０はパッケージの外周部に設けられる。複数の接地用コンタクト２０と複数の接地用バンプ２８は、パッケージの外周部において交互に並んでいる。なお、半導体装置２００を実装面側において、複数の接地用コンタクト２０は接地用配線２２１に覆われている。図１０では便宜上、接地用コンタクト２０の位置が示されている。また、接地用配線２２１は、パッケージの外周部において複数の導電性バンプ２６を囲む。 Also, a plurality of grounding contacts 20 are provided on the outer periphery of the package. The plurality of grounding contacts 20 and the plurality of grounding bumps 28 are alternately arranged on the outer periphery of the package. Note that, on the mounting surface side of the semiconductor device 200, the plurality of ground contacts 20 are covered with the ground wiring 221. In FIG. 10, the position of the ground contact 20 is shown for convenience. The ground wiring 221 surrounds the plurality of conductive bumps 26 at the outer peripheral portion of the package.
　複数の導電性バンプ２６は、高周波信号が入力または出力される信号バンプ２６ａを含む。信号バンプ２６ａは接地用コンタクト２０と整合回路で接続されている。また、パッケージの中央部には、複数の半導体チップ１２が設けられる。接地用配線２２１、接地用バンプ２８および接地用コンタクト２０は、半導体チップ１２が設けられる領域を囲む。 The plurality of conductive bumps 26 include signal bumps 26a to which high-frequency signals are input or output. The signal bump 26a is connected to the ground contact 20 by a matching circuit. A plurality of semiconductor chips 12 are provided at the center of the package. The ground wiring 221, the ground bump 28, and the ground contact 20 surround a region where the semiconductor chip 12 is provided.
　このように、半導体装置２００では、半導体チップ１２および信号バンプ２６ａを囲うように、複数の接地用コンタクト２０、複数の接地用バンプ２８および接地用配線２２１をレイアウトする。平面視において、半導体チップ１２および信号バンプ２６ａは、接地用配線２２１によって外部と隔てられている。これにより、シールド効果をさらに向上できる。 As described above, in the semiconductor device 200, the plurality of grounding contacts 20, the plurality of grounding bumps 28, and the grounding wiring 221 are laid out so as to surround the semiconductor chip 12 and the signal bumps 26a. In plan view, the semiconductor chip 12 and the signal bump 26 a are separated from the outside by a ground wiring 221. Thereby, the shielding effect can be further improved.
　図１１は、実施の形態１の第２の変形例に係る半導体装置３００の下面図である。図１１に示されるように、必要とする電磁シールドの性能に応じて、パッケージの外周部において接地用配線３２１が途切れていても良い。接地用配線３２１が途切れた部分には、信号バンプ２６ａが配置される。パッケージの外周部に信号バンプ２６ａが配置されることで、外部との信号の入出力をし易くできる。 FIG. 11 is a bottom view of the semiconductor device 300 according to the second modification of the first embodiment. As shown in FIG. 11, the ground wiring 321 may be interrupted at the outer periphery of the package according to the required performance of the electromagnetic shield. A signal bump 26a is disposed in a portion where the ground wiring 321 is interrupted. By arranging the signal bumps 26a on the outer periphery of the package, it is possible to easily input / output signals from / to the outside.
　これらの変形は以下の実施の形態に係る半導体装置および半導体装置の製造方法について適宜応用することができる。なお、以下の実施の形態に係る半導体装置および半導体装置の製造方法については実施の形態１との共通点が多いので、実施の形態１との相違点を中心に説明する。 These modifications can be applied as appropriate to the semiconductor device and the method for manufacturing the semiconductor device according to the following embodiments. Note that the semiconductor device and the method for manufacturing the semiconductor device according to the following embodiment have much in common with the first embodiment, and therefore, differences from the first embodiment will be mainly described.
実施の形態２．
　図１２は、実施の形態２に係る半導体装置４００の断面図である。導体膜１４は、複数の半導体チップ１２の間で絶縁層１０の上面を覆う絶縁層被覆部１４ａを有する。絶縁層被覆部１４ａは、絶縁層１０の上面と接している。絶縁層１０の裏面のうち絶縁層被覆部１４ａの直下には、チップ間配線４２３ａが設けられる。また、半導体装置４００は、絶縁層１０を上面から裏面に貫通する複数の第２コンタクト４２５を備える。複数の第２コンタクト４２５は、チップ間配線４２３ａと複数の半導体チップ１２とをそれぞれ接続する。 Embodiment 2. FIG.
FIG. 12 is a cross-sectional view of the semiconductor device 400 according to the second embodiment. The conductor film 14 has an insulating layer covering portion 14 a that covers the upper surface of the insulating layer 10 between the plurality of semiconductor chips 12. The insulating layer covering portion 14 a is in contact with the upper surface of the insulating layer 10. Of the back surface of the insulating layer 10, an inter-chip wiring 423 a is provided directly below the insulating layer covering portion 14 a. In addition, the semiconductor device 400 includes a plurality of second contacts 425 that penetrate the insulating layer 10 from the top surface to the back surface. The plurality of second contacts 425 connect the inter-chip wiring 423a and the plurality of semiconductor chips 12, respectively.
　複数の半導体チップ１２は、複数の第２コンタクト４２５とチップ間配線４２３ａによって接続されている。複数の第２コンタクト４２５とチップ間配線４２３ａは、一方の半導体チップ１２の信号の出力端子と、他方の半導体チップ１２の信号の入力端子とを繋ぐ。チップ間配線４２３ａは、高周波信号の線路となる。チップ間配線４２３ａと絶縁層１０と導体膜１４とは、マイクロストリップ線路を形成する。 The plurality of semiconductor chips 12 are connected to the plurality of second contacts 425 by inter-chip wiring 423a. The plurality of second contacts 425 and the inter-chip wiring 423 a connect the signal output terminal of one semiconductor chip 12 and the signal input terminal of the other semiconductor chip 12. The inter-chip wiring 423a serves as a high-frequency signal line. The interchip wiring 423a, the insulating layer 10, and the conductor film 14 form a microstrip line.
　図１３は、実施の形態２に係る半導体装置４００の下面図である。半導体装置４００では、半導体装置２００と同様に、複数の半導体チップ１２を囲んで、接地用配線２２１、接地用バンプ２８および接地用コンタクト２０が設けられる。チップ間配線４２３ａの両側において、複数の半導体チップ１２は配線４２３ｂで互いに接続される。配線４２３ｂは、接地用コンタクト２０に接続されている。なお、半導体装置４００を実装面側において、複数の半導体チップ１２は絶縁層１０に覆われている。図１３では半導体チップ１２の位置が便宜上示されている。また、図１３では導電性バンプ２６が省略されている。 FIG. 13 is a bottom view of the semiconductor device 400 according to the second embodiment. In the semiconductor device 400, similarly to the semiconductor device 200, the ground wiring 221, the ground bump 28, and the ground contact 20 are provided so as to surround the plurality of semiconductor chips 12. On both sides of the interchip wiring 423a, the plurality of semiconductor chips 12 are connected to each other by the wiring 423b. The wiring 423 b is connected to the ground contact 20. Note that, on the mounting surface side of the semiconductor device 400, the plurality of semiconductor chips 12 are covered with the insulating layer 10. In FIG. 13, the position of the semiconductor chip 12 is shown for convenience. In FIG. 13, the conductive bumps 26 are omitted.
　チップ間配線４２３ａの幅は、チップ間配線４２３ａと絶縁層１０と導体膜１４とがマイクロストリップ線路を形成するように設定される。チップ間配線４２３ａの信号線幅は、絶縁層１０の厚さと誘電率に応じて最適な値に設定される。 The width of the interchip wiring 423a is set so that the interchip wiring 423a, the insulating layer 10, and the conductor film 14 form a microstrip line. The signal line width of the inter-chip wiring 423a is set to an optimum value according to the thickness of the insulating layer 10 and the dielectric constant.
　一般に、直流または低周波の信号配線については、パッケージ配線の設計ルールに従い、電流容量等を考慮して配線太さを決める。これに対し、高周波の信号配線に関しては、特性インピーダンスを考慮する必要がある。本実施の形態では、電磁シールドである導体膜１４を利用してマイクロストリップ線路を形成する。これにより、適した特性インピーダンスの伝送線路を構成できる。従って、チップ間の配線損失を抑制し、半導体装置４００の性能を向上できる。 Generally, for DC or low-frequency signal wiring, the wiring thickness is determined in consideration of the current capacity and the like according to the package wiring design rules. On the other hand, for high-frequency signal wiring, it is necessary to consider characteristic impedance. In the present embodiment, the microstrip line is formed using the conductor film 14 which is an electromagnetic shield. Thereby, it is possible to configure a transmission line having a suitable characteristic impedance. Therefore, wiring loss between chips can be suppressed and the performance of the semiconductor device 400 can be improved.
　なお、各実施の形態で説明した技術的特徴は適宜に組み合わせて用いてもよい。 It should be noted that the technical features described in each embodiment may be used in appropriate combination.
　１００、２００、３００、４００　半導体装置、１０　絶縁層、１２　半導体チップ、１４　導体膜、１４ａ　絶縁層被覆部、１６　封止体、１８　第１コンタクト、２０　接地用コンタクト、４２３ａ　チップ間配線、４２５　第２コンタクト、２６　導電性バンプ、２６ａ　信号バンプ、２８　接地用バンプ 100, 200, 300, 400 Semiconductor device, 10 Insulating layer, 12 Semiconductor chip, 14 Conductor film, 14a Insulating layer covering, 16 Sealing body, 18 First contact, 20 Ground contact, 423a Interchip wiring, 425th 2 contacts, 26 conductive bumps, 26a signal bumps, 28 ground bumps

Claims (11)

  1. 　絶縁層と、
    　前記絶縁層の上面に設けられた半導体チップと、
    　前記半導体チップの上面および側面と、前記絶縁層の上面のうち前記半導体チップから露出した部分と、を覆う導体膜と、
    　前記導体膜の上面を覆う封止体と、
    　前記絶縁層の裏面に設けられた導電性バンプと、
    　前記絶縁層の裏面に設けられた接地用バンプと、
    　前記絶縁層を上面から裏面に貫通し、前記半導体チップと前記導電性バンプとを接続する第１コンタクトと、
    　前記絶縁層を上面から裏面に貫通し、前記導体膜と前記接地用バンプとを接続する接地用コンタクトと、
    　を備え、
    　前記導体膜は、前記絶縁層の上面を端部まで覆うことを特徴とする半導体装置。     An insulating layer;
    A semiconductor chip provided on the upper surface of the insulating layer;
    A conductor film covering the upper surface and side surfaces of the semiconductor chip and a portion of the upper surface of the insulating layer exposed from the semiconductor chip;
    A sealing body covering the upper surface of the conductor film;
    Conductive bumps provided on the back surface of the insulating layer;
    A grounding bump provided on the back surface of the insulating layer;
    A first contact that penetrates the insulating layer from the top surface to the back surface, and connects the semiconductor chip and the conductive bump;
    A ground contact that penetrates the insulating layer from the top surface to the back surface, and connects the conductor film and the ground bump;
    With
    The semiconductor device, wherein the conductor film covers an upper surface of the insulating layer up to an end.
  2. 　前記接地用バンプと前記接地用コンタクトは、前記半導体チップが設けられる領域を囲むことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the ground bump and the ground contact surround a region where the semiconductor chip is provided.
  3. 　前記接地用バンプは、前記導電性バンプを囲むことを特徴とする請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the grounding bump surrounds the conductive bump.
  4. 　前記導電性バンプは、高周波信号が入力または出力される信号バンプを含むことを特徴とする請求項１から３の何れか１項に記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the conductive bump includes a signal bump to which a high frequency signal is input or output.
  5. 　前記接地用バンプは、前記半導体チップの接地用端子と電気的に接続されることを特徴とする請求項１から４の何れか１項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the ground bump is electrically connected to a ground terminal of the semiconductor chip.
  6. 　前記半導体チップを複数備え、
    　前記導体膜は、前記複数の半導体チップの間で前記絶縁層の上面を覆う絶縁層被覆部を有することを特徴とする請求項１から５の何れか１項に記載の半導体装置。     A plurality of the semiconductor chips,
    6. The semiconductor device according to claim 1, wherein the conductor film has an insulating layer covering portion that covers an upper surface of the insulating layer between the plurality of semiconductor chips.
  7. 　前記絶縁層の裏面のうち前記絶縁層被覆部の直下に設けられたチップ間配線と、
    　前記絶縁層を上面から裏面に貫通し、前記チップ間配線と前記複数の半導体チップとをそれぞれ接続する第２コンタクトと、
    　を備えることを特徴とする請求項６に記載の半導体装置。     Of the back surface of the insulating layer, the inter-chip wiring provided immediately below the insulating layer covering portion,
    A second contact penetrating the insulating layer from the upper surface to the rear surface, and connecting the inter-chip wiring and the plurality of semiconductor chips respectively;
    The semiconductor device according to claim 6, comprising:
  8. 　前記チップ間配線の幅は、前記チップ間配線と前記絶縁層と前記導体膜とがマイクロストリップ線路を形成するように設定されることを特徴とする請求項７に記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the width of the inter-chip wiring is set so that the inter-chip wiring, the insulating layer, and the conductor film form a microstrip line.
  9. 　前記封止体は導電性であることを特徴とする請求項１から８の何れか１項に記載の半導体装置。 9. The semiconductor device according to claim 1, wherein the sealing body is conductive.
  10. 　前記封止体は電波を吸収することを特徴とする請求項１から９の何れか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the sealing body absorbs radio waves.
  11. 　絶縁層の上面に複数の半導体チップを搭載し、
    　前記複数の半導体チップの上面および側面と、前記絶縁層の上面のうち前記半導体チップから露出した部分と、を導体膜で覆い、
    　前記導体膜の上面を封止体で覆い、
    　前記絶縁層を上面から裏面まで貫通し、前記絶縁層の上面側で前記複数の半導体チップと接続される複数の第１コンタクトを形成し、
    　前記絶縁層を上面から裏面まで貫通し、前記絶縁層の上面側で前記導体膜と接続される複数の接地用コンタクトを形成し、
    　前記絶縁層の裏面に、前記複数の第１コンタクトと接続される複数の導電性バンプを形成し、
    　前記絶縁層の裏面に、前記複数の接地用コンタクトと接続される複数の接地用バンプを形成し、
    　前記複数の導電性バンプと前記複数の接地用バンプを形成した後に、前記封止体と、前記導体膜と、前記絶縁層と、を前記複数の半導体チップの間で切断することを特徴とする半導体装置の製造方法。     A plurality of semiconductor chips are mounted on the upper surface of the insulating layer,
    Covering the upper surface and side surfaces of the plurality of semiconductor chips and the portion of the upper surface of the insulating layer exposed from the semiconductor chip with a conductor film,
    Cover the upper surface of the conductor film with a sealing body,
    Penetrating the insulating layer from the top surface to the back surface, forming a plurality of first contacts connected to the plurality of semiconductor chips on the top surface side of the insulating layer;
    Penetrating the insulating layer from the upper surface to the back surface, and forming a plurality of grounding contacts connected to the conductor film on the upper surface side of the insulating layer;
    Forming a plurality of conductive bumps connected to the plurality of first contacts on the back surface of the insulating layer;
    Forming a plurality of ground bumps connected to the plurality of ground contacts on the back surface of the insulating layer;
    After forming the plurality of conductive bumps and the plurality of grounding bumps, the sealing body, the conductor film, and the insulating layer are cut between the plurality of semiconductor chips. A method for manufacturing a semiconductor device.
PCT/JP2018/016665 2018-04-24 2018-04-24 Semiconductor device and method of manufacturing semiconductor device WO2019207657A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04180659A (en) * 1990-11-15 1992-06-26 Nec Yamagata Ltd Semiconductor device
JP2007059533A (en) * 2005-08-23 2007-03-08 Murata Mfg Co Ltd Circuit module
JP2016092106A (en) * 2014-10-31 2016-05-23 日立化成株式会社 Semiconductor device manufacturing member and manufacturing method of semiconductor device using the same
US20160254237A1 (en) * 2015-02-27 2016-09-01 Qualcomm Incorporated Radio-frequency (rf) shielding in fan-out wafer level package (fowlp)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04180659A (en) * 1990-11-15 1992-06-26 Nec Yamagata Ltd Semiconductor device
JP2007059533A (en) * 2005-08-23 2007-03-08 Murata Mfg Co Ltd Circuit module
JP2016092106A (en) * 2014-10-31 2016-05-23 日立化成株式会社 Semiconductor device manufacturing member and manufacturing method of semiconductor device using the same
US20160254237A1 (en) * 2015-02-27 2016-09-01 Qualcomm Incorporated Radio-frequency (rf) shielding in fan-out wafer level package (fowlp)

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