JPS61208830A - Charged beam exposure method - Google Patents

Abstract

PURPOSE:To perform readily and accurately drawing in case of EB direct drawing that a primary material is formed of various types of materials by accurately forming the size of a pattern on an irregular surface even if a material having a large reflecting electron coefficient is presented on the raised portion of a silicon substrate. CONSTITUTION:A tantalum layer (Ta) 102 is formed on a silicon substrate 101, and an irregular surface is formed on the substrate. A positive type resist layer 103 made of PMMA (polymethylmethacrylate) is coated to bury a recess, baked, and an electron beam is emitted. Then, the entire PMMA layer 203 is coated, baked, and an electron beam is emitted. Further, a resist is selectively exposed with a beam 204, an image is drawn, and a resist pattern 303 is formed by developing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of exposing a resist with a charged beam to a resist coated on a substrate having uneven parts having different reflected electron coefficients.

[Technical background of the invention and its problems]

In recent years, the trend of miniaturization of LSI devices has progressed, and in the near future it will be 0.5 (teacher) and even 0.25. Devices with ccm (μm:) dimensions are about to appear. It is difficult to fabricate such fine devices using conventional methods using optical steppers, and therefore new phosphorography is desperately needed. Among these, electron beam and Lithography is widely recognized as the most powerful technology.

However, as shown in Figure 6, the conventional electron beam
In phosphorography technology, on the silicon substrate 601,
If there is a convex portion 602 made of wiring made of a material with a large reflected electron coefficient, for example tungsten, the resist 603 on the convex portion will be exposed excessively, and the pattern resolution will differ in the resist on the concave and convex portion, making it impossible to form a pattern accurately. There is a problem.

[Purpose of the invention]

An object of the present invention is to provide a multi-beam exposure method that can reduce pattern dimensional errors when the substrate surface has uneven parts with different reflected electron coefficients in a simple manner, and that can cope with ultra-fine miniaturization of LSI devices. Our goal is to provide the following.

[Summary of the invention]

In the present invention, after a resist film is formed on a substrate having an uneven surface and convex portions formed of a material having a larger reflected electron coefficient than the concave portions, a first resist layer is buried in the concave portions of the substrate and exposed to light. Irradiating at least the first resist layer with an energy beam at a dose lower than the necessary dose, and applying a second resist layer over the entire surface extending from above the first resist layer to above the convex portions. In this method, the energy beam is selectively irradiated with the required irradiation amount for exposure.

In order to prevent the proximity effect during exposure, the charged beam exposure method preferably includes a step of irradiating the entire surface of the second resist layer with an energy beam at a dose lower than the dose required for exposure. This can be done by a desired drawing or the like. In this case, in order to effectively suppress the proximity effect, it is desirable that the acceleration voltage of the electron beam be 40 KV or higher.

〔Effect of the invention〕

According to the present invention, even if a material with a large reflected electron coefficient is present in the convex portions of the silicon substrate, the dimensions of the pattern in the concave and convex portions can be formed with high precision. As a result, in the case of EB direct drawing where the underlying material is made of various different materials, accurate drawing can be easily performed, which is a great practical advantage.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

First, as shown in Figure 1, a silicon substrate (wafer/'
) Tantalum layer (Ta) 102 on 101 with a thickness of 30 mm
00A is formed to form irregularities on the substrate. Although not shown in the figure, an oxide film or the like is usually coated on this in integrated circuits. Then PMMA (polymethyl methacrylate)
A positive resist layer 103 is applied to a total thickness of 2,800 μC so as to fill the recesses and baked to prepare a sample.
The entire surface of the sample is irradiated with an electron beam using a beam 104 with a correction amount of 5% of /ml. After that, as shown in Figure 2, PMM
A layer 203 is applied to the entire surface with a thickness of 1/jm and baked, and the irradiation amount required for electron beam exposure is 60 μC/d.
The entire surface of the sample is irradiated with a VC electron beam using a beam 205 with a correction amount of 15%. Further, the resist is selectively exposed to a beam 204 with an irradiation dose of 60 μC/d at an acceleration voltage of 50 KV to perform drawing, and a resist pattern is formed by development processing. Figure K3 is a plan view showing a resist pattern 303 formed on a substrate having unevenness by the above method.

As a drawing pattern, for example, as shown in FIG. 4, two large-area patterns 400 and two
A 0.5 μm line pattern 401 was formed. The length of the large area pattern 400 was set to be 4oottm@w. However, FIG. 4(a) is a sectional view and FIG. 4(b) is a plan view.

As shown in FIG. 5, the amount of dimensional variation of the pattern drawn and formed in this way, especially the dimensional variation of the 0.5 μm line, is on St (curve 1) and on Ta (curve 2) under the same development conditions.
) are formed with almost the same dimensions, P-P
(lio, within 0.6 μm.

In other words, the amount of variation in pattern dimensions due to the proximity effect is reduced to 0.5μ.
It was possible to make the pattern within ±10° (±0.03 μm) of the m pattern.

In addition, in FIG. 5, the horizontal axis represents the width W of the large area pattern.
, the vertical axis indicates the dimensional difference ΔS from the design pattern of the 0.5 μm line.

In contrast, in the conventional method, Fig. 6(a) and (b)
K As shown in the cross-sectional and plan views, if a pattern is selectively drawn and exposed at 604 on the beam with the dose necessary for exposure, and irradiation for correction is not performed, the pattern will be formed due to the proximity effect as shown in Figure 7. The amount of dimensional variation is as much as 0.25 #m, and under the same development, the pattern size on the Si substrate (curve 1) and the pattern size on the Ta substrate (curve 2) are 0. It was not possible to satisfy the permissible value of dimensional variation within ±0.05 μm: 0.1 μm, 0.5 μm, <±10 inches of turn.

As described above, according to the method used in this disaster, the amount of pattern size variation due to the dimensional variation on the uneven substrate with different reflected electron coefficients and the proximity effect was reduced from the conventional 0.35 μm to 3.0 μm.
It can be significantly reduced to within 5 μm (±0.03 pm). Therefore, it can sufficiently handle the formation of devices with submicron patterns, and its usefulness is tremendous. In addition, since the concave portion is filled with the first resist layer 103 and baked, and then the second resist layer 203 is applied, the surface of the second resist layer 203 has good flatness and less blur in the image formation. stomach. Note that in the above-mentioned embodiment, full-surface correction is used in order to suppress the proximity effect when exposing the upper PMMA resist layer 203 with a thickness of 11 trn, but the effect of the present invention is due to the full-surface correction. However, similar results have been obtained by correction of non-pattern portions or by a combination of full-scale correction and non-pattern correction. However, from the viewpoint of throughput, full-temperature correction is more suitable. In addition to electron beams, ion beams can be used as charged beams for exposure, and as energy beams for corrective irradiation, light, X-rays, etc. may be used in addition to electron beams. Irradiation with a charged beam or an energy beam may be performed by pattern projection (transfer) in addition to the drawing method.

Charged beam exposure at 40 KV to reduce the proximity effect
It is desirable to perform this at a higher acceleration voltage.

[Brief explanation of drawings]

1 and 2 are process sectional views for explaining the present invention in detail, FIG. 3 is a plan view showing the state of pattern formation of a sample obtained in an example of the present invention, and FIG. 4 is a process sectional view for explaining the present invention in detail. Fig. 5 is a characteristic diagram showing the dimensional difference △So between the exposed pattern and the designed pattern with respect to the width W of the large-area turn. , Explanatory diagram showing the pattern forming process by the conventional method, No. 7
The figure is a characteristic diagram showing the change in the dimensional difference ΔS with respect to the pattern width W in the conventional method. 101.601- St wafer, 102,602-
Ta. 103.203,303,603...Resist (PM
MA ), 104 , 205 . . . electron beam for full-surface exposure, 204 , 604 . . . electron beam for EB drawing. (7317) Patent attorney Kensuke Norichika (and 1 other person) Figure 1 Figure 2 Figure 1O Figure 3 Figure 4 -;4 ・05J”9 Figure 5 Figure 6

Claims (4)

[Claims] (1) A resist film is formed on a substrate with an uneven surface and a convex part made of a material with a larger reflected electron coefficient than the concave parts, and selective exposure is performed by irradiating the resist film with a charged beam. A charged beam exposure method, comprising the step of embedding a first resist layer in a recessed portion of the substrate and irradiating at least the first resist layer with an energy beam at a dose lower than the dose required for exposure. , comprising the step of applying a second resist layer to the entire surface extending from above the first resist layer to above the convex portion, and selectively irradiating and exposing it with a charged beam at a dose necessary for exposure. A charged beam exposure method that uses (2) The charged beam exposure method includes a step of irradiating the entire surface of the second resist layer with an energy beam at a dose smaller than the dose required for exposure. Charged beam exposure method described. (3) The charged beam exposure method according to claim 1, wherein the selective exposure with the charged beam is performed by electron beam lithography. (4) The charged beam exposure method according to claim 3, wherein the acceleration voltage of the electron beam is 40 KV or more.