JPS61208345A - Synchronous supervisory device - Google Patents

Synchronous supervisory device

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Publication number
JPS61208345A
JPS61208345A JP4883285A JP4883285A JPS61208345A JP S61208345 A JPS61208345 A JP S61208345A JP 4883285 A JP4883285 A JP 4883285A JP 4883285 A JP4883285 A JP 4883285A JP S61208345 A JPS61208345 A JP S61208345A
Authority
JP
Japan
Prior art keywords
output
detection
signal
supervisory
monitoring device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4883285A
Other languages
Japanese (ja)
Inventor
Junji Namiki
並木 淳治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4883285A priority Critical patent/JPS61208345A/en
Publication of JPS61208345A publication Critical patent/JPS61208345A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To transmit the synchronizing state of a reference carrier surely even under high noise level by constituting the titled device with the 1st detecting means outputting a detection signal when a detection output is received near a normal signal position, the 2nd detection means at a position other than the vicinity of signal position and a comparision means comparing a means value of output of each means. CONSTITUTION:When a 4-phase PSK signal enters two supervisory devices and a reference carrier is synchronized, the relation of means output values is the 1st supervisory device 3 > 2nd supervisory device 3' regardless of the quantity of input noise. On the other hand, since four signal points are turned around the origin at the asynchronizing state of the reference carrier, the mean output value is expressed as 1st supervisory device = 2nd supervisory device independingly of the quantity of input noise similarly. Each means output is obtained from lowpass filters 4, 4'. The synchronization of the carrier is identi fied by the quantity of means output of the two supervisory devices.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は位相変調波、振幅位相、変調波を同期検波復
調するために必要な参照搬送波の同期を監視する技術に
関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a technique for monitoring the synchronization of a phase modulated wave, an amplitude phase, and a reference carrier wave necessary for coherent detection demodulation of a modulated wave.

(従来技術とその間開点) 搬送波帯のディジタル伝送には古くから利用されている
2相及び4相位相変調方式(PSK)や近年の、地上マ
イクロ波帯を中心に広く利用される様になった振幅位相
変調方式(Quadrature Amplitude
Modulation;QAM)がある。これらの復調
には雑音特性に優れて同期検波方式が利用されている。
(Conventional technology and gap between them) Two-phase and four-phase phase keying (PSK) have been used for a long time for carrier band digital transmission, and in recent years, they have become widely used mainly in terrestrial microwave bands. Quadrature Amplitude Modulation
Modulation (QAM). For these demodulations, a synchronous detection method is used because it has excellent noise characteristics.

同期検波方式には送信側搬送波に同期を参照搬送波が必
要である。同搬送波の同期が確立されている場合に限り
受信側で送信側で送った送信符号と同じものが観測でき
、・送受搬送波間にΔf(Hz)だけの同波数差が存在
していると受信側では1秒間にΔfの早さで回転する送
信符号空間を観測することになる。したがって雑音があ
まり顕著でない場合には同期検波後の復調信号点が正規
の位置で観測されているかどうかで比較的簡単に同期状
態を検出できる。これらの公知例としては1975年1
0月290発行の電子通信学長・通信方式研究会資料(
C875−12)[衛星通信用ハイブリット変復調装置
1に見られる。
The synchronous detection method requires a reference carrier to be synchronized with the transmitting carrier. Only when the synchronization of the same carrier waves is established, the receiving side can observe the same transmitted code as the transmitting side, and if there is a difference in the same wave number of Δf (Hz) between the transmitting and receiving carrier waves, the reception On the other hand, a transmitted code space that rotates at a speed of Δf per second is observed. Therefore, if the noise is not very noticeable, the synchronization state can be detected relatively easily by checking whether the demodulated signal point after coherent detection is observed at the correct position. Publicly known examples of these are 1975 1
Materials published by the President of Electronic Communications and Communication Methods Study Group (October 290) (
C875-12) [Seen in hybrid modulation/demodulation device 1 for satellite communication.

従来の同期監視装置の一実施例のブロック図を第2図に
示す。搬送波帯の入力信号は端子90から同期検波器1
へ入り、同相、直交両成分はアナログディジタル変換器
20.21で各々ディジタル化され端子100.101
へ出される。ここで同期検波器1は乗算器12.13低
域濾波器14.15、瓦/2移相器11、参照搬送波を
発生する発振器10から成る。3は読出し専用メモリー
(Read 0nly Memory :ROM)で、
2次元の符号空間を端子100.101からのディジタ
ル化された同相、直交座標で認識し、正規の信号点近傍
に対応するアドレスが印加されたときに[1]を出力し
、その他の時は零を出力するものである。4相位相変調
波に対する読出し専用メモリーの内容の例第3図(a)
A block diagram of an embodiment of a conventional synchronization monitoring device is shown in FIG. The carrier band input signal is sent from the terminal 90 to the synchronous detector 1.
The in-phase and quadrature components are respectively digitized by analog-to-digital converters 20.21 and sent to terminals 100.101.
be sent to Here, the synchronous detector 1 includes a multiplier 12, 13, a low-pass filter 14, 15, a half-tilt phase shifter 11, and an oscillator 10 that generates a reference carrier wave. 3 is a read-only memory (ROM),
Recognizes the two-dimensional code space using the digitized in-phase and rectangular coordinates from terminals 100 and 101, and outputs [1] when an address corresponding to the vicinity of a regular signal point is applied, and at other times. It outputs zero. Example of contents of read-only memory for 4-phase phase modulated wave Figure 3 (a)
.

(b)に示す。Shown in (b).

第3図(a)、 (b)の4つの斜線部は4相PSKの
4つの信号点exp(i 7L/4)、 exp(j3
x/4)、 exp(j5x/4)、 expθ7に/
 4 )を覆っている。このメモリーは同期検波器の同
期状態を監視する監視装置として働いている。メモリー
3の出力は低域濾波器4により平滑化され、比較器5に
加えられある値以上の出力が低域濾波器4がら得られた
ときを同期状態と認識し出力端子91〜判定値を出力す
る。
The four shaded areas in FIGS. 3(a) and (b) are the four signal points exp(i7L/4) and exp(j3) of the 4-phase PSK.
x/4), exp(j5x/4), expθ7/
4) Covers. This memory works as a monitoring device to monitor the synchronization status of the synchronous detector. The output of the memory 3 is smoothed by a low-pass filter 4, and applied to a comparator 5. When an output of a certain value or more is obtained from the low-pass filter 4, it is recognized as a synchronized state, and the output terminal 91 outputs a judgment value. Output.

この場合、雑音が大きくなるために従って受信信号点の
分布が大きくなり、同期状態であっても第3図(a)、
 (b)の傾線部分〜受信信号が入らなくなり、非同期
状態との識別が非常に困難になる。
In this case, as the noise increases, the distribution of received signal points increases, and even in the synchronized state, as shown in Fig. 3(a),
From the sloped line part in (b), no reception signal is received, making it very difficult to distinguish it from an asynchronous state.

(発明の目的) この発明は、高雑音レベル下においても、確実に参照搬
送波の同期状態を送出する同期監視装置を提供すること
にある。
(Object of the Invention) An object of the present invention is to provide a synchronization monitoring device that reliably transmits the synchronization state of a reference carrier wave even under a high noise level.

(発明の構成) 本発明によれば、振幅位相変調波の同期検波出力が供給
される同期監視装置であって、(a)前記検波出力が正
規の信号点位置近傍に受信されたときに検出信号を出力
する第1の検出手段、(b)前記検波出力が前記正規の
信号点位置近傍以外の位置に受信されたときに検出信号
を出力する第2の検出手段、 (c)前記第1の検出手段出力の平均値と前記第2の検
出手段出力の平均値とを比較する比較手段、とから構成
されることを特徴とする同期監視装置が得られる。
(Structure of the Invention) According to the present invention, there is provided a synchronous monitoring device to which a synchronous detection output of an amplitude phase modulated wave is supplied, wherein (a) detection is performed when the detection output is received near a regular signal point position; a first detection means for outputting a signal; (b) a second detection means for outputting a detection signal when the detection output is received at a position other than the vicinity of the regular signal point position; (c) the first detection means; and comparing means for comparing the average value of the output of the second detection means with the average value of the output of the second detection means.

(構成の詳細な説明) 次に本発明に付いて図面を参照して詳細に説明する。従
来の実施例が入力雑音レベルの増大に従って的確な識別
能力を失う最大の理由は第2図で言うと5の比較器の閾
値が固定されていると言う点である。すなわち受信信号
点分布は入力雑音の増大に従って大きくなり、その為メ
モリー3が1を出力する確率が下がってしまうのに対し
、これに的確に対応して比較器の閾値を下げる構造が無
い点である。ただし、この比較器の閾値をあまり下げす
ぎると、非同期状態でもこの閾値を上回る状態が発生し
てしまい結局は有効な同期監視ができないと言ってよい
。本発明はこの欠点を克服するために2種類の監視装置
を設けて、その装置の2出力の相対レベルによって同期
監視を行うものである。
(Detailed Description of Configuration) Next, the present invention will be described in detail with reference to the drawings. The main reason why the conventional embodiment loses accurate discrimination ability as the input noise level increases is that the threshold of comparator 5 in FIG. 2 is fixed. In other words, the received signal point distribution increases as the input noise increases, and as a result, the probability that memory 3 outputs 1 decreases, but there is no structure to lower the comparator threshold in response to this. be. However, if the threshold value of this comparator is lowered too much, a state in which this threshold value is exceeded will occur even in an asynchronous state, and it can be said that effective synchronous monitoring cannot be performed after all. In order to overcome this drawback, the present invention provides two types of monitoring devices and performs synchronous monitoring based on the relative levels of the two outputs of the devices.

(実施例) 第1図(a)、 (b)、 (c)は本発明の一実施例
のブロック図である。図中1の同期検波器、3の監視装
置、4゜4′の低域濾波器は第2図のものと同一である
。さらに5の比較器はその閾値の設定は異なるものの、
第2図のものと同一である。3′の監視装置第1図(c
)は3の監視装置同図(b)の内容を90°回転させた
ものである。今4相PSKの信号が2つの監視装置に入
った時、参照搬送波が同期している場合には、入力雑音
の大小に関わらず、その平均出力値は第1の監視装置3
〉第2の監視装置3”・・・・・・(1)となる。一方
、参照搬送波の非同期状態では4つの信号点が原点の回
りを回転しているので、同じく入力雑音の大小にかかわ
らず、その平均出力値は第1の監視装置−第2の監視装
置・・・・・・(2)となる。各々平均出力は低域濾波
器4,4゛から得られる。搬送波の同期、非同期は2つ
の監視装置の平均出力の大小により識別できることから
、この実施例・第2の監視装置の平均出力を第1の監視
装置の平均出力で割る方式を示している。割算器6はこ
の操作を行っている。この他の方法としては両者の差を
とることもできる。同期時には(1)式より割算器6の
出力は1より小さくなり、非同期時には(2)式より1
の値をとる。従って割算G6の後の比較器5の閾値とし
ては1より小さい値、例えば0.9を設定しておくこと
により、 比較器入力≧0.9−非同期状態 化較器入力<0.9−同期状態 と識別することができる。この識別の確度は4,4′の
低域濾波器帯域を狭めることにより改善される。図中の
ブロック7は同期、非同期の識別器として働いているこ
とが分かる。
(Embodiment) FIGS. 1(a), (b), and (c) are block diagrams of an embodiment of the present invention. In the figure, the synchronous detector 1, the monitoring device 3, and the 4°4' low-pass filter are the same as those in FIG. Furthermore, although the threshold value setting of comparator 5 is different,
It is the same as that in Figure 2. 3' monitoring device Figure 1 (c
) shows the contents of the monitoring device in Figure 3 (b) rotated by 90 degrees. When a 4-phase PSK signal enters two monitoring devices, if the reference carrier waves are synchronized, its average output value will be the same as that of the first monitoring device 3, regardless of the magnitude of input noise.
〉Second monitoring device 3''...(1).On the other hand, in the asynchronous state of the reference carrier, the four signal points rotate around the origin, so similarly, regardless of the magnitude of input noise, First, the average output value is the first monitoring device - the second monitoring device (2).The respective average outputs are obtained from the low-pass filters 4 and 4.Synchronization of carrier waves, Since asynchrony can be identified by the magnitude of the average output of two monitoring devices, this embodiment shows a method in which the average output of the second monitoring device is divided by the average output of the first monitoring device.The divider 6 is This operation is performed.Another method is to take the difference between the two.During synchronization, the output of the divider 6 is smaller than 1 from equation (1), and when asynchronous, from equation (2), the output is less than 1.
takes the value of Therefore, by setting the threshold of comparator 5 after division G6 to a value smaller than 1, for example 0.9, comparator input≧0.9−asynchronous state comparator input<0.9− It can be identified as a synchronous state. The accuracy of this identification is improved by narrowing the 4,4' low pass filter band. It can be seen that block 7 in the figure works as a synchronous/asynchronous discriminator.

(発明の効果) 以上の様に本発明によれば、雑音レベルが高い状況で動
作する復調器の同期検波器の参照搬送波の同期l非同期
を的確に識別することができる。
(Effects of the Invention) As described above, according to the present invention, it is possible to accurately identify whether the reference carrier is synchronized or unsynchronized in a synchronous detector of a demodulator operating under a high noise level.

なお、第1図(C)は(b)を90’回転させたものに
なっているが、一般の振幅位相変調方式に対しては(b
)と(C)の斜線部分がなるべくかさならないような回
転角を選ぶことが、識別確度を高める上で必要である。
Note that (C) in Figure 1 is a 90' rotation of (b), but for the general amplitude phase modulation method (b)
) and (C) must be selected so that the shaded portions do not overlap as much as possible in order to improve identification accuracy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、 (b)、 (c)は本発明の実施例の
ブロック図、第2図は従来の同期監視装置のブロック図
、第3図(a)、 (b)は監視装置用の読出し専用メ
モリーの例を示す図である。 図中3は第1の監視装置 3は第1の監視装置 7は識別器      を各々示す。 71−1  図 1′ (b)           (c) 7I−2面 71′3 図
FIGS. 1(a), (b), and (c) are block diagrams of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional synchronization monitoring device, and FIGS. 3(a) and (b) are monitoring devices. FIG. 2 is a diagram showing an example of a read-only memory for use in a computer. In the figure, 3 indicates a first monitoring device 3, a first monitoring device 7, and a discriminator, respectively. 71-1 Figure 1' (b) (c) 7I-2 side 71'3 Figure

Claims (1)

【特許請求の範囲】 振幅位相変調波の同期検波出力が供給される同期監視装
置であって、 (a)前記検波出力が正規の信号点位置近傍に受信され
たときに検出信号を出力する第1の検出手段、(b)前
記検波出力が前記正規の信号点位置近傍以外の位置に受
信されたときに検出信号を出力する第2の検出手段、 (c)前記第1の検出手段出力の平均値と前記第2の検
出手段出力の平均値とを比較する比較手段、とから構成
されることを特徴とする同期監視装置。
[Scope of Claims] A synchronous monitoring device to which a synchronous detection output of an amplitude phase modulated wave is supplied, comprising: (a) a synchronous monitoring device that outputs a detection signal when the detection output is received near a regular signal point position; (b) a second detection means that outputs a detection signal when the detection output is received at a position other than the vicinity of the regular signal point position; (c) an output of the first detection means; A synchronous monitoring device comprising: comparison means for comparing the average value with the average value of the output of the second detection means.
JP4883285A 1985-03-12 1985-03-12 Synchronous supervisory device Pending JPS61208345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4883285A JPS61208345A (en) 1985-03-12 1985-03-12 Synchronous supervisory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4883285A JPS61208345A (en) 1985-03-12 1985-03-12 Synchronous supervisory device

Publications (1)

Publication Number Publication Date
JPS61208345A true JPS61208345A (en) 1986-09-16

Family

ID=12814209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4883285A Pending JPS61208345A (en) 1985-03-12 1985-03-12 Synchronous supervisory device

Country Status (1)

Country Link
JP (1) JPS61208345A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0330550A (en) * 1989-06-28 1991-02-08 Nec Corp Demodulation synchronization deciding circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5084121A (en) * 1973-11-26 1975-07-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5084121A (en) * 1973-11-26 1975-07-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0330550A (en) * 1989-06-28 1991-02-08 Nec Corp Demodulation synchronization deciding circuit

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