JPH0614069A - Synchronization detector for digital angular modulation signal demodulation circuit - Google Patents

Abstract

PURPOSE:To obtain the synchronization detection circuit in which synchronization is surely detected in a short time by employing two synchronization discrimination devices whose discrimination speed differs, using the 1st discrimination device operated at a fast speed and having noise immunity to detect asynchronization and to execute a pull-in operation and using the 2nd discrimination device to detect the synchronization state. CONSTITUTION:A 1st synchronization state discrimination device 11 discriminating a synchronization state (P0) based on a relation of phases of a carrier recovery circuit 6 outputs P0 in the normal synchronization state and in a pseudo lock state and outputs no P0 in the asynchronization state. A 2nd discrimination device 12 discriminating the synchronization P0 by using a digital signal processing circuit 5 outputs P0 only in the normal synchronization and outputs no P0 in the pseudo lock state and in the asynchronization state. The occurrence of frequency of pseudo locking is low in a low C/N usually and the discrimination device 11 is used mainly for the discrimination at a low C/N and the 1st and 2nd discrimination devices 11, 12 are used for the discrimination at a strong input state where pseudo locking is often caused. Thus, the synchronization is surely detected in a short time even at a low C/N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a device for detecting the synchronization state of a sync pull-in device used in a demodulation circuit for digital angle modulation signals such as QPSK (Quadrature Phase Shift Keying) and MSK (Minimum Shift Keying). Regarding

[0002]

2. Description of the Related Art Multi-channel PCM using communication satellites
In CS voice broadcasting for broadcasting, a direct modulation method is adopted in which a carrier is directly modulated by a digital signal in which multi-channel signals are time-division multiplexed in order to improve the utilization efficiency of radio waves. In CS voice broadcasting, MSK-modulated radio waves are used at a transmission rate of 24.576 Mbps. In general, a synchronous detection system demodulation circuit for a digital angle modulation wave such as an MSK modulation wave or a QPSK modulation wave is designed so that the capture range of a carrier reproduction circuit is narrowed to about several 100 kHz in order to reduce fixed deterioration. On the other hand, after receiving the radio wave from the satellite,
A frequency converter is installed immediately after the antenna to reduce the loss due to the cable, but the frequency fluctuation of the local oscillator of this frequency converter is expected to be about ± 1.5 MHz. This requires a pull-in circuit when tuning the received signal. As an example of a pull-in circuit for detuning due to such frequency drift, Japanese Patent Laid-Open No. 62-136152.
There is an example disclosed in the publication.

As shown in FIG. 4, in the demodulation circuit for a QPSK modulated signal, when the digital signal processing section does not detect the synchronous state, it is judged to be in the asynchronous state, and the low frequency sweep signal is controlled by the voltage control of the QPSK carrier reproducing circuit. It is superimposed on the control voltage of the oscillator to perform pull-in, and when the synchronization state is detected, superimposition of the sweep signal is stopped.

In FIG. 4, in front of the QPSK demodulation circuit 107, an antenna 101, a mixer 102 as an antenna converter, a local oscillator 103, and a mixer 10 are provided.
4, a local oscillator 105 for tuning, and a bandpass filter 106 for band limiting are provided. Antenna 1
01 receives a radio wave in the 12 GHz band and is converted into a signal in the 1 GHz band by mixer 102 and local oscillator 103. Then, it is further converted into a signal in the 400 MHz band by mixer 104 and local oscillator 105.

The QPSK demodulation circuit 107 is provided with a loop filter 113 and a voltage control oscillator 114 for carrier reproduction. Reference numeral 108 is a digital signal processing unit, and 109 is a synchronization pattern detection unit therein. QP
When the SK demodulation circuit 107 is in the synchronization state, the synchronization pattern is detected, and the synchronization pattern detection unit 109 outputs the detection signal. The capture range of this QPSK demodulation circuit 107 is about ± 500 kHz, and the lock range is ±
It is several MHz. Local oscillator 10 of antenna converter
When 3 is drifting by several MHz, the demodulation circuit 107 cannot synchronize. Therefore, the low frequency oscillator 11
0, a switch 111, and an adder 112 are provided to turn on the switch 111 to add the low frequency signal to the carrier phase error signal when the synchronization pattern is not detected, and sweep the voltage controlled oscillator 114 to perform pull-in. ing.

This utilizes the characteristic that the capture range is narrow but the lock range is wide, and the apparent capture range can be widened. With this configuration, even if the carrier frequency is deviated from the center, it is possible to perform pulling and demodulation.

However, in this synchronization state determination method, synchronization detection cannot be performed without a digital signal processing circuit, and when the input signal is weak and noise increases (low C / N), the digital signal processing circuit operates correctly. There was a problem such as not being able to detect synchronization without doing so. Furthermore, when performing Viterbi decoding or removing phase ambiguity, there is a problem in that it takes time to detect a synchronization pattern and determine a synchronization state, especially in a digital signal processing circuit.

There is a method of not using a digital signal processing circuit as a method of detecting synchronization. It is P by demodulation circuit alone
The synchronization state is determined from the phase relationship of the LL carrier reproduction circuit. The synchronization detection for the QPSK modulated signal is disclosed in Japanese Patent Laid-Open No. 63-164655. In this conventional technique, a signal obtained by phase-shifting the control voltage signal of the voltage controlled oscillator, which is the phase error voltage of the loop, by 90 degrees is used for PLL synchronization detection. That is, when the error voltage is given by sinΦ, the signal used for synchronization detection is cosΦ. Φ = 0 and cosΦ = 1 when the loop is synchronized
In addition, when asynchronous, Φ = 0 to 2π becomes a random phase, and the average value of cosΦ becomes 0. Synchronous and asynchronous detection is performed by this signal.

[0009]

By the way, in the method according to the prior art, the demodulation circuit alone can perform the synchronization detection, is resistant to low C / N, and the time required for the synchronization detection is short. There is a drawback in that the synchronization signal is output even in the so-called pseudo lock state in which the lock is performed in the place where the phase relation is not normal.

Detection and countermeasures against such a pseudo lock are disclosed in Japanese Patent Laid-Open No. 63-30049.

In the first method, the pseudo lock is treated in the same manner as in the asynchronous state, and the synchronization detection is the same as the method by the above-mentioned digital signal processing circuit. Here, the determination is made by the number of code error rates. This method has the drawbacks that it is weak to low C / N and that it takes time to detect.

A second method monitors the control voltage of the voltage controlled oscillator to distinguish between normal lock and pseudo lock, and when it is judged that the lock is pseudo lock, controls the voltage controlled oscillator to move to a normal synchronous state. It is something to try.

A third method is to provide a voltage controlled oscillator with a control voltage limiter or an output frequency limiter to prevent the pseudo lock from occurring.

In the second method, a pseudo lock can be identified. However, the second and third methods are not preferable for mass-produced products. This is because there is a variation in the relationship between the absolute value of the control voltage of the voltage controlled oscillator and the oscillation frequency in each set. Further, this characteristic also changes with changes in ambient temperature. On the other hand, if the limiter range is made too narrow so as not to cause pseudo lock, the pulling operation range becomes too narrow, and if the limiter range is made too wide, pseudo lock may occur due to temperature changes and the like. For this reason, fairly accurate adjustment is required, and since there are variations, it is necessary to measure the control voltage-oscillation frequency characteristics of each unit.

As described above, in the synchronous state detecting method in the prior art, the low C /
There are problems such as weakness in N and time required for detection. Due to the phase relationship of the demodulation circuit, there is a problem of false detection that the pseudo lock state is output as a synchronous state, and there is a problem of adjustment in the dedicated pseudo lock detection circuit. Remains.

The present invention has been made in view of the above problems of the prior art, and its object is to have a low C / N ratio,
It is an object of the present invention to provide a synchronization state detection device for a digital angle modulation signal demodulation circuit, which has a short detection time, is free from erroneous detection, and does not require complicated adjustment.

[0017]

In view of the fact that the frequency of pseudo lock is low in a low C / N state, the above object is to provide a first sync state discriminator for discriminating the sync state from the phase relationship of the demodulation circuit, A second synchronization state discriminator for discriminating the synchronization state by the digital signal processing circuit is provided, and the control means for surely discriminating the pseudo lock state from the combination of the outputs of the two synchronization state discriminators causes a special case in the pseudo lock state. Can be achieved by controlling a voltage controlled oscillator.

[0018]

The first sync state discriminator for discriminating the sync state from the phase relationship of the digital angle modulation signal demodulation circuit outputs the sync state in the normal sync state and the pseudo lock state,
When it is in the asynchronous state, it is output as the asynchronous state. The second sync state discriminator that discriminates the sync state from the state of the digital signal processing circuit outputs the sync state only in the normal sync state, and outputs the asynchronous state in the pseudo lock state and the asynchronous state.

Three states can be discriminated by the two synchronization state discriminators. When the first state discriminator is "synchronous" and the second state discriminator is "synchronous", it is a normal synchronization state. The first state discriminator is "synchronous" and the second state discriminator is "synchronous". When it is "asynchronous", it is in the pseudo lock state, and when the first state discriminator is "asynchronous", it is in the asynchronous state. The first state discriminator is “asynchronous” and the second state discriminator is “synchronous”.

As described above, whether or not the system is in the asynchronous state can be determined only by the first synchronous state discriminator. In the asynchronous state, the voltage controlled oscillator is swept to perform the synchronous pull-in operation. The determination can be reliably performed in a short detection time even in the low C / N state. The output of the first sync state discriminator is used as the information for stopping the sweep, although it takes time to determine whether the normal sync state is reached because the output of the second sync state discriminator is required. It is enough. After that, when it is determined that the pseudo-locked state is established, the voltage-controlled oscillator may be specially controlled by the control means to release the pseudo-locked state and be brought into the normal synchronization state.

Generally, since the frequency of pseudo lock is low in the low C / N state, the first sync state discriminator mainly operates in the low C / N state in the strong input state where the pseudo lock easily occurs. The determination is made by the second synchronization state discriminator. In this way, it is possible to realize a synchronous state detection device that is resistant to low C / N, has a short detection time, and can be surely determined.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronization state detecting device according to the embodiment of the present invention. In FIG. 1, a synchronization state detecting device includes an input terminal 1 for inputting an IF (intermediate frequency) signal of a band-limited digital angle modulated wave.
A quadrature detector 2 including two multipliers, a 90-degree phase shifter and two low-pass filters, A / D converters 3 and 4, a digital signal processing circuit 5, and a carrier reproducing circuit 6. , PLL loop filter 7, VCO (voltage controlled oscillator) 8, VCO control circuit 9, clock recovery circuit 10, first synchronization discriminator 11, second synchronization discriminator 12, and as control means. It is basically composed of the control device 13 of FIG.

Depending on the system, the A / D converters 3 and 4 can be replaced with a comparator and a latch circuit or a data punching circuit. The digital signal processing circuit 5 performs a Viterbi decoding process, an error correction process, a sync signal detection process, a deinterleave process, and the like. The carrier recovery circuit 6 receives the quadrature detection output signal as an input, and the clock recovery circuit 10 supplies the clock signal to the A / D converters 3 and 4 and the signal processing circuit 5. The first sync state discriminator 11 is a carrier regeneration circuit 6
The synchronous state is discriminated from the phase relation of 1), and the second synchronous state discriminator 12 discriminates the synchronous state from the operating state of the digital signal processing circuit 5. The control device 13 receives the outputs of the first and second synchronization state discriminators 11 and 12 as inputs, and receives the VCO control circuit 9
To control.

In FIG. 1, the relationship between the outputs of the first and second synchronization status discriminators, the system synchronization status, and the operation content of the controller 13 is shown in Table 1.

[0026]

[Table 1]

As can be seen from this table, when the outputs of the first and second sync status discriminators are in sync, the system is in sync when the outputs are in sync and the controller 13 does not need to operate. First,
When the output of the second synchronization state discriminator is synchronous or asynchronous, the system is in the pseudo lock state, the control device 13 first releases the pseudo lock, and then performs the synchronous pull-in operation. The control device 13 can be realized by a simple logic circuit, and a microcomputer can also be used.

A concrete example of the VCO control circuit 9 controlled by the control device 13 is shown in FIG. In FIG. 2, reference numeral 22 is an input terminal for a control signal from the control device 13. Reference numeral 21 is a VCO control signal input terminal from the loop filter 7.
25 is a switch, 24 is an adder, 27 is a ROM,
26 is a D / A converter, and 23 is a control output terminal of the VCO 8.

In the VCO control circuit 9 having such a configuration, when the control device 13 determines that the lock is a pseudo lock, it is first set to 2.
2 to open the switch 25, open the PLL loop and release the pseudo lock. At this point, the synchronous state discriminators 11 and 12 are in an asynchronous or asynchronous state. Next, the switch 25 is closed, and the ROM 27 reads D /
The A converter 26 transfers the data for generating the waveform as shown in (A) or (B) to perform the sync pull-in operation.
The transfer of data from the ROM 27 is stopped when the output of the first synchronization status discriminator 11 enters the synchronization status. After that, the state of the second synchronization state discriminator 12 is checked, and if the state is synchronous, the pull-in operation is ended, and if the state is asynchronous, it is assumed that the pseudo lock has occurred again and the pseudo lock is released again. At this time, the waveform of (B) is output when it is the waveform of (A) last time, and the waveform of (A) is output when the previous time is (B). In this way, the pseudo lock is released and the normal synchronization state can be achieved.

However, even if the first synchronization state discriminator 11 is synchronous and the second synchronization state discriminator 12 is asynchronous, there are cases where the pseudo lock state is not established. For example, there is a case where the input signal level is low and is synchronized in the analog system, but in the digital system there are too many errors and the second synchronous state discriminator outputs as asynchronous. Even in such a case, the same procedure as in the case of the pseudo lock is repeated several times, and if the synchronized state is not achieved even after that, some warning is output and the pull-in operation may be stopped. That is, when the first synchronous state detector 11 is asynchronous, the pull-in operation after the release in the pseudo lock may be performed.

FIG. 3 shows another embodiment of the present invention, in which the oscillator for the regenerated carrier of the quadrature detector is a fixed frequency oscillator, and the local oscillator of the heterodyne circuit is V of the PLL circuit.
The case where the present invention is applied to a digital angle modulation signal demodulation circuit having a structure of CO is shown. The structure of this demodulation circuit is described in detail in JP-A-63-30049.
There is a feature that stable demodulation characteristics can be obtained even with a frequency shift of the input signal. In FIG. 3, the same reference numerals as those in FIG. 1 indicate the same functions. 31 is a fixed frequency oscillator, 32 is an input signal terminal, 33 is a multiplier,
34 is a bandpass filter (BPF),
The multiplier 33 and the BPF 34 form a heterodyne circuit (frequency conversion circuit). The operation is the same as in the case of FIG. 1 except that the frequency of the VCO 8 is different.

[0032]

As is apparent from the above description, according to the inventions of claims 1 to 3 configured as described above, two synchronous state discriminators having different discriminating speeds are provided, and asynchronous detection is performed. Is performed by the first synchronization state discriminator that is fast and has low C / N, so that the pull-in operation can be started or the pull-in sweep operation can be stopped in a short time. Further, since the second synchronization state discriminator which can surely discriminate the synchronization is also used, the pseudo lock state can be surely detected without requiring complicated adjustment.

As a result, it is possible to realize a synchronization state detecting device for a digital angle modulation signal demodulation circuit which is resistant to low C / N, has a short detection time, is free from erroneous detection, and does not require complicated adjustment.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of a VCO control circuit.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional technique.

[Explanation of symbols]

 2 quadrature detector 5 digital signal processing circuit 6 carrier reproducing circuit 8 VCO (voltage controlled oscillator) 9 VCO control circuit 11 first synchronization state discriminator 12 second synchronization state discriminator 13 controller

Claims (3)

[Claims] 1. A digital angle controller comprising a voltage controlled oscillator, a carrier regenerating circuit, a clock regenerating circuit, and a digital signal processing circuit for performing processing such as error correction processing, demodulation signal detection processing, deinterleaving processing of demodulated signals. A synchronization detection device for a digital angle modulation signal demodulation circuit, which is provided in a modulation signal demodulation circuit and detects a synchronization state, comprising: a first synchronization state discriminator that discriminates a system synchronization state from a phase relationship of the carrier reproduction circuit; A second synchronous state discriminator for discriminating a synchronous state from the state of the digital signal processing circuit; a voltage controlled oscillator control circuit for controlling the voltage controlled oscillator; and outputs of the first and second synchronous state discriminators. It is used as an input, and the voltage control oscillator control circuit is controlled by determining the system synchronization state from the output states of the first and second synchronization state discriminators. Synchronization detection apparatus in a digital angle-modulated signal demodulation circuit, characterized in that it comprises a control means for the. 2. The control means determines that the system is in a pseudo lock state when the output of the first synchronous state discriminator is in the synchronous state and the output of the second synchronous state discriminator is in the asynchronous state. 2. The synchronization detecting device for a digital angle modulation signal demodulation circuit according to claim 1, wherein the voltage controlled oscillator control circuit is controlled so as to release the pseudo lock state and move toward a normal synchronization state. 3. The control means, if the normal synchronization state is not obtained even if the control is performed so as to move toward the normal synchronization state, the operation from the pseudo lock state release to the retracting operation is performed a certain number of times or a certain time. 3. The synchronization detecting device for a digital angle modulation signal demodulation circuit according to claim 2, wherein the voltage control oscillator control circuit is controlled so as to stop the pull-in operation when the normal synchronization state is not achieved.