JPH09238173A - Method and device for synchronizing frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize the frequency of the receiving carrier of orthogonal amplitude modulated signals having a large multilevel value to that of a reproduced carrier in a short time. SOLUTION: In order to synchronize the frequency of the receiving carrier of orthogonal amplitude modulated signals having a large multilevel value to that of a reproduced carrier, a symbol point which is to be utilized for frequency discrimination is defined in advance out of symbol points a-j in an I-Q plane and, when the signal point corresponding to the defined symbol point is received, the frequency synchronization is established in a short time by rotating I-Q orthogonal coordinate axes by moving the signal points on the straight line L connecting an origin O to an ideal symbol point having the largest amplitude value. In addition, by repeating the synchronizing process by switching the receiving symbol point utilized for discrimination in accordance with the synchronous state, the phase error which occurs when the frequencies are synchronized to each other is reduced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to quadrature amplitude modulation (Q
The present invention relates to a frequency synchronization method and an apparatus for synchronizing the frequency of a modulated carrier and the frequency of a reproduced carrier when demodulating an (AM) signal.

[0002]

2. Description of the Related Art In quadrature amplitude modulation, two independent signals are amplitude-modulated by two orthogonal carrier waves,
They are added together to form the transmitted signal. On the receiving side that receives this signal, the received signal is branched into two, one of them is multiplied by the regenerated carrier generated by the oscillator, and the other is multiplied by a signal whose phase is shifted by π / 2. The in-phase signal and the quadrature signal are demodulated by the detection, the amplitudes of these signals are identified, and the multi-level signal represented by the combination of the in-phase signal and the quadrature signal amplitude is decoded.

This received signal can be displayed on the IQ plane in which the in-phase component is represented by the I axis and the quadrature component is represented by the Q axis. FIG. 54 shows the first quadrant of the IQ plane,
The ideal symbol point in 56QAM, that is, the point where the carrier power to noise power ratio is theoretically maximum is indicated by a black circle. When the frequencies of the modulated wave and the reproduced carrier wave are deviated, the symbol point of the received signal is received at a position deviated from the original ideal symbol point on the IQ plane. This rotation angle corresponds to the phase difference between the modulated wave and the reproduced carrier wave. The radius of the circular arc in FIG. 55 corresponds to the amplitude of each ideal symbol point, and when the frequencies of the two carrier waves are different, the symbol point received on the IQ plane with a deviation from the original position is as follows. It is observed that an arc is drawn.

When the frequencies of the two carriers are equal and have a nonzero phase difference, the reception position of the symbol point rotates about the origin O by an angle corresponding to the phase difference. Since the phase difference is constant, the reception symbol point appears at the position of the black circle in FIG. 56 on the IQ plane. Here, FIG. 56 is 16Q for simplicity.
The case of AM is shown. I and Q are IQ orthogonal coordinates with the phase of the reproduced carrier as a reference, and the received symbol point rotates by an angle corresponding to the phase difference.

When the two carriers have a frequency difference,
The received symbol points rotate around the origin O one after another, and the origin O
Seems to rotate at a constant speed around. If the symbol rate is sufficiently large, a plurality of concentric circles having a radius of the amplitude of the received symbol point can be seen on the IQ plane as shown in FIG. Here, FIG. 57 shows the case of 16QAM for simplicity.

On the receiving side, this frequency difference is eliminated and rotation is stopped.

Conventionally, in order to compare the frequency of the received carrier wave and the frequency of the reproduced carrier wave and correct the frequency deviation,
The following methods are used.

FIG. 58 shows the configuration of a digital QAM receiver using a conventional frequency synchronizer. The A / D converter 43, the detector 44, the roll-off filter 45, the bit converter 46, and the frequency phase comparator. It consists of 47.

In FIG. 58, the received modulated wave down-converted to the intermediate frequency (IF) by the tuner is A / D.
The converter 43 converts it into a digital signal, and the detector 44 synchronously detects it to decompose it into an in-phase signal (I signal) and a quadrature signal (Q signal). After that, the waveform is shaped by the roll-off filter 45, the shift between the frequency and the phase is detected by the frequency / phase comparator 47, and the result is fed back to the detector 44. Then, the bit converter 46 converts the IQ signal into a binary bit string.

The frequency phase comparator 47 detects the frequency deviation ΔF and the phase deviation Δθ of the IQ signal output from the roll-off filter 45 and feeds it back to the detector 44.
The detector 44 reproduces the carrier wave with ΔF and Δθ and synchronously detects the received wave.

As shown in FIG. 59, the frequency / phase comparator 47 includes an amplitude calculation circuit 48, a maximum amplitude value identification circuit 49, a symbol point determination circuit 50, a phase calculation circuit 51, a phase rotation circuit 52, a phase comparison circuit 53, and It is composed of a frequency comparison circuit 54.

In FIG. 59, assuming that the signal point received for the first time after resetting the system is point 55 in FIG. 60 and the magnitudes of its in-phase component and quadrature component are i and q, the amplitude calculation circuit 48 calculates √ ( The distance of the received signal point from the origin O, that is, the amplitude is obtained by the calculation of i ² + q ² ) and is transmitted to the maximum amplitude value identification circuit 49 and the symbol point determination circuit 50.

On the other hand, in the phase calculation circuit 51, tan
By the calculation of ^-1 (q / i), the angle between the straight line connecting the reception signal point and the origin O and the I axis, that is, the phase of the reception signal point is obtained and transmitted to the phase rotation circuit 52.

The calculated amplitude value is the maximum amplitude value identification circuit 4
At 9 it is discriminated whether or not the received signal point is the signal point having the maximum amplitude value, and if it is the maximum amplitude value, it is notified to the phase comparison circuit 53. At the same time, return to yourself. Once the signal having the maximum amplitude value is received and the output of the identification circuit 49 becomes active, the amplitude value determination process is not performed and the output is stopped until the next system reset.

The phase rotation circuit 52 transfers the value received from the phase calculation circuit 51 to the symbol point determination circuit 50 and the phase comparison circuit 53 as it is.

The symbol point determination circuit 50 determines the original symbol point (which will be referred to as an ideal symbol point) position of the received signal from the obtained amplitude and phase, and compares the phases of the ideal symbol points with each other. Tell circuit 53.

When the value of the maximum amplitude value identification circuit 49 is not active, the phase comparison circuit 53 does not perform the phase comparison process because the reception signal point is not the signal point having the maximum amplitude value, and the information of the next reception signal is not obtained. Wait for you to arrive.

When the value of the maximum amplitude value identification circuit 49 is active, it is determined that the received signal point is a symbol point existing on the straight line 56. Here, the received signal point is the point 55 in FIG.
Then, the magnitude θ _R of the phase shift from the straight line 56 is obtained. Size theta _R of the phase shift of the received point, in the case of 256QAM, the phase of the linear 56 is a [pi / 4, in the phase comparator circuit _{53, θ R = (π /} 4) -tan -1 (q / i) is calculated. Then, θ _R is transmitted to the detector 44 of FIG. 58, and also to the frequency comparison circuit 54 and the phase rotation circuit 52. Where θ _R is I based on the received carrier
It can also be said that it represents the deviation angle between the -Q Cartesian coordinate system and the IQ Cartesian coordinate system based on the reproduced carrier wave.

The frequency comparison circuit 54 is a phase comparison circuit 53.
If outputs θ _R , the value is stored.

Then, the next received signal is received. This point is designated as point 57 in FIG. Amplitude and phase are amplitude calculation circuit 48
The phase is calculated by the phase calculation circuit 51, and the phase is a value θ _S rotated by θ _R by the phase rotation circuit 52 and transmitted to the symbol point determination circuit 50 and the phase comparison circuit 53. The reception point after rotation is point 58 in FIG.

The symbol point determination circuit 50 determines the ideal symbol point corresponding to the received signal point from the amplitude and the corrected phase. This point is designated as point 59 in FIG. Then, the phase θ _T of the ideal symbol point is transmitted to the phase comparison circuit 53.

In the phase comparison circuit 53, the phase difference Δθ between θ _S and θ _T and Δθ = θ _T −θ _S are obtained and transmitted to the wave detector 44 of FIG. 58 and also to the frequency comparison circuit 54 and the phase rotation circuit 52. .

In the frequency comparison circuit 54, the magnitude of the frequency deviation ΔF is obtained as ΔF = (1 / 2π) (Δθ / t _sym ) since the phase changes by Δθ in one symbol time t _sym , and the result is shown in FIG. Notify the detector 44.

For the next received signal, the phase rotation circuit 5
2 rotates the phase by θ _R + Δθ. Similar processing is performed for the subsequent received signals.

As described above, according to the conventional method, when the frequencies of the received carrier and the reproduced carrier are not synchronized, the IQ orthogonal coordinate axis is determined, that is, the frequency synchronization processing is performed by the above procedure.

[0026]

However, the above-mentioned conventional frequency synchronization method has a problem that the frequency synchronization time increases as the number of multivalues increases. That is, in the conventional method, the symbol point having the maximum amplitude value, that is, I
-I-only after receiving the symbol points at the four corners on the Q-plane.
The Q orthogonal coordinate axis is established, and the reproduced carrier frequency is synchronized with the received carrier frequency. The probability of receiving the symbol points at the four corners is 16 if the probability of occurrence of all the symbol points is equal.
QAM is 1/4, 64QAM is 1/16, 256Q
AM 1 / 64th, 1024QAM 1 / 26th,
It decreases as the multi-valued number increases, and thus the frequency synchronization time also increases as the multi-valued number increases.

The present invention solves such a conventional problem. Even when the number of multivalues is large, the first IQ orthogonal coordinate axis can be quickly determined and the frequency synchronization time can be shortened. An object of the present invention is to provide a frequency synchronization method and an apparatus thereof.

[0028]

As shown in FIG. 53, the frequency synchronization method and apparatus according to the present invention synchronizes the frequencies of the reception carrier and the reproduction carrier of a quadrature amplitude modulation signal having a large number of levels, Symbol point a on the IQ plane
In j, the symbol points used for frequency determination are defined in advance, and when the signal points corresponding to the defined symbol points are received, they are placed on the straight line L connecting the origin O and the ideal symbol point having the maximum amplitude value. By rotating the IQ orthogonal coordinate axes so as to move, frequency synchronization is established in a short time, and the reception symbol points used for determination are switched according to the synchronization state, and the synchronization processing is repeated to obtain the phase at synchronization. It reduces the error.

According to the present invention, even in the case of quadrature amplitude modulation with many multi-valued numbers, only the four corner symbol points having the maximum amplitude value are used to synchronize the received carrier frequency and the reproduced carrier frequency. Compared with the above, by using the four corners and the surrounding symbol points, the reception probability of the symbol points used for the determination is increased, the first IQ orthogonal coordinate axis is quickly determined, and the synchronization of the two carrier frequencies is established. can do.

Further, the frequency synchronization is established by using the symbol points used for the determination as the four corner points and the symbol points around the four corner points, and then the symbol points used for the determination are the four corner points and the narrower range of the symbols around the four corner points. Frequency synchronization processing is performed only at points, and finally, frequency synchronization processing is performed only at the symbol points on the diagonal line of the IQ plane, thereby establishing frequency synchronization in a short time and reducing phase error. be able to.

[0031]

The invention according to claim 1 of the present invention has the largest amplitude value because the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation are synchronized. When the reception symbol point or the reception symbol point having the second largest amplitude value is received, the Cartesian coordinate axes are moved so as to move the reception symbol point on the straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. It is characterized by rotating, and in the case of quadrature amplitude modulation with a large multi-valued number, synchronization can be established in one-third the time as compared with the conventional case.

Further, according to the second aspect of the present invention, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the largest amplitude value, or When a reception symbol point having the second largest amplitude value or a reception symbol point having the fourth largest amplitude value is received, the reception symbol point is on a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. The quadrature coordinate axis is rotated so as to move to the position 1. In the case of quadrature amplitude modulation with a large multi-valued number, synchronization can be established in 1/4 the time as compared with the conventional case.

Further, according to the third aspect of the invention, since the frequency of the modulated carrier of the multi-valued quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the largest amplitude value, or When the reception symbol point having the second largest amplitude value, the reception symbol point having the third largest amplitude value, or the reception symbol point having the fourth largest amplitude value is received, the reception symbol point is defined as the origin O. It is characterized by rotating the Cartesian coordinate axis so as to move on a straight line connecting the ideal symbol point having the maximum amplitude value.
Synchronization can be established in 1/6 the time compared to the conventional case.

The invention described in claim 4 is the same as claim 1
The frequency synchronization method according to any one of claims 1 to 3, wherein the reception symbol points that determine the rotation amount of the orthogonal coordinate axes are switched according to the frequency synchronization state. In the case of a large number of quadrature amplitude modulations, the synchronization can be established in 1/6 the time as compared with the conventional case, and the phase error at the time of synchronization can be reduced.

Further, according to the invention of claim 5, since the frequency of the modulated carrier of the multi-valued quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the smallest amplitude value, or When the reception symbol point having the third smallest amplitude value is received, the orthogonal coordinate axes are rotated so as to move the reception symbol point on the straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. In the case of quadrature amplitude modulation with a large multi-valued number, it is possible to establish synchronization in half the time compared with the conventional case.

Further, according to the invention of claim 6, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the smallest amplitude value, or When a reception symbol point having the third smallest amplitude value or a reception symbol point having the fifth smallest amplitude value is received, the reception symbol point is on a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. The quadrature coordinate axis is rotated so as to move to the position 1. In the case of quadrature amplitude modulation with a large multi-valued number, synchronization can be established in 1/4 the time as compared with the conventional case.

The invention described in claim 7 is the same as claim 5
Alternatively, in the frequency synchronization method according to claim 6, the reception symbol points that determine the rotation amount of the orthogonal coordinate axes are switched according to the frequency synchronization state, and the orthogonality with a large multi-valued number is used. In the case of amplitude modulation, synchronization can be established in a quarter of the time as compared with the conventional case, and the phase error at the time of synchronization can be reduced.

Further, according to the invention of claim 8, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation are synchronized, the reception symbol point having the largest amplitude value, or When the reception symbol point having the smallest amplitude value is received, the orthogonal coordinate axis is rotated so as to move the reception symbol point to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. In the case of quadrature amplitude modulation with a large multi-valued number,
Synchronization can be established in half the time as compared with the conventional case.

In the ninth aspect of the invention, since the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier wave used for demodulation, the reception symbol point having the largest amplitude value, or When the reception symbol point having the second largest amplitude value or the reception symbol point having the smallest amplitude value is received, the reception symbol point is moved to the straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. The quadrature coordinate axes are rotated as described above, and in the case of quadrature amplitude modulation with a large multi-valued number, synchronization can be established in a quarter time as compared with the conventional case.

In the tenth aspect of the invention, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation are synchronized, the reception symbol point having the largest amplitude value, or When the reception symbol point having the second largest amplitude value, the reception symbol point having the fourth largest amplitude value, or the reception symbol point having the smallest amplitude value is received, the reception symbol point is set to the origin O and the maximum amplitude. It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting an ideal symbol point having a value, and in the case of quadrature amplitude modulation with a large number of levels, it is 1/5 compared to the conventional case. Synchronization can be established at the time of.

Further, according to the invention of claim 11, since the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation are synchronized, the reception symbol point having the largest amplitude value, or Receives the received symbol point with the second largest amplitude value, the received symbol point with the third largest amplitude value, the received symbol point with the fourth largest amplitude value, or the received symbol point with the smallest amplitude value The received symbol point is the origin O
It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting the ideal symbol point having the maximum amplitude value. Synchronization can be established in a fraction of the time.

The invention according to claim 12 is the frequency synchronization method according to any one of claims 8 to 11, wherein the received symbol determines the rotation amount of the orthogonal coordinate axes according to the frequency synchronization state. The feature is that the points are switched, and in the case of quadrature amplitude modulation with a large number of multivalues, synchronization can be established in a shorter time than in the past, and the phase error at the time of synchronization is further reduced. be able to.

Further, in the invention described in claim 13, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the largest amplitude value, or When the reception symbol point having the smallest amplitude value or the reception symbol point having the third smallest amplitude value is received, the reception symbol point is moved to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. It is characterized by rotating the Cartesian coordinate axis so that, in the case of quadrature amplitude modulation with a large multi-valued number,
Synchronization can be established in one-third the time as compared to the conventional case.

In the fourteenth aspect of the present invention, since the frequency of the modulated carrier of the multi-valued quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the largest amplitude value, or When the reception symbol point having the second largest amplitude value, the reception symbol point having the smallest amplitude value, or the reception symbol point having the third smallest amplitude value is received, the reception symbol point is set to the origin O and the maximum amplitude. It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting an ideal symbol point having a value, and in the case of quadrature amplitude modulation with a large number of levels, it is 1/5 compared to the conventional case. Synchronization can be established at the time of.

Further, in the invention as set forth in claim 15, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation are synchronized, the reception symbol point having the largest amplitude value, or Receives the received symbol point with the second largest amplitude value, the received symbol point with the fourth largest amplitude value, the received symbol point with the smallest amplitude value, or the received symbol point with the third smallest amplitude value The received symbol point is the origin O
It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting the ideal symbol point having the maximum amplitude value. Synchronization can be established in a fraction of the time.

Further, the invention according to claim 16 is the reception symbol point having the largest amplitude value, the reception symbol point having the second largest amplitude value, or the reception symbol point having the third largest amplitude value. , Or the reception symbol point having the fourth largest amplitude value, the reception symbol point having the smallest amplitude value, or the reception symbol point having the third smallest amplitude value, the reception symbol point is defined as the origin O. It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting to the ideal symbol point having the maximum amplitude value. Synchronization can be established in 1 time.

The invention described in claim 17 is the frequency synchronization method according to any one of claims 13 to 16, wherein the received symbol determines the rotation amount of the orthogonal coordinate axes according to the frequency synchronization state. The feature is that the points are switched, and in the case of quadrature amplitude modulation with a large number of multivalues, synchronization can be established in a shorter time than in the past, and the phase error at the time of synchronization is further reduced. be able to.

In the eighteenth aspect of the present invention, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the largest amplitude value, or When the reception symbol point having the smallest amplitude value, the reception symbol point having the third smallest amplitude value, or the reception symbol point having the fifth smallest amplitude value is received, the reception symbol point is set to the origin O and the maximum amplitude. It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting an ideal symbol point having a value, and in the case of quadrature amplitude modulation with a large number of levels, it is 1/5 compared to the conventional case. Synchronization can be established at the time of.

In the nineteenth aspect of the invention, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation are synchronized, the reception symbol point having the largest amplitude value, or Receives the received symbol point with the second largest amplitude value, the received symbol point with the smallest amplitude value, the received symbol point with the third smallest amplitude value, or the received symbol point with the fifth smallest amplitude value The received symbol point is the origin O
It is characterized in that the orthogonal coordinate axes are rotated so as to move on a straight line connecting the ideal symbol point having the maximum amplitude value. Synchronization can be established in a fraction of the time.

Further, in the invention as set forth in claim 20, since the frequency of the modulated carrier of the multi-valued quadrature amplitude modulation signal is synchronized with the frequency of the reproduced carrier used for demodulation, the reception symbol point having the largest amplitude value, or Received symbol point having the second largest amplitude value, or received symbol point having the fourth largest amplitude value, or received symbol point having the smallest amplitude value, or received symbol point having the third smallest amplitude value, or When the reception symbol point having the fifth smallest amplitude value is received, the orthogonal coordinate axes are rotated so that the reception symbol point is moved to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. In the case of quadrature amplitude modulation having a large multi-valued number, it is possible to establish synchronization in 1/8 the time compared with the conventional case.

Further, in the invention described in claim 21, since the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation are synchronized, the reception symbol point having the largest amplitude value, or Received symbol point having the second largest amplitude value, received symbol point having the third largest amplitude value, or received symbol point having the fourth largest amplitude value, or received symbol point having the smallest amplitude value, or When a reception symbol point having the third smallest amplitude value or a reception symbol point having the fifth smallest amplitude value is received, the reception symbol point is on a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. The quadrature coordinate axis is rotated so as to move to 1), and in the case of quadrature amplitude modulation with a large multi-valued number, it is 1/10 of the conventional one. Synchronization can be established in time.

The invention according to claim 22 is the frequency synchronization method according to any one of claims 18 to 21, wherein the received symbol determines the rotation amount of the orthogonal coordinate axes according to the frequency synchronization state. The feature is that the points are switched, and in the case of quadrature amplitude modulation with a large number of multivalues, synchronization can be established in a shorter time than in the past, and the phase error at the time of synchronization is further reduced. be able to.

The invention described in claim 23 is a frequency synchronizer for synchronizing the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal with the frequency of the reproduced carrier used for demodulation. A frequency phase comparison means for carrying out the frequency synchronization method according to any one of claims 22 to 23 is provided, and in the case of quadrature amplitude modulation having a large number of multi-levels, synchronization is performed in a shorter time compared to the conventional case. It can be established, and the phase error at the time of synchronization can be reduced.

According to a twenty-fourth aspect of the present invention, the frequency / phase comparison means determines the amplitude calculation circuit for obtaining the amplitude of the received signal point, and whether the obtained amplitude value is maximum or minimum, or how large. , Or a plurality of amplitude value identification circuits that identify the smallest value, a symbol point determination circuit that determines an ideal symbol point corresponding to the received signal point from the obtained amplitude values, and a phase calculation that obtains the phase of the received signal point Circuit, an adder circuit that adds the outputs of a plurality of amplitude value identification circuits, a phase comparison circuit that obtains the phase difference between the received signal point and the ideal symbol point according to the output of the adder circuit, and a receive operation that depends on the obtained phase difference. It is equipped with a phase rotation circuit that rotates the phase of the signal point, and a frequency comparison circuit that obtains the magnitude of the frequency deviation from the obtained phase difference. A short time it is possible to establish synchronization, it is possible to further reduce the synchronization time of the phase error.

Further, in the invention described in claim 25, the frequency phase comparison means is provided with an amplitude limiting circuit for limiting the transmission of the output of each amplitude value identifying circuit to the adding circuit depending on the position of the reception signal point. In the case of quadrature amplitude modulation having a large number of multivalues, it is possible to establish synchronization in a shorter time than in the conventional case and further reduce the phase error at the time of synchronization.

(Embodiment 1) Hereinafter, a frequency synchronizer according to a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. The coordinates in FIGS. 3 and 4 are
For simplicity, only the first quadrant of the IQ plane in 256QAM is shown, but the second, third, and fourth quadrants are rotated about the origin O.

FIG. 1 shows the configuration of a QAM receiver using a frequency synchronizer according to the first embodiment of the present invention, which includes an A / D converter 1, a detector 2, a roll-off filter 3 and a bit. It is composed of a converter 4 and a frequency correlator / phase comparator 5.

In FIG. 1, the received modulated wave down-converted to the intermediate frequency (IF) by the tuner is A / D.
The converter 1 converts the signal into a digital signal, the detector 2 performs synchronous detection, and decomposes into an in-phase signal (I signal) and a quadrature signal (Q signal). After that, the waveform is shaped by the roll-off filter 3, the deviation between the frequency and the phase is detected by the frequency / phase comparator 5, and the result is fed back to the detector 2. Then, the bit converter 4 converts the IQ signal into a binary bit string.

The frequency / phase comparator 5 detects the frequency deviation ΔF and the phase deviation Δθ of the IQ signal output from the roll-off filter 3 and feeds it back to the detector 2. The detector 2 reproduces the carrier wave with ΔF and Δθ and synchronously detects the received wave.

As shown in FIG. 2, the frequency phase comparator 5 includes an amplitude calculating circuit 6, a maximum amplitude value identifying circuit 7, and an amplitude value A.
Discrimination circuit 8, symbol point determination circuit 9, addition circuit 10, phase calculation circuit 11, phase rotation circuit 12, phase comparison circuit 1
3. Comprised of a frequency comparison circuit 14.

In FIG. 2, when the signal point received for the first time after resetting the system is point 21 in FIG. 4 and the magnitudes of the in-phase component and the quadrature component are i and q, the amplitude calculation circuit 6
By calculating √ (i ² + q ² ), the distance from the origin O of the received signal point, that is, the amplitude is obtained, and transmitted to the maximum amplitude value identification circuit 7, the amplitude value A identification circuit 8, and the symbol point determination circuit 9. .

On the other hand, in the phase calculation circuit 11, tan
By the calculation of ^-1 (q / i), the angle between the straight line connecting the reception signal point and the origin O and the I axis, that is, the phase of the reception signal point is obtained and transmitted to the phase rotation circuit 12.

The calculated amplitude value is the maximum amplitude value identification circuit 7
At, it is discriminated whether or not the received signal point is the signal point having the maximum amplitude value, and if it is the maximum amplitude value, the fact is notified to the phase comparison circuit 10. The signal having the maximum amplitude value corresponds to the symbol point 16 and the radius of the arc 19, as shown in FIG.

At the same time, the amplitude value A discrimination circuit 8 discriminates whether or not the signal point has the second largest amplitude value, and if so, informs the addition circuit 10 to that effect. As shown in FIG. 3, the amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20.

The adder circuit 10 adds the received signals and sends them to the phase comparison circuit 13. If the received signal has the maximum amplitude value or the second largest amplitude value, the adder circuit 1
The 0 output becomes active. The value of the adder circuit 10 is returned to itself, and when the value is active, the addition processing is not performed at the subsequent reception signal points and the output is stopped.

The phase rotation circuit 12 transmits the value received from the phase calculation circuit 11 as it is to the symbol point determination circuit 9 and the phase comparison circuit 14.

The symbol point determination circuit 9 determines the position of the original symbol point of the received signal, that is, the ideal symbol point, from the obtained amplitude and phase, and transmits the phase of the ideal symbol point to the phase comparison circuit 13.

When the value of the adder circuit 10 is not active, the phase comparison circuit 13 does not perform the phase comparison process because the received signal point is not the signal point having the maximum amplitude value or the second largest amplitude value, and the system is Wait for the next signal to be received immediately after reset.

When the value of the adder circuit 10 is active, it is determined that the received signal point is a symbol point existing on the straight line 15. Here, the received signal point is point 21 in FIG. 4, and the straight line 1
The amount of phase shift θ ₁ from 5 is obtained. Size theta ₁ of the phase shift of the received point, in the case of 256QAM, the phase of the linear 15 is a [pi / 4, in the phase comparator circuit _{13, θ 1 = (π /} 4) -tan -1 (q / i) Obtained by the calculation of (1). Then, while transmitting θ ₁ to the detector 2 of FIG. 1, the frequency comparison circuit 14 and the phase rotation circuit 12
Tell Where θ ₁ is I− based on the received carrier.
It can also be said that it represents a deviation angle between the Q orthogonal coordinate system and the IQ orthogonal coordinate system based on the reproduced carrier wave.

The frequency comparison circuit 14 is the phase comparison circuit 13
When outputs θ ₁ , the value is stored.

Then, the next received signal is received. This point is designated as point 22 in FIG. Although the amplitude and the phase are calculated by the amplitude calculating circuit 6 and the phase calculating circuit 11, the phase is a value θ ₂ rotated by θ ₁ by the phase rotating circuit 12 and transmitted to the symbol point determining circuit 9 and the phase comparing circuit 13. The reception point after rotation is point 23 in FIG.

The symbol point determination circuit 9 determines the ideal symbol point corresponding to the received signal point from the amplitude and the corrected phase. This point is designated as point 24 in FIG. Then, the phase θ ₃ of the ideal symbol point is transmitted to the phase comparison circuit 13.

In the phase comparison circuit 13, the phase difference Δθ between θ ₂ and θ ₃ , Δθ = θ ₃ −θ ₂ (2) is calculated and transmitted to the detector 2 of FIG. It is transmitted to the phase rotation circuit 12.

In the frequency comparison circuit 14, since the phase changes by Δθ in one symbol time t _sym , the magnitude ΔF of the frequency shift is ΔF = (1 / 2π) (Δθ / t _sym ) (3) And transmit it to the detector 2 of FIG.

Regarding the next received signal, the phase rotation circuit 1
2 rotates the phase by θ ₁ + Δθ. Similar processing is performed for the subsequent received signals.

As described above, according to the first embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the second largest amplitude value is received. It has a feature that frequency can be compared.

When frequency comparison is started at the receiving point having the second largest amplitude value, a phase error of ± 4.1 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude of deviation Δθ to the detector 2 of FIG. 1 and performing complex multiplication.

Further, if the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 12/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. The probability of occurrence is three times as high as the probability of one fourth, and thus synchronization can be established in one third of the time.

(Second Embodiment) FIG. 5 shows the configuration of a frequency phase comparator 5 according to a second embodiment of the present invention. The overall configuration of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Same as 1. The coordinates of FIG. 6 show only the first quadrant of the IQ plane in 256QAM for simplicity, but the second, third, and fourth quadrants are rotated about the origin O. In addition, in FIG.
The same reference numerals are given to the portions overlapping with, and the duplicate description will be omitted.

In this embodiment, the maximum amplitude value identification circuit 7
In parallel with the amplitude value A identifying circuit 8 and the amplitude value B identifying circuit 25.
Is provided. The maximum amplitude value identifying circuit 7 identifies whether the received signal point is a signal point having the maximum amplitude value, and the amplitude value B identifying circuit 25 determines that the received signal point has the fourth largest amplitude value. Is identified. Once identified as signal points with these corresponding amplitude values,
The addition circuit 10 is notified of that fact.

As shown in FIG. 6, the amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. Further, the amplitude value B, that is, the signal point having the fourth largest amplitude value corresponds to the symbol point 26 and has the amplitude value corresponding to the radius of the arc 27.

As described above, according to the second embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the fourth If a signal point with a large amplitude value is received at
It has the feature of frequency comparison.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 16/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are four times as many occurrence probabilities as there are four quarter probabilities, so synchronization can be established in a quarter of the time.

(Third Embodiment) FIG. 7 shows the configuration of a frequency / phase comparator 5 according to a third embodiment of the present invention. The overall configuration of a QAM receiver including the frequency / phase comparator 5 is as shown in FIG. Same as 1. Note that the coordinates in FIG. 8 show only the first quadrant of the IQ plane in 256QAM for simplicity, but the second, third, and fourth quadrants are rotated about the origin O. . Further, in FIG. 7, the same parts as those in FIG.

In this embodiment, the maximum amplitude value identifying circuit 7
In parallel with the amplitude value A discrimination circuit 8 and the amplitude value B discrimination circuit 2
5. An amplitude value C identification circuit 28 is provided. The maximum amplitude value identifying circuit 7 identifies whether the received signal point is a signal point having the maximum amplitude value. The amplitude value B identifying circuit 25 identifies whether the received signal point is the signal point having the fourth largest amplitude value. The amplitude value C identifying circuit 28 identifies whether or not the received signal point is the signal point having the third largest amplitude value. If it is identified that the signal point has the corresponding amplitude value, the fact is notified to the adder circuit 10.

As shown in FIG. 8, the amplitude value A, that is, the signal point having the second largest amplitude value is the symbol points 17 and 18.
And has an amplitude value corresponding to the radius of the arc 20. Further, the amplitude value B, that is, the signal point having the fourth largest amplitude value corresponds to the symbol point 26 and has the amplitude value corresponding to the radius of the arc 27. Further, the amplitude value C, that is, the signal point having the third largest amplitude value corresponds to the symbol points 29 and 30, and has the amplitude value corresponding to the radius of the arc 31.

As described above, according to the third embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value, or the third signal point having the largest amplitude value. When the signal point having the largest amplitude value or the signal point having the fourth largest amplitude value is received, the frequencies can be compared.

When frequency comparison is started at the signal point having the third largest amplitude value, a phase error of ± 8.7 ° may occur as shown in FIG. It can be corrected by feeding back the magnitude Δθ of the signal to the detector 2 of FIG.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 24/256, so that 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are 6 times more probabilities of occurrence than 4 times the probability, so that synchronization can be established in 1/6 the time.

(Embodiment 4) FIG. 9 shows the configuration of a frequency phase comparator 5 according to a fourth embodiment of the present invention. The overall configuration of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Same as 1. Note that the coordinates in FIG. 10 show only the first quadrant of the IQ plane in 256QAM for simplicity, but regarding the second, third, and fourth quadrants,
It is rotated around the origin O. In FIG. 9, the same parts as those in FIG. 7 are designated by the same reference numerals, and the duplicated description will be omitted.

In this embodiment, the amplitude value limiting circuit 3 is shown in FIG.
2 is added. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 8, 25, 2 depending on the position of the received signal point.
It is a circuit that limits the output of 8 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 8, 2
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs of 5 and 28 is activated. When the maximum amplitude value identifying circuit 7 or the amplitude value B identifying circuit 25 is activated, the pattern 1 is set, and when the amplitude value A identifying circuit 8 is activated, the pattern 2 is set.
The case where the amplitude value C identification circuit 28 is activated is defined as pattern 3.

(Pattern 1) When the maximum amplitude value discriminating circuit 7 or the amplitude value B discriminating circuit 25 is activated, the received signal point has the maximum amplitude value or the fourth largest amplitude value, and these are on the straight line 15. Exists. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10 and causes the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is similar to that of the third embodiment.

(Pattern 2) When the amplitude value A discrimination circuit 8 is activated, the received signal point has the second largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Further, the amplitude value limiting circuit 32 is
Regarding the subsequent received signal points, the values of the amplitude value A identifying circuit 8 and the amplitude value C identifying circuit 28 are not transmitted to the adding circuit 10,
Only the values of the maximum amplitude value identification circuit 7 and the amplitude value B identification circuit 25 are restricted to pass. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparison circuit 13 calculates the equation (2) and outputs the phase difference, and the frequency comparison circuit 14 outputs the equation (3). Calculate.

At the subsequent reception signal points, the adder circuit 10 is first
If the value of becomes active, the amplitude value limiting circuit 32
Stops the processing of the adder circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is similar to that of the third embodiment.

(Pattern 3) When the amplitude value C discriminating circuit 28 is activated, the received signal point has the third largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. In addition, the amplitude value limiting circuit 32
Is the amplitude value C identification circuit 2 for the received signal points after the next.
The maximum amplitude value identification circuit 7 is not transmitted to the adder circuit 10
And amplitude value A discrimination circuit 8 and amplitude value B discrimination circuit 25
Restrict passing only the value of. At the subsequent received signal points, while the value of the adder circuit 10 is not active,
The phase comparison circuit 13 calculates the equation (2) and outputs the phase difference, and the frequency comparison circuit 14 calculates the equation (3).

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the amplitude value B identifying circuit 25
Since the value becomes active, the processing of the above pattern 1 or pattern 2 is performed.

As described above, according to the fourth embodiment, immediately after the system is reset, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value, or 3 It has a feature that the frequencies can be compared by receiving the signal point having the second largest amplitude value or the signal point having the fourth largest amplitude value.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 24/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are six times as many occurrences as there are four quarters, so synchronization can be established in one sixth the time.

Furthermore, since the reception point monitoring is continued even after the frequencies have once been synchronized and the frequency phase comparison is finally made with reference to the reception points existing on the straight line 15, the circuit scale is smaller than that of the third embodiment. Although it is large, it has a feature that no phase error occurs.

From the circuit block diagram of FIG. 9, the amplitude value C
When the identification circuit 28 is deleted, the frequency synchronization time becomes longer, but the circuit scale can be reduced.

(Fifth Embodiment) FIG. 11 shows the configuration of a frequency phase comparator 5 according to the fifth embodiment of the present invention. The overall configuration of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Is the same as. Note that the coordinates in FIG. 12 show only the first quadrant of the IQ plane in 256QAM for simplicity, but regarding the second, third, and fourth quadrants,
It is rotated around the origin O. Further, in FIG. 11, parts that are the same as those in FIG.

In this embodiment, a minimum amplitude discriminating circuit 33 and an amplitude value D discriminating circuit 34 are provided as the amplitude value discriminating circuit.
The minimum amplitude discriminating circuit 33 discriminates whether or not the received signal point is a signal point having the minimum amplitude value, and the amplitude value D discriminating circuit 34 judges that the received signal point is the signal point having the third smallest amplitude value. Identify whether there is. If the received signal point has the minimum amplitude value or the third smallest amplitude value, the fact is notified to the adder circuit 10.

As shown in FIG. 12, the signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. Further, the amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38.

As described above, according to the second embodiment, the frequencies can be compared by resetting the system and then receiving the signal point having the minimum amplitude value or the signal point having the third smallest amplitude value first. It has the feature.

Further, if the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 8/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are twice as many occurrences as there are four times the probabilities, so that synchronization can be established in half the time.

Further, since the receiving point on the straight line 15 is used, there is a feature that no phase error occurs.

(Embodiment 6) FIG. 13 shows the configuration of a frequency phase comparator 5 according to a sixth embodiment of the present invention. The overall configuration of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Is the same as. Note that the coordinates in FIG. 14 show only the first quadrant of the IQ plane in 256QAM for simplicity, but regarding the second, third, and fourth quadrants,
It is rotated around the origin O. In FIG. 13, the same parts as those in FIG. 11 are designated by the same reference numerals, and the duplicated description will be omitted.

In this embodiment, the minimum amplitude identifying circuit 33, the amplitude value D identifying circuit 34, and the amplitude value E are used as the amplitude value identifying circuits.
An identification circuit 39 is provided. The minimum amplitude discriminating circuit 33 discriminates whether the received signal point is a signal point having the minimum amplitude value, and the amplitude value D discriminating circuit 34 discriminates whether the received signal point is the signal point having the third smallest amplitude value. To identify if
The amplitude value E discrimination circuit 39 discriminates whether or not the received signal point is the signal point having the fifth smallest amplitude value. If it is determined that the signal points have the corresponding amplitude values, the fact is notified to the adding circuit 10.

As shown in FIG. 14, the signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38. The signal point having the amplitude value E, that is, the fifth smallest amplitude value is the symbol point 4
It has an amplitude value corresponding to 0 and 41 and corresponding to the radius of the arc 42.

As described above, according to the sixth embodiment, after resetting the system, the signal point having the minimum amplitude value first, the signal point having the third smallest amplitude value, or the fifth smallest amplitude value. The feature is that the frequencies can be compared when a signal point having a value is received.

When frequency comparison is started at the receiving point having the fifth smallest amplitude value, a phase error of ± 14 ° may occur as shown in FIG. 14, but the phase shift of the phase comparison circuit 13 is large. This can be corrected by feeding back the length Δθ to the detector 2 in FIG.

Further, if the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 16/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are four times as many occurrences as there are four quarters, so synchronization can be established in a quarter of the time.

(Embodiment 7) FIG. 15 shows the configuration of a frequency phase comparator 5 according to the seventh embodiment of the present invention. The overall configuration of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Is the same as. Note that the coordinates in FIG. 16 show only the first quadrant of the IQ plane in 256QAM for simplification, but regarding the second, third, and fourth quadrants,
It is rotated around the origin O. Further, in FIG. 15, the same parts as those in FIG. 13 are designated by the same reference numerals, and the overlapping description will be omitted.

In this embodiment, the amplitude value limiting circuit 3 is shown in FIG.
2 is added. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 33, 34, 39 according to the position of the received signal point.
Is a circuit that limits the transmission of the output of 1 to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the amplitude value identification circuits 33, 34,
Depending on which of the 39 outputs was activated,
The operation of the amplitude value limiting circuit 32 and the subsequent processing are different. Minimum amplitude value identification circuit 33 or amplitude value D identification circuit 34
Is set to be pattern 1 and the amplitude value E identification circuit 39 is set to be pattern 2

(Pattern 1) When the value of the minimum amplitude value discriminating circuit 33 or the amplitude value D discriminating circuit 34 becomes active, the reception signal point has the minimum amplitude value or the third smallest amplitude value, and these are the straight line 15 Exists on. The amplitude value limiting circuit 32 stops the processing of the adding circuit 10, and the phase comparing circuit 13 calculates the equation (1) and outputs the phase difference. The subsequent operation is similar to that of the sixth embodiment.

(Pattern 2) When the value of the amplitude value E discrimination circuit 39 becomes active, the received signal point has the fifth smallest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the value of the amplitude value E identification circuit 39 to the adder circuit 10 with respect to the subsequent received signal points, and limits only the values of the minimum amplitude value identification circuit 33 and the amplitude value D identification circuit 34 to pass through. . At the subsequent reception signal points, the adder circuit 10
While the value of is not active, the phase comparator 13 outputs the phase shift in the calculation of the equation (2), and the frequency comparator circuit 14
Calculates the equation (3). When the value of the adding circuit 10 first becomes active at the subsequent reception signal points, the amplitude value limiting circuit 32 stops the processing of the adding circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14
The frequency shift is calculated from this value. The subsequent operation is similar to that of the sixth embodiment.

As described above, according to the seventh embodiment, after the system is reset, the signal point having the minimum amplitude value first, the signal point having the third smallest amplitude value, or the fifth smallest amplitude value is obtained. The feature is that the frequencies can be compared when a signal point having a value is received.

If the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 16/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are four times as many occurrences as there are four quarters, so synchronization can be established in a quarter of the time.

Furthermore, since the reception point monitoring is continued even after the frequencies are once synchronized and the frequency phase comparison is finally performed with reference to the reception points existing on the straight line 15, the circuit scale is larger than that of the sixth embodiment. However, it has the feature that no phase error occurs.

(Embodiment 8) FIG. 17 shows the configuration of a frequency phase comparator 5 according to the eighth embodiment of the present invention. The overall configuration of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Is the same as. Note that the coordinates in FIG. 18 show only the first quadrant of the IQ plane in 256QAM for simplification, but regarding the second, third, and fourth quadrants,
It is rotated around the origin O. In FIG. 17, parts that are the same as those in FIG. 2 are given the same reference numerals and redundant description will be omitted.

In this embodiment, the minimum amplitude value identification circuit 33 is provided in parallel with the maximum amplitude value identification circuit 7. The minimum amplitude value identification circuit 33 identifies whether the received signal point is a signal point having the minimum amplitude value. If the signal point having the maximum amplitude value or the minimum amplitude value is identified, the fact is notified to the adding circuit 10.

As shown in FIG. 18, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37.

As described above, according to the eighth embodiment, if the signal point having the minimum amplitude value is received in addition to the signal point having the maximum amplitude value after resetting the system,
It has the feature of frequency comparison.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 8/256. Therefore, 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are twice as many occurrences as there are four times the probabilities, so that synchronization can be established in half the time.

Further, since only the reception points on the straight line 15 are used for identification, there is a feature that no phase error occurs.

(Ninth Embodiment) FIG. 19 shows the structure of a frequency phase comparator 5 according to the ninth embodiment of the present invention. The overall structure of a QAM receiver including the frequency phase comparator 5 is shown in FIG. Is the same as. Note that the coordinates in FIG. 20 show only the first quadrant of the IQ plane in 256QAM for simplification, but regarding the second, third, and fourth quadrants,
It is rotated around the origin O. Further, in FIG. 19, the same parts as those in FIG. 2 are designated by the same reference numerals, and the duplicated description will be omitted.

In this embodiment, the minimum amplitude value identification circuit 33 and the amplitude value A identification circuit 8 are provided in parallel with the maximum amplitude value identification circuit 7. The minimum amplitude value identifying circuit 33 identifies whether the signal point has the minimum amplitude value, and the amplitude value A identifying circuit 8 identifies whether the signal point has the second largest amplitude value. . If it is identified as a reception point having these corresponding amplitude values, the fact is notified to the adder circuit 10.

As shown in FIG. 20, the signal point having the maximum amplitude value corresponds to the symbol point 16 and the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20.

As described above, according to the ninth embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the minimum amplitude value, or the second largest amplitude value. The feature is that frequency comparison can be performed by receiving a signal point having

When frequency comparison is started at the receiving point having the second largest amplitude value, a phase error of ± 4.1 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude Δθ of the signal to the wave detector 2 of FIG.

Further, if the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 16/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are four times as many occurrences as there are four quarters, so synchronization can be established in a quarter of the time.

(Embodiment 10) FIG. 21 shows the first embodiment of the present invention.
1 shows the configuration of the frequency phase comparator 5 in the embodiment of No. 0, and the overall configuration of the QAM receiving apparatus including the frequency phase comparator 5 is the same as that in FIG. Note that the coordinates in FIG. 22 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 1, parts that are the same as those in FIG. 2 are given the same reference numerals and redundant description will be omitted.

In this embodiment, the minimum amplitude value identification circuit 33, the amplitude value A identification circuit 8, and the maximum amplitude value identification circuit 7 are provided in parallel.
An amplitude value B identification circuit 25 is provided. Minimum amplitude value identification circuit 3
3 identifies whether or not the signal point has the minimum amplitude value. The amplitude value A identifying circuit 8 identifies whether or not the signal point has the second largest amplitude value. The amplitude value B identifying circuit 25 identifies whether or not the signal point has the fourth largest amplitude value. If it is determined that the reception point has the corresponding amplitude value, the fact is notified to the addition circuit 10.

As shown in FIG. 22, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The amplitude value B, that is, the signal point having the fourth largest amplitude value corresponds to the symbol point 26 and has the amplitude value corresponding to the radius of the arc 27.

As described above, according to the tenth embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the minimum amplitude value or the second largest amplitude value. The frequency comparison can be performed by receiving a signal point having, a signal point having a fourth largest amplitude value, or a signal point having a minimum amplitude value.

When frequency comparison is started at the receiving point having the second largest amplitude value, a phase error of ± 4.1 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude Δθ of the signal to the wave detector 2 of FIG.

If the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 20/256. Therefore, 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are five times as many occurrences as there are four quarters, so synchronization can be established in one fifth of the time.

(Embodiment 11) FIG. 23 shows the first embodiment of the present invention.
1 shows the configuration of a frequency phase comparator 5 in the first embodiment, and the overall configuration of a QAM receiving apparatus including the frequency phase comparator 5 is the same as FIG. Note that the coordinates in FIG. 24 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. Also in FIG.
2 that are the same as those in FIG. 2 are assigned the same reference numerals and overlapping explanations will be omitted.

In this embodiment, the minimum amplitude value identification circuit 33, the amplitude value A identification circuit 8, and the maximum amplitude value identification circuit 7 are provided in parallel.
An amplitude value B identifying circuit 25 and an amplitude value C identifying circuit 28 are provided. The minimum amplitude value identification circuit 33 identifies whether or not the signal point has the minimum amplitude value. Amplitude value A discrimination circuit 8
Identifies whether the signal point has the second largest amplitude value. The amplitude value B identifying circuit 25 identifies whether or not the signal point has the fourth largest amplitude value. The amplitude value C identifying circuit 28 identifies whether or not the signal point has the third largest amplitude value. If it is determined that the reception point has the corresponding amplitude value, the fact is notified to the addition circuit 10.

As shown in FIG. 24, the signal point having the maximum amplitude value corresponds to the symbol point 16 and the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The amplitude value B, that is, the signal point having the fourth largest amplitude value corresponds to the symbol point 26 and has the amplitude value corresponding to the radius of the arc 27. The signal point having the amplitude value C, that is, the third largest amplitude value is the symbol point 2
It has amplitude values corresponding to 9, 30 and the radius of the arc 31.

As described above, according to the eleventh embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the third signal point having the largest amplitude value. The frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a fourth largest amplitude value, or a signal point having a minimum amplitude value.

When frequency comparison is started at the receiving point having the third largest amplitude value, a phase error of ± 8.7 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude Δθ of the signal to the wave detector 2 of FIG.

If the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 28/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are seven times as many occurrences as there are four quarters, so synchronization can be established in one seventh the time.

(Embodiment 12) FIG. 25 shows the first embodiment of the present invention.
2 shows the configuration of the frequency phase comparator 5 in the second embodiment, and the overall configuration of the QAM receiver including the frequency phase comparator 5 is the same as FIG. Note that the coordinates in FIG. 26 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 5, parts that are the same as those in FIG. 23 are assigned the same reference numerals and explanations thereof are omitted.

FIG. 23 shows the amplitude value limiting circuit 3 according to the present embodiment.
2 is added. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 8, 25, 2 depending on the position of the received signal point.
This is a circuit that restricts the outputs of 8 and 33 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 8, 2
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs of 5, 28 and 33 is activated. Pattern 1 when the maximum amplitude value identification circuit 7 or the amplitude value B identification circuit 25 or minimum amplitude value identification circuit 33 becomes active, pattern 2 when the amplitude value A identification circuit 8 becomes active, and amplitude value C identification Circuit 2
Pattern 8 is when 8 is activated.

(Pattern 1) Maximum amplitude value identifying circuit 7 or amplitude value B identifying circuit 25 or minimum amplitude value identifying circuit 33
When the value of is activated, the received signal point has the maximum amplitude value or the fourth largest amplitude value or the minimum amplitude value, which are on the straight line 15. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10 and causes the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is similar to that of the eleventh embodiment.

(Pattern 2) When the value of the amplitude value A discrimination circuit 8 becomes active, the received signal point has the second largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. In addition, the amplitude value limiting circuit 32
Is the amplitude value A discrimination circuit 8 for the received signal points after the next.
And the value of the amplitude value C identification circuit 28 is not transmitted to the addition circuit 10, and the maximum amplitude value identification circuit 7 and the amplitude value B identification circuit 25
And the value of the minimum amplitude value identification circuit 33 is limited to pass. At the subsequent received signal points, the phase comparator 13 outputs the phase shift in the calculation of the equation (2) while the value of the adder circuit 10 is not active, and the frequency comparator circuit 14
Calculates the equation (3).

At the subsequent reception signal points, the adder circuit 10 is first
If the value of becomes active, the amplitude value limiting circuit 32
Stops the processing of the adder circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is similar to that of the eleventh embodiment.

(Pattern 3) When the value of the amplitude value C discrimination circuit 28 becomes active, the received signal point has the third largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the value of the amplitude value C identification circuit 28 to the addition circuit 10 for the subsequent received signal points, and the maximum amplitude value identification circuit 7, the amplitude value A identification circuit 8 and the amplitude value B identification circuit 2
5 and the value of the minimum amplitude value identification circuit 33 are restricted to pass. At the subsequent reception signal points, the adder circuit 10
While the value of is not active, the phase comparator 13 outputs the phase shift in the calculation of the equation (2), and the frequency comparator circuit 14
Calculates the equation (3).

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the amplitude value B identifying circuit 25
Alternatively, since the value of the minimum amplitude value identification circuit 33 has become active, the processing of pattern 1 or pattern 2 is performed.

As described above, according to the twelfth embodiment, after the system is reset, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the third It has a feature that frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a fourth largest amplitude value, or a signal point having a minimum amplitude value.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 28/256. Therefore, 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are seven times as many occurrences as there are four quarters, so synchronization can be established in one seventh the time.

Furthermore, since the reception point monitoring is continued even after the frequencies are once synchronized, and the frequency phase comparison is finally performed with the reception points existing on the straight line 15 as a reference, the circuit scale is larger than that of the eleventh embodiment. However, it has the feature that no phase error occurs.

When the amplitude value C identification circuit 28 is deleted from the circuit block diagram of FIG. 25, the frequency synchronization time becomes longer, but the circuit scale can be reduced.

(Embodiment 13) FIG. 27 shows the first embodiment of the present invention.
3 shows the configuration of a frequency phase comparator 5 in the third embodiment, and the overall configuration of a QAM receiver including the frequency phase comparator 5 is the same as that in FIG. Note that the coordinates in FIG. 28 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 7, the same parts as those in FIG.

In this embodiment, a minimum amplitude value identification circuit 33 and an amplitude value D identification circuit 34 are provided in parallel with the maximum amplitude value identification circuit 7. The minimum amplitude value identification circuit 33 identifies whether the received signal point is a signal point having the minimum amplitude value. The amplitude value D identifying circuit 34 identifies whether the received signal point is the signal point having the third smallest amplitude value.
If it is identified that the signal point has the maximum amplitude value, the minimum amplitude value, or the third smallest amplitude value, the fact is notified to the adder circuit 10.

As shown in FIG. 28, the signal point having the maximum amplitude value corresponds to the symbol point 16 and the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38.

As described above, according to the thirteenth embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the minimum amplitude value or the third smallest amplitude value. The feature is that the frequency can be compared by receiving the signal point having

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 12/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are three times as many occurrences as there are four-fourths of probability, so synchronization can be established in one-third of the time.

Further, since only the reception points on the straight line 15 are used for identification, there is a feature that no phase error occurs.

(Embodiment 14) FIG. 29 shows the first embodiment of the present invention.
4 shows the configuration of a frequency phase comparator 5 in the fourth embodiment, and the overall configuration of a QAM receiving apparatus including the frequency phase comparator 5 is the same as FIG. Note that the coordinates in FIG. 30 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 9, the same parts as those in FIG.

In this embodiment, the maximum amplitude value identification circuit 7 and the amplitude value A identification circuit 8, the minimum amplitude value identification circuit 33, are arranged in parallel.
An amplitude value D identification circuit 34 is provided. Amplitude value A discrimination circuit 8
Identifies whether the signal point has the second largest amplitude value. The minimum amplitude value identification circuit 33 identifies whether or not the signal point has the minimum amplitude value. The amplitude value D identifying circuit 34 identifies whether or not the signal point has the third smallest amplitude value. If the reception point is identified as having these corresponding amplitude values, the addition circuit 1
Tell 0.

As shown in FIG. 30, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38.

As described above, according to the fourteenth embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the minimum amplitude value It is characterized in that frequency comparison can be performed by receiving a signal point having a value of or a signal point having a third smallest amplitude value.

When frequency comparison is started at the receiving point having the second largest amplitude value, a phase error of ± 4.1 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude Δθ of the signal to the wave detector 2 of FIG.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 20/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are five times as many occurrences as there are four quarters, so synchronization can be established in one fifth of the time.

(Embodiment 15) FIG. 31 shows the first embodiment of the present invention.
5 shows the configuration of a frequency / phase comparator 5 in the fifth embodiment, and the overall configuration of a QAM receiver including the frequency / phase comparator 5 is the same as in FIG. Note that the coordinates in FIG. 32 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 1, parts that are the same as those in FIG. 2 are given the same reference numerals and redundant description will be omitted.

In this embodiment, an amplitude value A identifying circuit 8, an amplitude value B identifying circuit 25, a minimum amplitude value identifying circuit 33, and an amplitude value D identifying circuit 34 are provided in parallel with the maximum amplitude value identifying circuit 7. The minimum amplitude value identification circuit 33 identifies whether or not the signal point has the minimum amplitude value. Amplitude value A discrimination circuit 8
Identifies whether the signal point has the second largest amplitude value. The amplitude value B identifying circuit 25 identifies whether or not the signal point has the fourth largest amplitude value. The amplitude value D identifying circuit 34 identifies whether or not the signal point has the third smallest amplitude value. If it is determined that the reception point has the corresponding amplitude value, the fact is notified to the addition circuit 10.

As shown in FIG. 32, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The amplitude value B, that is, the signal point having the fourth largest amplitude value corresponds to the symbol point 26 and has the amplitude value corresponding to the radius of the arc 27. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38.

As described above, according to the fifteenth embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value, or the fourth signal point having the largest amplitude value. The frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a minimum amplitude value, or a signal point having a third smallest amplitude value.

When frequency comparison is started at the receiving point having the second largest amplitude value, a phase error of ± 4.1 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude Δθ of the signal to the wave detector 2 of FIG.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 24/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are six times as many occurrences as there are four quarters, so synchronization can be established in one sixth the time.

(Embodiment 16) FIG. 33 shows the first embodiment of the present invention.
6 shows the configuration of a frequency phase comparator 5 in the sixth embodiment, and the overall configuration of a QAM receiver including the frequency phase comparator 5 is the same as that in FIG. The coordinates in FIG. 34 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 3, the same parts as those in FIG.

In this embodiment, the maximum amplitude value identification circuit 7 and the amplitude value A identification circuit 8, the amplitude value B identification circuit 25, the amplitude value C identification circuit 28, the minimum amplitude value identification circuit 33, and the amplitude value D identification circuit are arranged in parallel. 34 is provided. The amplitude value A identifying circuit 8 identifies whether or not the signal point has the second largest amplitude value. The amplitude value B identifying circuit 25 identifies whether or not the signal point has the fourth largest amplitude value. The amplitude value C identifying circuit 28 identifies whether or not the signal point has the third largest amplitude value. The minimum amplitude value identification circuit 33
Whether or not the signal point has the minimum amplitude value is identified.
The amplitude value D identifying circuit 34 identifies whether or not the signal point has the third smallest amplitude value. If it is determined that the reception point has the corresponding amplitude value, the fact is notified to the addition circuit 10.

As shown in FIG. 34, the signal point having the maximum amplitude value corresponds to the symbol point 16 and the amplitude value corresponding to the radius of the arc 19. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The amplitude value B, that is, the signal point having the fourth largest amplitude value is the symbol point 26.
And has an amplitude value corresponding to the radius of the arc 27. The amplitude value C, that is, the signal point having the third largest amplitude value corresponds to the symbol points 29 and 30, and has the amplitude value corresponding to the radius of the arc 31. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38.

As described above, according to the sixteenth embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the second largest amplitude value or the third signal point It is said that frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a fourth largest amplitude value, a signal point having a smallest amplitude value, or a signal point having a third smallest amplitude value. It has characteristics.

When frequency comparison is started at the receiving point having the third largest amplitude value, a phase error of ± 8.7 ° may occur as shown in FIG. This can be corrected by feeding back the magnitude Δθ of the signal to the wave detector 2 of FIG.

If the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 32/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are eight times as many occurrences as there are four quarters, so synchronization can be established in one eighth of the time.

(Embodiment 17) FIG. 35 shows the first embodiment of the present invention.
7 shows the configuration of a frequency phase comparator 5 in the seventh embodiment, and the overall configuration of a QAM receiver including the frequency phase comparator 5 is the same as that in FIG. Note that the coordinates in FIG. 36 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 5, parts that are the same as those in FIG. 33 are assigned the same reference numerals and overlapping description will be omitted.

In this embodiment, the amplitude value limiting circuit 3 shown in FIG.
2 is added. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 8, 25, 2 depending on the position of the received signal point.
This is a circuit that restricts the outputs of 8, 33, and 34 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and directly transmits the information of each amplitude value identifying circuit to the adding circuit 10. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 8, 2
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs 5, 28, 33 and 34 is activated. When the maximum amplitude value identification circuit 7, the amplitude value B identification circuit 25, the minimum amplitude value identification circuit 33, or the amplitude value D identification circuit 34 is activated, the pattern 1 is set, and when the amplitude value A identification circuit 8 is activated, the pattern 1 is set. Pattern 2 and the case where the amplitude value C identification circuit 28 is activated are referred to as pattern 3.

(Pattern 1) Maximum amplitude value identification circuit 7 or amplitude value B identification circuit 25 or minimum amplitude value identification circuit 33
Alternatively, when the value of the amplitude value D identification circuit 34 becomes active, the received signal point has the maximum amplitude value or the fourth largest amplitude value or the minimum amplitude value or the third smallest amplitude value, which are on the straight line 15. Exists. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10 and causes the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is the same as in the sixteenth embodiment.

(Pattern 2) When the value of the amplitude value A discrimination circuit 8 becomes active, the received signal point has the second largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. In addition, the amplitude value limiting circuit 32
Is the amplitude value A discrimination circuit 8 for the received signal points after the next.
And the value of the amplitude value C identification circuit 28 is not transmitted to the addition circuit 10, and the maximum amplitude value identification circuit 7 and the amplitude value B identification circuit 25
And the values of the minimum amplitude value identification circuit 33 and the amplitude value D identification circuit 34 are restricted to pass. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparator 13 outputs the phase shift in the calculation of the formula (2), and the frequency comparison circuit 14 calculates the formula (3). I do.

At the subsequent reception signal points, the adder circuit 10 is first
If the value of becomes active, the amplitude value limiting circuit 32
Stops the processing of the adder circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is the same as in the sixteenth embodiment.

(Pattern 3) When the value of the amplitude value C identification circuit 28 becomes active, the received signal point has the third largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the value of the amplitude value C identification circuit 28 to the addition circuit 10 for the subsequent received signal points, and the maximum amplitude value identification circuit 7, the amplitude value A identification circuit 8 and the amplitude value B identification circuit 2
5 and the minimum amplitude value identification circuit 33 and the amplitude value D identification circuit 34 are limited to pass. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparator 13 outputs the phase shift in the calculation of the formula (2), and the frequency comparison circuit 14 calculates the formula (3). I do.

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the amplitude value B identifying circuit 25
Alternatively, since the value of the minimum amplitude value identification circuit 33 or the amplitude value D identification circuit 34 becomes active, the above pattern 1
Alternatively, the processing of pattern 2 is performed.

As described above, according to the seventeenth embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the third A feature that frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a fourth largest amplitude value, a signal point having a smallest amplitude value, or a signal point having a third smallest amplitude value. Have.

If the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 32/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are eight times as many occurrences as there are four quarters, so synchronization can be established in one eighth of the time.

Further, even after the frequencies are synchronized once, the reception point monitoring is continued, and finally the frequency phase comparison is performed with reference to the reception points existing on the straight line 15. Therefore, the circuit scale is larger than that of the sixteenth embodiment. However, it has the feature that no phase error occurs.

When the amplitude value C identification circuit 28 is deleted from the circuit block diagram of FIG. 35, the frequency synchronization time becomes longer, but the circuit scale can be reduced.

(Embodiment 18) FIG. 37 shows the first embodiment of the present invention.
8 shows the configuration of the frequency phase comparator 5 in the eighth embodiment, and the overall configuration of the QAM receiver including the frequency phase comparator 5 is the same as FIG. Note that the coordinates in FIG. 38 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 7, the same parts as those in FIG.

In this embodiment, a minimum amplitude value identification circuit 33, an amplitude value D identification circuit 34, and an amplitude value E identification circuit 39 are provided in parallel with the maximum amplitude value identification circuit 7. The minimum amplitude value identification circuit 33 identifies whether or not the received signal point is a signal point having the minimum amplitude value. The amplitude value D identification circuit 34
It is identified whether or not the received signal point is the signal point having the third smallest amplitude value. The amplitude value E discrimination circuit 39 discriminates whether or not the received signal point is the signal point having the fifth smallest amplitude value. If it is identified as the maximum amplitude value, the minimum amplitude value, the signal point having the third smallest amplitude value, or the signal point having the fifth smallest amplitude value, the fact is notified to the adding circuit 10.

As shown in FIG. 38, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38. The signal point having the fifth smallest amplitude value corresponds to the symbol points 40 and 41, and has the amplitude value corresponding to the radius of the arc 42.

As described above, according to the eighteenth embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the minimum amplitude value, or the third smallest amplitude value. It has a feature that frequency comparison can be performed by receiving a signal point having a signal having a value of 5 or a signal point having a fifth smallest amplitude value.

When frequency comparison is started at the receiving point having the fifth smallest amplitude value, a phase error of ± 14 ° may occur as shown in FIG. 38, but the phase shift of the phase comparison circuit 13 is large. This can be corrected by feeding back the length Δθ to the detector 2 in FIG.

If the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 20/256. Therefore, 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are five times as many occurrences as there are four quarters, so synchronization can be established in one fifth of the time.

(Embodiment 19) FIG. 39 shows the first embodiment of the present invention.
9 shows the configuration of a frequency phase comparator 5 in the ninth embodiment, and the overall configuration of a QAM receiver including the frequency phase comparator 5 is the same as that in FIG. Note that the coordinates in FIG. 40 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 9, the same parts as those in FIG.

In this embodiment, the maximum amplitude value identification circuit 7 and the amplitude value A identification circuit 8, the minimum amplitude value identification circuit 33, are arranged in parallel.
An amplitude value D identifying circuit 34 and an amplitude value E identifying circuit 39 are provided. The amplitude value A identifying circuit 8 identifies whether or not the signal point has the second largest amplitude value. The minimum amplitude value identification circuit 33 identifies whether or not the signal point has the minimum amplitude value. The amplitude value D identifying circuit 34 identifies whether or not the signal point has the third smallest amplitude value. The amplitude value E identifying circuit 39 identifies whether or not the signal point has the fifth smallest amplitude value. If it is identified as a reception point having these corresponding amplitude values, the fact is notified to the adder circuit 10.

As shown in FIG. 40, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38. The amplitude value E, that is, the signal point having the fifth smallest amplitude value is the symbol point 40,
41 has an amplitude value corresponding to the radius of the arc 42.

As described above, according to the nineteenth embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the second largest amplitude value or the minimum amplitude value. The frequency comparison can be performed by receiving a signal point having a, a signal point having a third smallest amplitude value, or a signal point having a fifth smallest amplitude value.

When frequency comparison is started at the receiving point having the fifth smallest amplitude value, a phase error of ± 14 ° may occur as shown in FIG. 40, but the phase shift of the phase comparison circuit 13 is large. This can be corrected by feeding back the length Δθ to the detector 2 in FIG.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 28/256. Therefore, 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are seven times as many occurrences as there are four quarters, so synchronization can be established in one seventh the time.

(Embodiment 20) FIG. 41 shows a second embodiment of the present invention.
1 shows the configuration of the frequency phase comparator 5 in the embodiment of No. 0, and the overall configuration of the QAM receiving apparatus including the frequency phase comparator 5 is the same as that in FIG. Note that the coordinates in FIG. 42 are the first on the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 1, the same parts as in FIG.

In this embodiment, the maximum amplitude value identifying circuit 7 and the amplitude value A identifying circuit 8, the amplitude value B identifying circuit 25, the minimum amplitude value identifying circuit 33, the amplitude value D identifying circuit 34, and the amplitude value E identifying circuit are arranged in parallel. 39 is provided. The minimum amplitude value identification circuit 33
Whether or not the signal point has the minimum amplitude value is identified.
The amplitude value A identifying circuit 8 identifies whether or not the signal point has the second largest amplitude value. Amplitude value B identification circuit 2
5 identifies whether or not the signal point has the fourth largest amplitude value. The amplitude value D identifying circuit 34 identifies whether or not the signal point has the third smallest amplitude value.
The amplitude value E identifying circuit 39 identifies whether or not the signal point has the fifth smallest amplitude value. If it is determined that the reception point has the corresponding amplitude value, the fact is notified to the addition circuit 10.

As shown in FIG. 42, the signal point having the maximum amplitude value corresponds to the symbol point 16 and has the amplitude value corresponding to the radius of the arc 19. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The amplitude value B, that is, the signal point having the fourth largest amplitude value corresponds to the symbol point 26 and has the amplitude value corresponding to the radius of the arc 27. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38. The signal point having the amplitude value E, that is, the fifth smallest amplitude value corresponds to the symbol points 40 and 41, and has the amplitude value corresponding to the radius of the arc 42.

As described above, according to the twentieth embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the fourth It is said that frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a minimum amplitude value, a signal point having a third smallest amplitude value, or a signal point having a fifth smallest amplitude value. It has characteristics.

When frequency comparison is started at the reception point having the fifth smallest amplitude value, a phase error of ± 14 ° may occur as shown in FIG. 42, but the phase shift of the phase comparison circuit 13 is large. This can be corrected by feeding back the length Δθ to the detector 2 in FIG.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 32/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are eight times as many occurrences as there are four quarters, so synchronization can be established in one eighth of the time.

(Embodiment 21) FIG. 43 shows a second embodiment of the present invention.
1 shows the configuration of a frequency phase comparator 5 in the first embodiment, and the overall configuration of a QAM receiving apparatus including the frequency phase comparator 5 is the same as FIG. Note that the coordinates in FIG. 44 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 3, the same parts as in FIG.

In this embodiment, the maximum amplitude value identification circuit 7 and the amplitude value A identification circuit 8, the amplitude value B identification circuit 25, the amplitude value C identification circuit 28, the minimum amplitude value identification circuit 33, and the amplitude value D identification circuit are arranged in parallel. 34, an amplitude value E identification circuit 39 is provided. The amplitude value A identifying circuit 8 identifies whether or not the signal point has the second largest amplitude value. Amplitude value B identification circuit 25
Identifies whether the signal point has the fourth largest amplitude value. The amplitude value C identifying circuit 28 identifies whether or not the signal point has the third largest amplitude value. The minimum amplitude value identification circuit 33 identifies whether or not the signal point has the minimum amplitude value. The amplitude value D identification circuit 34 is 3
Whether or not the signal point has the second smallest amplitude value is identified. The amplitude value E identifying circuit 39 identifies whether or not the signal point has the fifth smallest amplitude value. If it is determined that the reception point has the corresponding amplitude value, the fact is notified to the addition circuit 10.

As shown in FIG. 44, the signal point having the maximum amplitude value corresponds to the symbol point 16 and the amplitude value corresponding to the radius of the arc 19. The amplitude value A, that is, the signal point having the second largest amplitude value corresponds to the symbol points 17 and 18, and has the amplitude value corresponding to the radius of the arc 20. The amplitude value B, that is, the signal point having the fourth largest amplitude value is the symbol point 26.
And has an amplitude value corresponding to the radius of the arc 27. The amplitude value C, that is, the signal point having the third largest amplitude value corresponds to the symbol points 29 and 30, and has the amplitude value corresponding to the radius of the arc 31. The signal point having the minimum amplitude value corresponds to the symbol point 35 and has the amplitude value corresponding to the radius of the arc 37. The amplitude value D, that is, the signal point having the third smallest amplitude value corresponds to the symbol point 36 and has the amplitude value corresponding to the radius of the arc 38. The signal point having the amplitude value E, that is, the fifth smallest amplitude value corresponds to the symbol points 40 and 41, and has the amplitude value corresponding to the radius of the arc 42.

As described above, according to the twenty-first embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the third A signal point with a large amplitude value, a signal point with a fourth largest amplitude value, a signal point with a smallest amplitude value, a signal point with a third smallest amplitude value, or a fifth smallest amplitude value If you receive a signal point,
It has the feature that frequency comparison is possible.

When frequency comparison is started at the receiving point having the fifth smallest amplitude value, a phase error of ± 14 ° may occur as shown in FIG. 44, but the phase shift of the phase comparison circuit 13 is large. This can be corrected by feeding back the length Δθ to the detector 2 in FIG.

If the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 40/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are ten times as many occurrences as there are four times the probability, so synchronization can be established in ten times less time.

(Embodiment 22) FIG. 45 shows a second embodiment of the present invention.
3 shows a configuration of a frequency phase comparator 5 in the second embodiment. The overall configuration of the QAM receiver including the frequency / phase comparator 5 is the same as in FIG. Note that the coordinates in FIG. 46 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 5, the same parts as those in FIG. 43 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, an amplitude value limiting circuit 32 is added to FIG. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 8, 25, depending on the position of the received signal point.
It is a circuit that restricts the outputs of 28, 33, 34 and 39 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the processing is stopped by the amplitude value limiting circuit 32.
Is controlled by

Immediately after resetting the system, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 8, 2
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs of 5, 28, 33, 34, 39 is activated. Maximum amplitude value identification circuit 7 or amplitude value B identification circuit 25 or minimum amplitude value identification circuit 33
Alternatively, when the amplitude value D identification circuit 34 is activated, the pattern 1 is set, when the amplitude value A identification circuit 8 is activated, the pattern 2 is set, when the amplitude value C identification circuit 28 is activated, the pattern 3 is set, and the amplitude is set. The case where the value E identification circuit 39 is activated is referred to as pattern 4.

(Pattern 1) Maximum amplitude value identifying circuit 7 or amplitude value B identifying circuit 25 or minimum amplitude value identifying circuit 33
Alternatively, when the value of the amplitude value D identification circuit 34 becomes active, the received signal point has the maximum amplitude value or the fourth largest amplitude value or the minimum amplitude value or the third smallest amplitude value, which are on the straight line 15. Exists. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10, and the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is similar to that of the twenty-first embodiment.

(Pattern 2) When the value of the amplitude value A discrimination circuit 8 becomes active, the received signal point has the second largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. In addition, the amplitude value limiting circuit 32
Is the amplitude value A discrimination circuit 8 for the received signal points after the next.
And amplitude value C identification circuit 28 and amplitude value E identification circuit 3
The value of 9 is not transmitted to the adder circuit 10, and the maximum amplitude value identification circuit 7
And the amplitude value B identification circuit 25, the minimum amplitude value identification circuit 33, and the amplitude value D identification circuit 34 are limited to pass. At the subsequent reception signal points, the adder circuit 10
While the value of is not active, the phase comparator 13 outputs the phase shift in the calculation of the equation (2), and the frequency comparator circuit 14
Calculates the equation (3).

At the subsequent reception signal points, the adder circuit 10 is first
If the value of becomes active, the amplitude value limiting circuit 32
Stops the processing of the adder circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is similar to that of the twenty-first embodiment.

(Pattern 3) When the value of the amplitude value C discriminating circuit 28 becomes active, the received signal point has the third largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the values of the amplitude value C identification circuit 28 and the amplitude value E identification circuit 39 to the adder circuit 10 for the subsequent received signal points, and the maximum amplitude value identification circuit 7, the amplitude value A identification circuit 8 and the amplitude value. Only the values of the B discriminating circuit 25, the minimum amplitude value discriminating circuit 33 and the amplitude value D discriminating circuit 34 are restricted to pass. At the received signal points after the next, the adder circuit 1
While the value of 0 is not active, the phase comparator 13
The phase shift is output by the calculation of the equation (2), and the frequency comparison circuit 1
4 calculates the formula (3).

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the amplitude value B identifying circuit 25
Alternatively, since the value of the minimum amplitude value identification circuit 33 or the amplitude value D identification circuit 34 becomes active, the above pattern 1
Alternatively, the processing of pattern 2 is performed.

(Pattern 4) When the value of the amplitude value E discrimination circuit 39 becomes active, the received signal point has the fifth smallest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the value of the amplitude value E identification circuit 39 to the adder circuit 10 for the subsequent received signal points, and outputs only the values of the other amplitude value limiting circuits 7, 8, 25, 28, 33, 34. Restrict it to pass. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparator 1
3 outputs the phase shift in the calculation of the formula (2), and the frequency comparison circuit 14 calculates the formula (3).

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the amplitude value B identifying circuit 25
Alternatively, the amplitude value C identification circuit 28 or the minimum amplitude value identification circuit 3
3 or the value of the amplitude value D discriminating circuit 34 becomes active, the above-described processing of pattern 1, pattern 2 or pattern 3 is performed.

As described above, according to the twenty-second embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value, or the third signal point having the largest amplitude value. A signal point with a large amplitude value, a signal point with a fourth largest amplitude value, a signal point with a smallest amplitude value, a signal point with a third smallest amplitude value, or a fifth smallest amplitude value If you receive a signal point,
It has the feature of frequency comparison.

Further, if the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 40/256, so that 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are ten times as many occurrences as there are four times the probability, so synchronization can be established in ten times less time.

Furthermore, since the reception point monitoring is continued even after the frequencies have once been synchronized and the frequency phase comparison is finally made with reference to the reception points existing on the straight line 15, the circuit scale is larger than that of the twenty-first embodiment. However, it has the feature that no phase error occurs.

When the amplitude value E identification circuit 39 is deleted from the circuit block diagram of FIG. 45, the frequency synchronization time becomes longer, but the circuit scale can be reduced.

(Embodiment 23) FIG. 47 shows a second embodiment of the present invention.
3 shows the configuration of a frequency phase comparator 5 in the third embodiment, and the overall configuration of a QAM receiver including the frequency phase comparator 5 is the same as that in FIG. Note that the coordinates in FIG. 48 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 7, the same parts as those in FIG. 37 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, an amplitude value limiting circuit 32 is added to FIG. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 33, 3 depending on the position of the received signal point.
This is a circuit that restricts the outputs of 4, 39 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 33, 3
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs 4 and 39 is activated. The case where the maximum amplitude value identifying circuit 7 or the minimum amplitude value identifying circuit 33 or the amplitude value D identifying circuit 34 is activated is referred to as pattern 1, and the case where the amplitude value E identifying circuit 39 is activated is referred to as pattern 2.

(Pattern 1) Maximum amplitude value identification circuit 7 or minimum amplitude value identification circuit 33 or amplitude value D identification circuit 34
When the value of is activated, the received signal point has the maximum amplitude value or the minimum amplitude value or the third smallest amplitude value, which are on the straight line 15. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10 and causes the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is similar to that of the eighteenth embodiment.

(Pattern 2) When the value of the amplitude value E discrimination circuit 39 becomes active, the received signal point has the fifth smallest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the value of the amplitude value E identification circuit 39 to the adder circuit 10 for the subsequent received signal points, but only the values of the maximum amplitude value identification circuit 7, the minimum amplitude value identification circuit 33, and the amplitude value D identification circuit 34. Restricted to pass through. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparator 13 outputs the phase shift in the calculation of the formula (2), and the frequency comparison circuit 14 calculates the formula (3). I do.

At the subsequent reception signal points, the adder circuit 10 is first
If the value of becomes active, the amplitude value limiting circuit 32
Stops the processing of the adder circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is similar to that of the eighteenth embodiment.

As described above, according to the twenty-third embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the minimum amplitude value or the third smallest amplitude value. It has a feature that frequency comparison can be performed by receiving a signal point having a signal having a value of 5 or a signal point having a fifth smallest amplitude value.

If the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 20/256. Therefore, 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are five times as many occurrences as there are four quarters, so synchronization can be established in one fifth of the time.

Furthermore, since the reception point monitoring is continued even after the frequencies have once been synchronized and the frequency phase comparison is finally made with reference to the reception points existing on the straight line 15, the circuit scale is larger than that of the eighteenth embodiment. However, it has the feature that no phase error occurs.

(Embodiment 24) FIG. 49 shows a second embodiment of the present invention.
4 shows the configuration of a frequency phase comparator 5 in the fourth embodiment, and the overall configuration of a QAM receiving apparatus including the frequency phase comparator 5 is the same as FIG. Note that the coordinates in FIG. 50 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. FIG.
In FIG. 9, the same parts as those in FIG. 39 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the amplitude value limiting circuit 32 is shown in FIG.
Is added. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 8, 33, 3 depending on the position of the received signal point.
This is a circuit that restricts the outputs of 4, 39 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 8, 3
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs of 3, 34 and 39 is activated. Pattern 1 when the maximum amplitude value identification circuit 7 or minimum amplitude value identification circuit 33 or amplitude value D identification circuit 34 is active, pattern 2 when the amplitude value A identification circuit 8 is active, and amplitude value E identification Circuit 3
When 9 becomes active, it is designated as pattern 3.

(Pattern 1) Maximum amplitude value identification circuit 7 or minimum amplitude value identification circuit 33 or amplitude value D identification circuit 34
When the value of is activated, the received signal point has the maximum amplitude value or the minimum amplitude value or the third smallest amplitude value, which are on the straight line 15. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10 and causes the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is similar to that of the nineteenth embodiment.

(Pattern 2) When the value of the amplitude value A discrimination circuit 8 becomes active, the received signal point has the second largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. In addition, the amplitude value limiting circuit 32
Is the amplitude value A discrimination circuit 8 for the received signal points after the next.
And the value of the amplitude value E identification circuit 39 is not transmitted to the addition circuit 10, and the maximum amplitude value identification circuit 7 and the minimum amplitude value identification circuit 3
3 and the value of the amplitude value D identification circuit 34 are restricted to pass. At the subsequent received signal points, the phase comparator 13 outputs the phase shift in the calculation of the equation (2) while the value of the adder circuit 10 is not active, and the frequency comparator circuit 14
Calculates the equation (3).

At the subsequent reception signal points, the adder circuit 10 is set first.
If the value of becomes active, the amplitude value limiting circuit 32
Stops the processing of the adder circuit 10. Then, the phase comparison circuit 13 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is similar to that of the nineteenth embodiment.

(Pattern 3) When the value of the amplitude value E discrimination circuit 39 becomes active, the received signal point has the fifth smallest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 is an amplitude value E discriminating circuit 3 for the received signal points after the next.
The value of 9 is not transmitted to the adder circuit 10, and the maximum amplitude value identification circuit 7
And the amplitude value A discrimination circuit 8 and the minimum amplitude value discrimination circuit 3
3 and the value of the amplitude value D identification circuit 34 are restricted to pass. At the subsequent received signal points, the phase comparator 13 outputs the phase shift in the calculation of the equation (2) while the value of the adder circuit 10 is not active, and the frequency comparator circuit 14
Calculates the equation (3).

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the minimum amplitude value identifying circuit 3
3 or the value of the amplitude value D discriminating circuit 34 becomes active, the above-described processing of pattern 1 or pattern 2 is performed.

As described above, according to the twenty-third embodiment, after resetting the system, first, in addition to the signal point having the maximum amplitude value, the signal point having the second largest amplitude value or the minimum amplitude value. The frequency comparison can be performed by receiving a signal point having, a signal point having a third smallest amplitude value, or a signal point having a fifth smallest amplitude value.

Further, if the occurrence probabilities of the respective received symbol points are equal, these signals are received with a probability of 28/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are seven times as many occurrences as there are four quarters, so synchronization can be established in one seventh the time.

Further, since the reception point monitoring is continued even after the frequencies are once synchronized and the frequency phase comparison is finally made with reference to the reception points existing on the straight line 15, the circuit scale is larger than that of the nineteenth embodiment. However, it has the feature that no phase error occurs.

(Embodiment 25) FIG. 51 shows a second embodiment of the present invention.
5 shows the configuration of a frequency / phase comparator 5 in the fifth embodiment, and the overall configuration of a QAM receiver including the frequency / phase comparator 5 is the same as in FIG. Note that the coordinates in FIG. 52 are the first in the IQ plane in 256QAM for simplicity.
Although only the quadrant is shown, the second, third, and fourth quadrants are rotated around the origin O. Also, FIG.
In FIG. 1, the same parts as those in FIG.

In this embodiment, an amplitude value limiting circuit 32 is added to FIG. The amplitude value limiting circuit 32 determines the amplitude value identifying circuits 7, 8, 25, depending on the position of the received signal point.
It is a circuit that restricts the outputs of 33, 34 and 39 from being transmitted to the adder circuit 10. The value of the adder circuit 10 is not fed back to itself, and the process stop is controlled by the amplitude value limiting circuit 32.

Immediately after the system is reset, the amplitude value limiting circuit 32 does not limit anything and transmits the information of each amplitude value identifying circuit to the adding circuit 10 as it is. The amplitude value limiting circuit 32 does not limit anything until the value of the adding circuit 10 becomes active.

When the value of the adder circuit 10 becomes active for the first time after resetting, the respective amplitude value identification circuits 7, 8, 2
The operation of the amplitude value limiting circuit 32 and the subsequent processing differ depending on which of the outputs 5, 5, 33, 34 and 39 is activated. When the maximum amplitude value identification circuit 7, the amplitude value B identification circuit 25, the minimum amplitude value identification circuit 33, or the amplitude value D identification circuit 34 is activated, the pattern 1 is set, and when the amplitude value A identification circuit 8 is activated, the pattern 1 is set. Pattern 2 and the case where the amplitude value E identification circuit 39 is activated are referred to as pattern 3.

(Pattern 1) Maximum amplitude value identifying circuit 7 or amplitude value B identifying circuit 25 or minimum amplitude value identifying circuit 33
Alternatively, when the value of the amplitude value D identification circuit 34 becomes active, the received signal point has the maximum amplitude value or the fourth largest amplitude value or the minimum amplitude value or the third smallest amplitude value, which are on the straight line 15. Exists. Amplitude value limiting circuit 3
2 stops the processing of the adder circuit 10 and causes the phase comparison circuit 13
Calculates the equation (1) and outputs the phase difference. The subsequent operation is the same as in the twentieth embodiment.

(Pattern 2) When the value of the amplitude value A discrimination circuit 8 becomes active, the received signal point has the second largest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. In addition, the amplitude value limiting circuit 32
Is the amplitude value A discrimination circuit 8 for the received signal points after the next.
And the value of the amplitude value E identification circuit 39 is not transmitted to the addition circuit 10, and the maximum amplitude value identification circuit 7 and the amplitude value B identification circuit 25
And the values of the minimum amplitude value identification circuit 33 and the amplitude value D identification circuit 34 are restricted to pass. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparator 13 outputs the phase shift in the calculation of the formula (2), and the frequency comparison circuit 14 calculates the formula (3). I do.

At the subsequent reception signal points, the adder circuit 10 is first
When the value of becomes active, the amplitude value limiting circuit 32 stops the processing of the adding circuit 10. And the phase comparison circuit 1
3 calculates the equation (1) instead of the equation (2) and outputs the phase shift. The frequency comparison circuit 14 calculates the frequency shift from this value. The subsequent operation is the same as in the twentieth embodiment.

(Pattern 3) When the value of the amplitude value E discrimination circuit 39 becomes active, the received signal point has the fifth smallest amplitude value. The phase comparison circuit 13 calculates the equation (1) and outputs the phase difference. Note that at this time, the adder circuit 10 is not stopped yet. Also, the amplitude value limiting circuit 3
2 does not transmit the value of the amplitude value E identifying circuit 39 to the adding circuit 10 for the subsequent received signal points, and the maximum amplitude value identifying circuit 7, the amplitude value A identifying circuit 8 and the amplitude value B identifying circuit 2
5 and the minimum amplitude value identification circuit 33 and the amplitude value D identification circuit 34 are limited to pass. At the subsequent reception signal points, while the value of the adder circuit 10 is not active, the phase comparator 13 outputs the phase shift in the calculation of the formula (2), and the frequency comparison circuit 14 calculates the formula (3). I do.

At the subsequent reception signal points, the adder circuit 10 is first
When the value of is activated, the maximum amplitude value identification circuit 7
Alternatively, the amplitude value A identifying circuit 8 or the amplitude value B identifying circuit 25
Alternatively, since the value of the minimum amplitude value identification circuit 33 or the amplitude value D identification circuit 34 becomes active, the above pattern 1
Alternatively, the processing of pattern 2 is performed.

As described above, according to the twenty-fifth embodiment, after resetting the system, in addition to the signal point having the maximum amplitude value first, the signal point having the second largest amplitude value or the fourth signal point having the largest amplitude value. A feature that frequency comparison can be performed by receiving a signal point having a large amplitude value, a signal point having a minimum amplitude value, a signal point having a third smallest amplitude value, or a signal point having a fifth smallest amplitude value. Have.

If the occurrence probabilities of the received symbol points are equal, these signals are received with a probability of 32/256, and therefore 256 signals in the case of only the signals at the four corners having the conventional maximum amplitude value are targeted. There are eight times as many occurrences as there are four quarters, so synchronization can be established in one eighth of the time.

Further, even after the frequencies are synchronized once, the reception point monitoring is continued, and finally the frequency phase comparison is performed with reference to the reception points existing on the straight line 15. Therefore, the circuit scale is larger than that in the twentieth embodiment. However, it has the feature that no phase error occurs.

[0271]

As is apparent from the above description of the embodiments, in the frequency synchronization method and apparatus of the present invention, even in the case of quadrature amplitude modulation having a large number of multi-values, the four corners on the IQ plane are compared. In addition to the symbol points, the surrounding symbol points are IQ
By using this to determine the position of the orthogonal coordinate axes, it is possible to establish synchronization between the received carrier frequency and the reproduced carrier frequency in a shorter time.

After frequency synchronization is established using the four corners and the peripheral symbol points, the frequency synchronization is performed by switching the symbol points used for the determination to the four corner points and a narrower range of the peripheral symbol points. By performing the processing and finally performing the frequency synchronization processing only at the symbol points on the diagonal line of the IQ axis, the frequency synchronization can be established in a shorter time and the phase error can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a QAM receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a frequency phase comparator which constitutes a part of the QAM receiver according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the first embodiment of the present invention that are present in the first quadrant.

FIG. 4 is a characteristic diagram showing the positions of symbol points in the process of synchronizing from a state where frequencies are not synchronized in the QAM receiver according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to a second embodiment of the present invention.

FIG. 6 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the second embodiment of the present invention, which are present in the first quadrant.

FIG. 7 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to a third embodiment of the present invention.

FIG. 8 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the third embodiment of the present invention, which are present in the first quadrant.

FIG. 9 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to a fourth embodiment of the present invention.

FIG. 10 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the fourth embodiment of the present invention that are present in the first quadrant.

FIG. 11 is a block diagram of a frequency phase comparator that constitutes a part of a QAM receiver according to a fifth embodiment of the present invention.

FIG. 12 is a characteristic diagram showing symbol points used in the QAM receiver according to the fifth embodiment of the present invention, which are present in the first quadrant.

FIG. 13 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to a sixth embodiment of the present invention.

FIG. 14 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the sixth embodiment of the present invention, which are present in the first quadrant.

FIG. 15 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to a seventh embodiment of the invention.

FIG. 16 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the seventh embodiment of the present invention, which are present in the first quadrant.

FIG. 17 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to an eighth embodiment of the invention.

FIG. 18 is a characteristic diagram showing symbol points used in the QAM receiver according to the eighth embodiment of the present invention, which are present in the first quadrant.

FIG. 19 is a block diagram of a frequency phase comparator which constitutes a part of a QAM receiver according to a ninth embodiment of the present invention.

FIG. 20 is a characteristic diagram showing symbol points used in the QAM receiving apparatus according to the ninth embodiment of the present invention, which are present in the first quadrant.

FIG. 21 is a QAM according to the tenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 22 is a QAM according to the tenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 23 is a QAM according to the eleventh embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 24 is a QAM according to the eleventh embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 25 is a QAM according to the twelfth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 26 is a QAM according to the twelfth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 27 is a QAM according to the thirteenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 28 is a QAM according to the thirteenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 29 is a QAM according to the fourteenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 30 is a QAM according to the fourteenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 31 is a QAM according to the fifteenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 32 is a QAM according to the fifteenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 33 is a QAM according to the 16th embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 34 is a QAM in the sixteenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 35 is a QAM in the seventeenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 36 is a QAM in the seventeenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 37 is a QAM in the eighteenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 38 is a QAM in the eighteenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 39 is a QAM according to the nineteenth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 40 is a QAM in the nineteenth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 41 is a QAM according to the twentieth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 42 is a QAM according to the twentieth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 43 is a QAM in the twenty-first embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 44 is a QAM in the twenty-first embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 45 is a QAM according to the 22nd embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 46 is a QAM according to the 22nd embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 47 is a QAM in the twenty-third embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 48 is a QAM according to the 23rd embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 49 is a QAM in the twenty-fourth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 50 is a QAM in the twenty-fourth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 51 is a QAM in the twenty-fifth embodiment of the present invention.
Block diagram of frequency phase comparator that forms part of receiver

FIG. 52 is a QAM in the twenty fifth embodiment of the present invention.
Characteristic diagram showing the symbol points used in the receiving device in the first quadrant

FIG. 53 is a characteristic diagram showing symbol points used in the QAM receiver in the outline of the present invention, which are present in the first quadrant.

FIG. 54 is a characteristic diagram showing a symbol point existing in the first quadrant on Cartesian coordinates in 256QAM in the conventional method and the frequency synchronization method and apparatus according to the embodiment of the present invention.

FIG. 55 is a rotation locus diagram of the symbol points existing in the first quadrant on the orthogonal coordinates in 256QAM and the reception symbol points at the time of asynchronization in the conventional method and the frequency synchronization method and apparatus according to the embodiment of the present invention.

FIG. 56 is a rotation locus diagram of 16QAM of received symbol points when the received carrier and the recovered carrier have the same frequency and a non-zero phase difference in the conventional method and the frequency synchronization method according to the embodiment of the present invention.

FIG. 57 is 16QAM of a reception symbol point when a reception carrier and a reproduction carrier have a frequency frequency difference in the conventional method and the frequency synchronization method according to the embodiment of the present invention.
Rotation locus map

FIG. 58: Q using frequency synchronization method according to conventional method
Block diagram of AM digital demodulator

FIG. 59: Q using frequency synchronization method according to conventional method
Block diagram of frequency phase comparator forming part of AM digital demodulator

FIG. 60 is a characteristic diagram showing the positions of symbol points in the process of synchronizing from a state where frequencies are not synchronized in the QAM receiver according to the conventional method.

[Explanation of symbols]

1 QAM receiver analog-digital (A
/ D) Converter 2 Detector in QAM receiver 3 Roll-off filter in QAM receiver 4 Bit converter in QAM receiver 5 Frequency phase comparator in QAM receiver 6 Amplitude calculation circuit in frequency phase comparator of QAM receiver 7 Maximum amplitude discrimination circuit in frequency phase comparator of QAM receiver 8 Amplitude value A discrimination circuit in frequency phase comparator of QAM receiver 9 Symbol point determination circuit in frequency phase comparator of QAM receiver 10 Frequency phase of QAM receiver Adder circuit in the comparator 11 Frequency calculation circuit in the QAM receiver Phase calculation circuit in the frequency comparator 12 Phase rotation circuit in the frequency phase comparator of the QAM receiver 13 Frequency of the QAM receiver Phase comparator circuit in the phase comparator 14 Frequency of the QAM receiver To the phase comparator Frequency comparison circuit 15 Straight line showing diagonal line of IQ plane 16 Symbol point having maximum amplitude value 17 Symbol point having second largest amplitude value 18 Symbol point having second largest amplitude value 19 Second largest amplitude Arc corresponding to the amplitude value of the symbol point having the value 20 Arc corresponding to the amplitude value of the symbol point having the maximum amplitude value 21 Received symbol point 22 Received symbol point 23 Symbol point after phase correction of 22 22 Ideal symbol point 25 Amplitude value B discrimination circuit in frequency phase comparator of QAM receiver 26 Symbol point 27 having fourth largest amplitude value 27 Circular arc corresponding to amplitude value of symbol point having fourth largest amplitude value 28 QAM receiver frequency Amplitude value C identification circuit in phase comparator 29 Symbol point with third largest amplitude value 30 Third largest value Symbol point having amplitude value 31 Circular arc corresponding to amplitude value of symbol point having third largest amplitude value 32 Amplitude value limiting circuit in frequency phase comparator of QAM receiving apparatus 33 Minimum amplitude in frequency phase comparator of QAM receiving apparatus Value discriminating circuit 34 Amplitude value in frequency phase comparator of QAM receiver D discriminating circuit 35 Symbol point having minimum amplitude value 36 Symbol point having third smallest amplitude value 37 Corresponding to amplitude value of symbol point having minimum amplitude value Circular arc 38 Circular arc corresponding to the amplitude value of the symbol point having the third smallest amplitude value 39 Amplitude value E discrimination circuit in the frequency phase comparator of the QAM receiver 40 40 Symbol point having the fifth smallest amplitude value 41 5th Symbol point with the smallest amplitude value 42 The circle corresponding to the amplitude value of the symbol point with the fifth smallest amplitude value 43 analog-digital (A / D) converter in frequency phase comparator of QAM receiver 44 detector in frequency phase comparator of QAM receiver 45 roll-off filter in frequency phase comparator of QAM receiver 46 of QAM receiver Bit converter in frequency phase comparator 47 Frequency phase comparator in frequency phase comparator of QAM receiving apparatus 48 Amplitude calculation circuit in frequency phase comparator of QAM receiving apparatus 49 Maximum amplitude discriminating circuit in frequency phase comparator of QAM receiving apparatus 50 Symbol point determination circuit in frequency phase comparator of QAM receiver 51 Phase calculation circuit in frequency phase comparator of QAM receiver 52 Phase rotation circuit in frequency phase comparator of QAM receiver 53 Phase in frequency phase comparator of QAM receiver Comparison Symbol point 59 ideal symbol point after the linear 57 received symbol point 58 points 22 indicating the diagonal of the frequency comparator circuit 55 receives the symbol point 56 I-Q plane and phase correction in the frequency phase comparator of the road 54 QAM receiver apparatus

Claims (25)

[Claims] 1. A reception symbol point having the largest amplitude value, or 2 in order to synchronize the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation.
When the reception symbol point having the second largest amplitude value is received, the orthogonal coordinate axis is rotated so as to move the reception symbol point to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. Frequency synchronization method. 2. A reception symbol point having the largest amplitude value, or 2 in order to synchronize the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation.
When the reception symbol point having the second largest amplitude value or the reception symbol point having the fourth largest amplitude value is received, the reception symbol point is placed on the straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. A frequency synchronization method characterized by rotating a Cartesian coordinate axis so as to move. 3. A reception symbol point having the largest amplitude value, or 2 in order to synchronize the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation.
When the received symbol point with the second largest amplitude value, the received symbol point with the third largest amplitude value, or the received symbol point with the fourth largest amplitude value is received,
A frequency synchronization method characterized by rotating an orthogonal coordinate axis so as to move the received symbol point on a straight line connecting an origin O and an ideal symbol point having a maximum amplitude value. 4. A reception symbol point that determines the amount of rotation of a rectangular coordinate axis according to the frequency synchronization state in order to synchronize the frequency of a modulated carrier wave of a multilevel quadrature amplitude modulation signal with the frequency of a reproduced carrier wave used for demodulation. The frequency synchronization method according to claim 1, 2 or 3, wherein the switching is performed. 5. A reception symbol point having the smallest amplitude value, or 3 in order to synchronize the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation.
When the reception symbol point having the second smallest amplitude value is received, the orthogonal coordinate axes are rotated so as to move the reception symbol point to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. Frequency synchronization method. 6. A reception symbol point having the smallest amplitude value, or 3 in order to synchronize the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation.
When the reception symbol point having the smallest amplitude value or the reception symbol point having the fifth smallest amplitude value is received, the reception symbol point is placed on the straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. A frequency synchronization method characterized by rotating a Cartesian coordinate axis so as to move. 7. A reception symbol point for determining a rotation amount of a rectangular coordinate axis according to a frequency synchronization state in order to synchronize a frequency of a modulated carrier wave of a multilevel quadrature amplitude modulation signal with a frequency of a reproduced carrier wave used for demodulation. 7. The frequency synchronization method according to claim 5, wherein the frequency synchronization method is switched. 8. A reception symbol point having the largest amplitude value or a reception symbol point having the smallest amplitude value for synchronizing the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation. When you receive
A frequency synchronization method characterized by rotating an orthogonal coordinate axis so as to move the received symbol point on a straight line connecting an origin O and an ideal symbol point having a maximum amplitude value. 9. A reception symbol point having the largest amplitude value, or 2 in order to synchronize the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation.
When the reception symbol point having the second largest amplitude value or the reception symbol point having the smallest amplitude value is received, the reception symbol point is moved to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. A frequency synchronization method characterized by rotating orthogonal coordinate axes as described above. 10. The reception symbol point having the largest amplitude value or the reception symbol having the second largest amplitude value for synchronizing the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation. Symbol point or 4
When the reception symbol point having the second largest amplitude value or the reception symbol point having the smallest amplitude value is received, the reception symbol point is moved to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. A frequency synchronization method characterized by rotating orthogonal coordinate axes as described above. 11. A reception symbol point having the largest amplitude value or a reception having the second largest amplitude value in order to synchronize the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation. Symbol point or 3
When the reception symbol point having the second largest amplitude value, the reception symbol point having the fourth largest amplitude value, or the reception symbol point having the smallest amplitude value is received, the reception symbol point is set to the origin O and the maximum amplitude value. A frequency synchronization method characterized in that the Cartesian coordinate axis is rotated so as to move on a straight line connecting an ideal symbol point having. 12. In order to synchronize the frequency of the modulated carrier wave of the multi-level quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation, the reception symbol points that determine the rotation amount of the orthogonal coordinate axis are switched according to the frequency synchronization state. The frequency synchronization method according to any one of claims 8 to 11, wherein the frequency synchronization method is performed. 13. A reception symbol point having the largest amplitude value or a reception symbol point having the smallest amplitude value for synchronizing the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation. , Or when the received symbol point with the third smallest amplitude value is received,
A frequency synchronization method characterized by rotating an orthogonal coordinate axis so as to move the received symbol point on a straight line connecting an origin O and an ideal symbol point having a maximum amplitude value. 14. The reception symbol point having the largest amplitude value or the reception symbol having the second largest amplitude value for synchronizing the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation. When a symbol point, a reception symbol point having the smallest amplitude value, or a reception symbol point having the third smallest amplitude value is received, the reception symbol point is connected to the origin O and the ideal symbol point having the maximum amplitude value. A frequency synchronization method characterized by rotating an orthogonal coordinate axis so as to move on a straight line. 15. The reception symbol point having the largest amplitude value or the reception symbol having the second largest amplitude value for synchronizing the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation. Symbol point or 4
When the received symbol point having the second largest amplitude value, the received symbol point having the smallest amplitude value, or the received symbol point having the third smallest amplitude value is received, the received symbol point is set to the origin O and the maximum amplitude value. A frequency synchronization method characterized in that the Cartesian coordinate axis is rotated so as to move on a straight line connecting an ideal symbol point having. 16. The reception symbol point having the largest amplitude value or the reception symbol having the second largest amplitude value for synchronizing the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation. Symbol point or 3
Received the received symbol point with the second largest amplitude value, the received symbol point with the fourth largest amplitude value, the received symbol point with the smallest amplitude value, or the received symbol point with the third smallest amplitude value. A frequency synchronization method characterized in that the orthogonal coordinate axis is rotated so that the received symbol point is sometimes moved to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. 17. In order to synchronize the frequency of a modulated carrier wave of a multi-valued quadrature amplitude modulation signal and the frequency of a reproduced carrier wave used for demodulation, a reception symbol point that determines the rotation amount of a rectangular coordinate axis is switched according to the frequency synchronization state. The frequency synchronization method according to any one of claims 13 to 16, wherein the frequency synchronization method is performed. 18. A reception symbol point having the largest amplitude value or a reception symbol point having the smallest amplitude value for synchronizing the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation. , Or when a reception symbol point having the third smallest amplitude value or a reception symbol point having the fifth smallest amplitude value is received, the reception symbol point is connected to the origin O and the ideal symbol point having the maximum amplitude value. A frequency synchronization method characterized by rotating an orthogonal coordinate axis so as to move on a straight line. 19. The reception symbol point having the largest amplitude value or the reception symbol having the second largest amplitude value for synchronizing the frequency of the modulated carrier of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier used for demodulation. When the symbol point, the received symbol point with the smallest amplitude value, the received symbol point with the third smallest amplitude value, or the received symbol point with the fifth smallest amplitude value is received, the received symbol point is the origin. A frequency synchronization method characterized by rotating an orthogonal coordinate axis so as to move on a straight line connecting O and an ideal symbol point having a maximum amplitude value. 20. In order to synchronize the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation, the reception symbol point having the largest amplitude value or the reception symbol point having the second largest amplitude value is received. Symbol point or 4
If the received symbol point with the next largest amplitude value, the received symbol point with the smallest amplitude value, the received symbol point with the third smallest amplitude value, or the received symbol point with the fifth smallest amplitude value is received A frequency synchronization method characterized in that the orthogonal coordinate axes are rotated so as to move the received symbol point on a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. 21. In order to synchronize the frequency of a modulated carrier wave of a multilevel quadrature amplitude modulation signal with the frequency of a reproduced carrier wave used for demodulation, a reception symbol point having the largest amplitude value or a reception symbol point having the second largest amplitude value. Symbol point or 3
Received symbol point having the second largest amplitude value, or received symbol point having the fourth largest amplitude value, or received symbol point having the smallest amplitude value, or received symbol point having the third smallest amplitude value, or 5 When the reception symbol point having the second smallest amplitude value is received, the orthogonal coordinate axes are rotated so as to move the reception symbol point to a straight line connecting the origin O and the ideal symbol point having the maximum amplitude value. Frequency synchronization method. 22. In order to synchronize the frequency of the modulated carrier wave of the multi-valued quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation, the reception symbol points that determine the rotation amount of the orthogonal coordinate axis are switched according to the frequency synchronization state. The frequency synchronization method according to any one of claims 18 to 21, wherein the frequency synchronization method is performed. 23. The frequency synchronization method according to claim 1, for synchronizing the frequency of the modulated carrier wave of the multilevel quadrature amplitude modulation signal and the frequency of the reproduced carrier wave used for demodulation. A frequency synchronizer equipped with frequency phase comparison means for. 24. An amplitude calculation circuit for calculating the amplitude of a reception signal point by the frequency / phase comparison means, and whether the calculated amplitude value is maximum,
Or a plurality of amplitude value identification circuits for identifying the smallest, or the largest or the smallest, and a symbol point determination circuit for determining an ideal symbol point corresponding to a received signal point from the obtained amplitude value. , A phase calculation circuit for obtaining the phase of the received signal point, an adder circuit for adding the outputs of a plurality of amplitude value identification circuits, and a phase comparison circuit for obtaining the phase difference of the received signal point from the ideal symbol point according to the output of the adder circuit When,
24. The frequency synchronization device according to claim 23, comprising a phase rotation circuit for rotating the phase of the reception signal point according to the obtained phase difference, and a frequency comparison circuit for obtaining the magnitude of the frequency deviation from the obtained phase difference. 25. The frequency synchronizer according to claim 24, wherein the frequency phase comparison means comprises an amplitude limiting circuit for limiting the transmission of the output of each amplitude value identifying circuit to the adding circuit depending on the position of the reception signal point.