JPS61207033A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent any disconnection from occurring by a method wherein a wiring corner part comprising a lower wiring layer made of polysilicon film is rounded by thermal oxidation. CONSTITUTION:An oxide film comprising the third oxide film 9 is arranged on a polysilicon film 5 in parallel with the oxide film 9 by pyro-oxidation e.g. at 1,000 deg.C for around 150min simultaneously the polysilicon film 5 is converted into the oxide film 9 from the surface side to form the oxide film 9 around 6,000Angstrom in total film thickness. At this time, the oxide film is formed on the polysilicon film 5 below a pattern 8 to provide both shoulder parts of the polysilion film 5 comprising a gate electrode with pertinent radius 5a. Next the oxide film 9 and the residual polysilicon film 5 not yet converted is anisotropically etched by RIE process using the pattern 8 as a mask to leave the polysilicon film 5 below the pattern 8. Through these procedures, a wiring may be processed without any possibility of disconnection at all.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device having multilayer wiring such as a MOSFET, and relates to a method for manufacturing a semiconductor device having multilayer wiring such as a MOSFET. The aim is to provide a device that prevents wire breakage.

(b) Conventional technology As semiconductor devices become more highly integrated, prevention of disconnection in multilayer interconnections has become an important issue (for example, Japanese Patent Laid-Open No. 56-17023
(see publication). In a general MOSFET, as shown in Fig. 1s2, a lower wiring layer (support) such as a gate electrode is provided on the semiconductor substrate (2) with a gate oxide film (2) interposed between them, and an interlayer insulating film is coated on top of this lower wiring layer. An upper wiring layer (material) is provided through this layer. The lower wiring layer ■ is formed using RIE (IJ active ion etching).
Since we are responding to miniaturization using technology, the wiring corner part (
22a) is formed at a right angle or at an angle close to a right angle. Upper layer wiring is formed on the lower wiring layer 1 through the interlayer insulating film as described above.

It is the intention to set up a layer (goods), and this upper layer wiring layer example is the step part (
If the wall thickness at 241) cannot be sufficiently thickened, the wire may be broken and molded.

(c) Problems to be Solved by the Invention The present invention takes such disconnection accidents into consideration and provides a method for manufacturing a semiconductor device that can utilize RIE technology useful for miniaturizing interconnections. .

B) Means for Solving the Problems The present invention is characterized in that the lower wiring layer is composed of a polysilicon film, and the wiring corners of this polysilicon film are rounded by thermal oxidation technology. a first step in which a 'F41 oxide film and a polysilicon film are sequentially stacked on the element region of the device region; a second step in which a second oxide film and a nitride film are sequentially stacked on the polysilicon film; Second
a third step of forming a pattern by leaving a part of the polymer film made of an oxide film and a nitride film in the device region and removing the other part, and thermally oxidizing the polysilicon film to form a pattern on its surface. an s4 step of converting the polysilicon film into a 3i83 oxide film from the side, and a step of removing the third oxide film and the polysilicon film that was not converted in the fourth step by an anisotropic etching method (for example, RIE) using the pattern as a mask. This is a method for manufacturing a semiconductor device comprising five steps.

(E) Effect In the present invention, during the thermal oxidation in the fourth step, the polysilicon film under the polymer film left in the third step is also
The closer to the top surface of the polysilicon film and the closer to the outside of the polymer film, the more the conversion into a larger oxide film is promoted. Therefore, when anisotropic etching is performed in a later step and the polymer film is removed, the converted portions are also removed at the same time, and the corner portions of the polysilicon film (lower wiring layer) left after the fifth step are removed at the same time. Rounds will be processed.

(f) Example FIG. 1 is a process explanatory diagram of one example of the method of the present invention. In this embodiment, a silicon MO8 integrated circuit element in which the lower wiring layer is made of a polysilicon film and the upper wiring layer is made of aluminum will be described.

On a semiconductor substrate (1) made of single crystal silicon, an element isolation part (3) for isolating an element region (2+) is formed, for example, by the Locos method.A silicon oxide film (hereinafter referred to as During the process of forming a gate oxide film (simply referred to as an oxide film), a gate oxide film is formed on the element region (2).
1 oxide film (4) is formed. In this step, in order to lower the resistance of this polysilicon film (5), phosphorus is doped by POC43 diffusion (first step, FIG. 1a). Next, on this polysilicon film (5), SiH4
(7) [Second oxide film (6) using low pressure CVD method
was formed at 1500A@, and 3ooor nitride (nitride film) (7) was formed on it with NHs and S i H2Cj'2
A nitride film (7) and a nitride film (7) are attached thereto (not shown) and subjected to exposure and development to leave a part of the element region and remove the other part, so that a pattern (8) remains on the gate electrode formation part. The second oxide film (6) is removed by etching (third step, C in the same figure). Next, 1000° C. pyrooxidation was applied for about 150 minutes to form an oxide film constituting the third oxide film on the polysilicon film (5) and convert the polysilicon film into the third oxide film from the surface side. A third oxide film (9) having a total thickness of approximately 600 OA' is formed (fourth step).

At this time, as shown in FIG. 1d, an oxide film is also formed on the polysilicon film (51) under the pattern (8) like a bird's beak in the LOCOS method, and as a result, both shoulders of the polysilicon film constituting the gate electrode are Next, using the pattern (8) as a mask, the third oxide film (9) and the polysilicon remaining without being converted in the fourth step are formed. The film (5) is anisotropically etched using the RIE method to leave the polysilicon film under the pattern (8) (fifth step, FIG. 1C). Next, the polysilicon film (5) that will become the gate electrode is etched. 5) Upper nitride film (7)
Then, the second oxide film (6) is removed by etching, a diffusion layer αOα1) which will become the source and drain is formed by ion implantation, and the fourth oxide film (121 is made of SiH4 and 0
A contact hole Q3) is formed by the atmospheric pressure CVD method using the reaction described in step 2, and a contact hole Q3) is formed, and the space between the aluminum films is deposited and a wiring process is performed (f in the same figure). The aluminum wiring (upper wiring layer) formed in this way has an interlayer insulating film ■ The underlying polysilicon film (lower wiring layer) is rounded at both shoulders of the wiring, that is, it is cut at right angles as in the conventional method. Since the wires are not connected to each other, wiring can be processed without fear of disconnection, contributing to improved yields of semiconductor devices.

(g) Effects of the Invention In the present invention, as described above, the lower wiring layer is composed of a polysilicon film, and the portion under the mask is partially converted into an oxide film during thermal oxidation to form a radius. Even if the RIE method, which is useful for miniaturization technology, is used, it is possible to make some of the corners of the lower wiring layer iζ rounded, and therefore the step of the upper wiring layer attached via the interlayer insulating layer becomes gentler. Disconnection can be prevented.

[Brief explanation of drawings]

FIGS. 1A to 1F are process explanatory diagrams of one embodiment of the method of the present invention, and FIG. 2 is a sectional view showing the configuration of a general multilayer (two-layer) wiring. (1)... Semiconductor substrate, +4) (6) [9)... 1.3N2, third oxide film, (5)... Polysilicon film.

Claims (1)

[Claims] (1) A first step in which a first oxide film and a polysilicon film are sequentially stacked on the element region of a semiconductor substrate, and a second step in which a second oxide film and a nitride film are sequentially stacked on the polysilicon film. a third step of forming a pattern by leaving a part of the polymer film made of the second oxide film and the nitride film in the element region and removing the other part; and a third step of thermally oxidizing the polysilicon film. An oxide film is provided on the polysilicon film, and a third layer is formed on the polysilicon film from the surface side.
a fourth step of converting into an oxide film; and a fifth step of removing the third oxide film and the polysilicon film that was not converted in the fourth step by an anisotropic etching method using the pattern as a mask. A method for manufacturing a semiconductor device.