JPS61205149U - - Google Patents
Info
- Publication number
- JPS61205149U JPS61205149U JP8977185U JP8977185U JPS61205149U JP S61205149 U JPS61205149 U JP S61205149U JP 8977185 U JP8977185 U JP 8977185U JP 8977185 U JP8977185 U JP 8977185U JP S61205149 U JPS61205149 U JP S61205149U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- island
- fence
- edge
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Description
第１図は本考案のリードフレームの構成図、第
２図は、縦断面図、第３図は従来のリードフレー
ムの規格を違反したリードフレームの外観図、第
４図は、リードフレームに合わせてＩＣペレツト
のサイズを変更した図、第５図は本考案のリード
フレームの外観図である。 １……ＩＣペレツト、２……出力ピン、３……
導体器、４……絶縁塀、５……リードフレーム、
６……アイランド、７……リード線、８……ワイ
ヤ。
２図は、縦断面図、第３図は従来のリードフレー
ムの規格を違反したリードフレームの外観図、第
４図は、リードフレームに合わせてＩＣペレツト
のサイズを変更した図、第５図は本考案のリード
フレームの外観図である。 １……ＩＣペレツト、２……出力ピン、３……
導体器、４……絶縁塀、５……リードフレーム、
６……アイランド、７……リード線、８……ワイ
ヤ。
Claims (1)
- アイランド縁に塀を有することを特徴とするリ
ードフレーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8977185U JPS61205149U (ja) | 1985-06-14 | 1985-06-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8977185U JPS61205149U (ja) | 1985-06-14 | 1985-06-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61205149U true JPS61205149U (ja) | 1986-12-24 |
Family
ID=30644164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8977185U Pending JPS61205149U (ja) | 1985-06-14 | 1985-06-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61205149U (ja) |
-
1985
- 1985-06-14 JP JP8977185U patent/JPS61205149U/ja active Pending