JPS61204950A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a wiring thickly with good selectivity, by growing a wiring material in a region, where the wiring is to be formed, on the surface of a semiconductor substrate covered by an insulating film in a vapor phase, applying an RF bias to the substrate, sputtering the surface of the substrate by inactive gas ions, and forming the wiring. CONSTITUTION:On a silicon substrate 1, a one-conducting type impurity diffused layer 12 is formed. An SiO2 film 11 is formed on the surface of the substrate by thermal oxidation or a CVD (chemical vapor deposition) method. A contact hole 13 is provided in said SiO2 film so as to face the impurity diffused layer. Then, RF bias is applied to the substrate 1. SiF4 and W on the surface of the substrate 1 undergo sputter etching by argon ions. Oxidizing reducing reaction of tungsten hexafluoride, the substrate silicon and hydrogen is performed by a low-pressure chemical vapor deposition method (LPCVD), and a tungsten film 14 is selectively embedded in the contact hole without depositing it on SiO2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming electrode wiring.

(Technical background of the invention and its problems) As LSIs become more highly integrated, chips become more complex and the number of wires required per unit area increases, making multilayer wiring technology increasingly important.

Conventionally, the wiring width of the second layer was made wider than the wiring width of the first layer, or the wiring width of the first layer was made tapered to alleviate irregularities and deal with disconnections. If this is the case, or if a third or fourth layer becomes necessary, it becomes impossible to cope with this alone.

Further, as the degree of integration increases and patterns become finer, the impurity diffusion layer has become extremely shallow, and in transistors and the like, it has come to be formed with a depth of 0.2- or less.

If such a shallow diffusion layer is used and the electrode is formed and covered with ordinary aluminum, the heat treatment during the manufacturing process will cause the aluminum and the silicon substrate to diffuse into each other, causing aluminum spikes to enter the impurity diffusion layer. ,base,
This can cause emitter junction short circuits and diffusion junction breakdown. On the other hand, when forming electrodes using aluminum containing excessive silicon, which is one method of preventing junction breakdown, silicon precipitates in the contact area between the diffusion layer and the aluminum, resulting in an increase in resistance. There are other problems.

Therefore, as a means to solve the above-mentioned problems, a high melting point metal such as tungsten is selectively buried in the through-hole portion between the aluminum wiring and the substrate silicon, or between the lower layer wiring and the upper layer wiring using a vapor phase growth method. is being carried out.

The selective vapor phase growth method will be explained using tungsten as an example. The reaction is an oxidation-reduction reaction that proceeds as follows.

Han Fe (zo)7H2(9)・+Si(S(substrate))→
W (S) + SF4 (9> + 2tlF (S?
) First, substrate silicon and -F6 react, W is formed on the substrate surface, which becomes a nucleus, and W reduced with hydrogen.
This is the way to grow. Therefore, W grows only on the exposed portions of silicon or on the metal surface, and does not grow on 5i02J:, so it is called a selective vapor phase growth method.

However, the above method has good selectivity only up to a film thickness of 2,000 mm at most, and if you try to embed more than 5 inches,
W also grows on z, resulting in poor selectivity. This is because SiF4, which is a reaction product waste absorbed on 5i02 J-, becomes a nucleus, and W grows on 5i02 as well. The reason why the selectivity deteriorates from 2000 Å or more is that at the beginning of the reaction, SiF4 adsorbed a very small amount and was unstable, but as the deposition time progressed, SiF4
This is thought to be due to the fact that the suction @hang also increases and becomes stable.

It is estimated that approximately 2,000 people were deposited during that time.

[Purpose of the invention]

The present invention is an improvement over the above-mentioned conventional problems, and aims to provide a method for manufacturing a semiconductor device that enables thick wiring to be formed with good selectivity.

(Summary of the Invention) The present invention selectively grows a wiring material in a vapor phase in a region on the surface of a semiconductor substrate covered with an insulating film where wiring is to be formed, and at the same time applies an RF bias to the substrate. The method is characterized in that wiring is formed by sputtering with inert gas ions.

〔Effect of the invention〕

According to the present invention, it is possible to embed wiring material with high selectivity into contact holes and through balls with a depth of 1- or more, improving the purity of the film and obtaining low contact resistance. This reaction could also be prevented.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic diagram of an apparatus used in an embodiment of the present invention. A silicon substrate 1 is placed on a quartz cathode electrode 2 which is biased by a power supply 5 through a conductor 20. An anode 3 fixed to a chamber 6 is opposed to it in parallel. 7 is a fluorine-based resin insulator, 9 is a shield, 10 is cooling water flowing through a conductor 20, and 8 and 18 are magnets 1 to 1. Atmosphere 4 is a mixture of argon, tungsten hexafluoride, and hydrogen gas.

FIG. 1 shows the manufacturing process of an embodiment of the present invention. First, an impurity diffusion layer 12 of one conductivity type is provided on a silicon substrate 1 by a known method, and the substrate surface is subjected to thermal oxidation or C.
5iOzl by VD (vapor phase chemical reaction) method! A contact hole 13 is formed in the 5iOz film for the impurity diffusion layer (see FIG. 1). Using the apparatus shown in FIG. 2, R bias is applied to the substrate 1, and S
While iF, 1, and W are sputter-etched with argon ions, tungsten hexafluoride is subjected to an oxidation-reduction reaction with the substrate silicon and hydrogen using a low-pressure chemical vapor deposition method (LPCVD method) to deposit a tungsten film 14 on 5i02. The contact hole was selectively filled without any damage (Fig. 1 υ
). Experimental conditions were 6F tungsten, hydrogen gas 8I
The amount is 1-2 respectively;caf/l1lin, 10-1
000 i/min, and the substrate temperature was in the range of 200 to 700°C. Next, after depositing the tungsten 14, an aluminum wiring 15 was formed (FIG. 1(C)).

As described above, the following effects could be obtained by the present invention.

■In the selective growth of tungsten, reaction product waste such as SiF4 becomes a nucleus and hinders selective growth. By sputter etching the substrate surface at the same time as the vapor phase growth of tungsten, the reaction product waste can be removed. , the selectivity of tungsten deposition was increased.

■Since sputter etching is performed simultaneously with vapor phase growth, the effect of sputter cleaning appears, and wet pretreatment is not required. In addition, the purity of the film was also increased because unreacted substances and reaction product wastes that were incorporated into the film were constantly removed by sputtering.

■It was possible to completely embed it in the contact part)
As a result, flattening was achieved and there were no disconnections in the second and third layer wiring. In general, the contact resistance has decreased, and the reaction between aluminum and silicon has disappeared.

Note that the conditions listed in the above examples are examples, and do not necessarily have to be carried out under the same conditions, and art dealers may change them to suit the conditions at the time, whether they are higher or lower than these. do not have.

In the above embodiment, the process of burying and planarizing contact holes in the diffusion layer has been described, but the same effect can be obtained for burying and planarizing through-hole portions in a multilayer wiring structure.

Moreover, although the case where the wiring material is tungsten has been given as an example, high melting point metals such as molybdenum, titanium, tantalum, etc. may also be used.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram of an apparatus used in the embodiment of the present invention. 1...Si substrate, 2...quartz electrode (cathode), 3...
・Anode, 4... Atmosphere gas (Ar & WFa & Hz
), 5... Power supply, 6... Chamber, 7... Teflon, 8... Magnet, 9... Shield, 10
...Cooling water, 11...5iO211! i! , 12・
...Impurity diffusion layer, 13...Contact hole, 14
...Tungsten film, 15...Aluminum wiring. (7317) Agent Patent Attorney Noriyuki Chika (1 idiot) Figure 1

Claims (3)

[Claims] (1) A punching step of forming a window in an insulating film formed on the surface of the substrate on which the first conductive layer is formed, and a step of forming holes in the window while sputtering the surface of the substrate with inert gas ions. A method for manufacturing a semiconductor device comprising the steps of selectively forming a conductive material constituting a second conductive layer by vapor phase growth, and then forming a third conductive layer to configure an electrode arrangement. . (2) The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is a semiconductor layer containing impurities of one conductivity type formed in a semiconductor substrate. (3) The first conductive layer is a wiring layer formed on the substrate via an insulating layer.
A method for manufacturing a semiconductor device described in Section 1.