JPS628542A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To alleviate a steep step part at the side wall of a contact hole, by forming a fist conducting layer in a vapor phase in a region, where a wiring layer is formed on the surface of a substrate, etching an insulating layer on the surface, and forming a second conducting layer. CONSTITUTION:In a P-type silicon substrate 1, arsenic ions are implanted, and an N<+> silicon diffused layer 2 is formed. Thereafter, a silicon dioxide film 3 is deposited. A contact hole 4 is provided in the film 3. Then, a tungsten film 5 grown on the surface of the layer 2, which is exposed in the contact hole 4, by a pressure reduced CVD method. Then, with the film 3 being etched, an aluminum thin film 6 is formed by a bias sputtering method. Then an aluminum thin film 7 is formed by a sputtering method. Thereafter, the film 6 and 7 are simultaneously patterned, and the aluminum wiring layer 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring layer.

[Technical background and problems] As semiconductor devices become more highly integrated, an extremely large number of elements are formed on a single semiconductor chip, wiring circuits become more complex, and the number of required wires increases. Therefore, due to the demand for miniaturization, multilayer wiring technology is becoming increasingly important.

In the multilayer wiring method, for example, a first wiring layer is formed, an interlayer insulating film is formed, a contact hole is drilled at a predetermined part of the interlayer insulating film, and a contact hole is formed in a predetermined position of the first wiring layer. A method is used in which a second wiring layer is formed on the upper layer after exposing one part of the contact hole, but in this method, if the sidewall of the contact hole is steep, the edge Disconnection is likely to occur in the second wiring layer. Therefore, for example, measures have been taken to make the width of the second wiring layer wider than that of the first layer, or to taper the stepped portion. However, if the aspect ratio of the contact hole is 1 or more, this method alone is no longer sufficient to cope with the problem.

Therefore, in order to solve these problems, contact balls between the first wiring layer (for example, aluminum layer) and the substrate (for example, silicon), or upper layer wiring and lower layer wiring (for example, first layer wiring) are used. Chemical vapor deposition (CV) is applied to the through hole between the first wiring layer and the second wiring layer.
Method D) can be used to selectively embed a thin film of a high melting point metal such as tungsten to alleviate the level difference, or a bias sputtering method can be used to form a wiring layer in such contact holes and through holes while etching the level difference. Several methods have been proposed.

In the former selective vapor deposition method in which a thin film of high-yield gold i is grown in contact holes or through holes, the reaction proceeds, for example, as follows.

WF (Q) +82 (Q) +s i (S
(Substrate))→W (S)+s i F4 ('J)+
28F (g) This reaction is a redox reaction, and first,
Silicon (S+') and tungsten hexafluoride (
WF6) reacts and tungsten (W) grows on the substrate surface, which then becomes a nucleus and tungsten (W) reduced by hydrogen grows there... and so on. go. Therefore, silicon dioxide film (Sin2
Tungsten film grows on the surface of the silicon substrate or the metal surface exposed in the through hole or contact hole formed in the insulating film, such as ), and does not grow on the insulating film.

However, this method also has good selectivity only when the film thickness is at most 20 mm.
If you try to embed more than 0OA, tungsten will grow on the insulating film as well, and the selectivity will deteriorate.
Furthermore, the film deposition rate was very slow, and it took several hours to form a 1 μm film.

In addition, the latter bias sputtering method applies a negative voltage with respect to the plasma potential not only to the target side but also to the substrate side, and sputters the substrate with gas ions at the same time as the target. By selecting the conditions, it is possible to reduce the steep step on the side wall of the through hole or contact hole, as shown in Figure 2 (a). By switching, a wiring layer can be formed as shown in FIG. 2(b).

However, there was a problem in that the substrate silicon was also etched in the contact hole, resulting in junction breakdown as shown in FIG. 2(C).

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to form a highly reliable wiring layer.

[Summary of the Invention] Therefore, in the present invention, a first conductive layer is selectively grown in a vapor phase in a region on the surface of a substrate where a wiring layer is to be formed, and then the insulating layer on the surface is etched by a bias sputtering method. By forming the second conductor layer, the edge of the side wall of the contact hole or through hole is removed and the step difference is reduced while the second conductor layer is formed.

After this, a third conductor layer is formed to form a wiring pattern of a desired shape.

The third conductor layer was formed by stopping the application of bias after forming the second conductor layer, and using a normal sputtering method.
It is convenient and desirable to perform this by depositing the same material as the second conductor layer.

Here, since the first conductive layer acts as a barrier, the substrate is prevented from being etched during etching by bias sputtering, and steps caused by through holes or contact holes are alleviated without causing junction breakdown.

[Effects of the Invention] According to the method of the present invention, it is possible to form a highly reliable a-contact layer without causing disconnection defects or the like in contact holes or through holes having an aspect ratio of 1 or more.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(d) are diagrams showing a process for forming a wiring layer according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
After forming an N+ type silicon diffusion layer 2 by ion-implanting arsenic ions into the silicon dioxide film, a silicon dioxide film 3 is deposited as an insulating layer. A contact ball 4 is drilled for I3.

Next, as shown in FIG. 1(b), a low pressure CVD method (Lr'CVD method) using tungsten hexafluoride and hydrogen as raw material gases was performed.
By method D), a tungsten film 5 as a first metal layer is selectively grown only on the surface of the N+ type silicon diffusion layer 2 exposed in the contact hole 4. The film-forming conditions were as follows: 1ffi of tungsten hexafluoride and 1ffi of hydrogen gas, respectively.
20cm3/n+in, 10~1000cm3/m
in, F, and the substrate temperature was 200 to 700°C.

Thereafter, as shown in FIG. 1C, while etching the silicon dioxide film 3 by bias sputtering, an aluminum thin film 6 is formed as a second metal layer. The film forming conditions at this time were an argon gas flow of 1140 c ~ 3 /
n+in, argon pressure 3.0×1O-1Pa, target power 500-1KW, substrate RF main power 0-100
It was set as W.

Further, a third gold layer is deposited by sputtering with the substrate RF main power O and the other conditions being the same as the bias sputtering method.
Aluminum thin II as ri layer! After forming J7, the lower aluminum film 6 and the upper aluminum thin film 7 are simultaneously patterned by photolithography.
As shown in FIG. 1(d), an aluminum wire 1Ji7 is formed.

In this method, the surface of the N0-type silicon diffusion layer exposed in the contact hole is covered with a tungsten thin film, so the substrate (N-type silicon diffusion layer) is etched when forming the aluminum thin film by bias sputtering. This prevents joint failure from occurring.

In addition, since the formation of the aluminum wiring layer is carried out in two steps: a bias sputtering method and a subsequent sputtering method,
Flattening is achieved and disconnection defects are reduced.

Furthermore, by forming a tungsten film between the aluminum wiring layer and the N÷ type silicon diffusion layer, the contact resistance is reduced, and there is no reaction between aluminum and silicon.

Although tungsten is used as the first conductor layer in the embodiment, it is not necessarily limited to this, and can be appropriately selected from high-melting point metals such as molybdenum, titanium, and tantalum.

Moreover, although aluminum thin films were used for both the second and third conductor layers, it goes without saying that other metals may be used, and different types of metals may be used.

Further, in the embodiment, the formation of a wiring layer in a contact hole for a diffusion layer has been described, but it goes without saying that the present invention is also effective in forming a wiring layer in a through hole in a multilayer wiring structure.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are diagrams showing the process of forming a wiring layer according to an embodiment of the present invention, and FIGS. 2(a) to (C) are diagrams showing the formation of a wiring layer using a conventional bias sputtering method. It is a figure showing a process. DESCRIPTION OF SYMBOLS 1...P type silicon substrate, 2...N+ type silicon diffusion layer, 3...Silicon dioxide film, 4...Contact hole, 5...Tungsten thin film, 6...Aluminum film (wiring) layer), 7...aluminum thin film (wiring layer). Representative Patent Attorney Takahisa Kimura Figure 1 (Q) Figure 1 (b) Figure 1 (c) Figure 1 (d)

Claims (5)

[Claims] (1) When forming a wiring layer on a substrate on which a predetermined semiconductor element region is formed, a drilling process is performed to form a contact window in an insulating film formed on the surface of the substrate, and the contact is formed by a vapor phase growth method. selectively forming a first conductive layer within the window; forming a second conductive layer while etching the insulating film by bias sputtering; and forming a third conductive layer as a wiring layer.
A method for manufacturing a semiconductor device, comprising the step of forming a conductor layer pattern. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the first conductor layer is made of a high melting point metal film. (3) The second conductive layer and the third conductive layer are made of the same metal.
) The method for manufacturing a semiconductor device according to item 2. (4) The method for manufacturing a semiconductor device according to claim (3), wherein the second and third conductive layers are made of aluminum films. (5) The method of manufacturing a semiconductor device according to claim (1), wherein the contact window is configured to make contact with an already formed wiring layer.