JPH0226049A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce contact resistance by forming a diffusion layer of the same conductive type as that of a semiconductor diffusion layer on a semiconductor substrate within a groove, embedding a first conductive layer, and then forming a second conductive layer on it. CONSTITUTION:A groove 5 is made through a diffusion layer 2 formed on a semiconductor substrate 1 on the semiconductor substrate 1 by etching the semiconductor substrate 1 within the contact window 5 and a diffusion layer 6 of the same conductive type as that of the diffusion layer 2 is formed on the semiconductor substrate 1 within this groove 5. After that, a first conductive layer 7 is embedded into the groove 5 and a second conductive layer 8 is formed on this first conductive layer 7, thus increasing the contact area of the diffusion layers 2 and 6 and the first conductive layer 7 of the semiconductor substrate 1. It reduces contact resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming contacts therein.

2. Description of the Related Art In conventional VLSI devices, the size of the contact window has become extremely small in order to increase the degree of integration, resulting in an increase in contact resistance between the wiring and the substrate. If the contact resistance is high, the characteristics of the semiconductor device may deteriorate or it may fail.

On the other hand, as the contact becomes finer, there is a problem in that the step coverage of the wiring at the contact portion deteriorates. As a method to solve this problem, a method of embedding a conductive material such as W in the contact has been proposed.

First, as an example of the prior art, a contact forming method employing a method of embedding a conductive material in a contact window will be described in detail with reference to FIGS. 2(a) to 2(d).

FIG. 2 is a cross-sectional view from the glabella insulating film formation step to the An wiring formation step, and for the sake of simplicity, only the wiring-silicon substrate contact portion is shown.

As shown in FIG. 2(a), first, a p-type silicon substrate 1
In the first step, a silicon oxide film 3 is formed as an insulating film between the eyebrows so as to cover the circuit elements (not shown) such as MO5 type transistors formed thereon and the n-type diffusion layer 2, as shown in FIG. 2(b).
As shown in FIG. 2, a contact window 5 is formed by etching the silicon oxide film 3 on the n-type diffusion layer 2 using the photoresist 4 as a mask. After this, Figure 2(c)
After removing the photoresist 4, a W film 7 is formed on the n-type diffusion layer 2 of the silicon substrate 1 within the contact window 5, as shown in FIG.
grow. At this time, the surface of the W film 7 and the silicon oxide film 3
The W film 7 is grown to such an extent that the heights of the surfaces of the two surfaces are almost the same. For example, WF, H, and a mixed gas are used as the selected members of the W film 7, and the temperature is about 300°C. lastly,
As shown in FIG. 2(d), the Au arrangement, &! Form 8 and complete.

Problems to be Solved by the Invention In the method of manufacturing a semiconductor device carried out in this manner, there is a problem that the contact area between the W film 7 and the n-type diffusion layer 2 is small, resulting in a high contact resistance. For example, the surface phosphorus concentration of the n-type diffusion layer 2 is IXIO211am-',
When the size of the contact window 5 is 1×1 μm 2 , the contact resistance is approximately 700.

Therefore, in circuits that require contact resistance to be as small as possible, contact resistance is reduced by increasing the area of the contact window, but this has the drawback of increasing chip size.

The present invention solves the above problems, and aims to provide a method for manufacturing a semiconductor device that allows a contact with low electrical resistance to be obtained without increasing the chip size.

Means for Solving the Problems In order to solve the above problems, the present invention includes etching the semiconductor substrate within the contact window to form a groove in the semiconductor substrate through a diffusion layer formed in the semiconductor substrate.
After forming a diffusion layer of the same conductivity type as the diffusion layer in the semiconductor substrate inside the groove of No. 3, a first conductive layer is buried inside the groove, and a second conductive layer is formed on the first conductive layer. It is something to do.

Effect: With the above configuration, the contact area between the diffusion layer of the semiconductor substrate and the first conductive layer increases, so that contact resistance can be reduced.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and will be explained using this.

For simplicity, only the contact portion between the wiring and the board is shown.

As shown in FIG. 1(a), first, a P-type silicon substrate 1
Next, as shown in FIG.
), the silicon oxide film 3 is dry etched using the photoresist 4 as an etching mask. At this time, for example, CHF□/02 is used as the etching gas.
Uses mixed gas. Subsequently, using the photoresist 4 as an etching mask, the silicon substrate 1 is etched to form a contact window 5, which is a groove. As an etching gas for the silicon substrate 1, for example, SF, /C
A CL mixed gas is used. After that, as shown in FIG. 1(c), after removing the photoresist 4 with 02 plasma, heat treatment is performed in, for example, a PH310□ mixed gas to form an n-type silicon substrate 1 within the contact window 5. Next, as shown in FIG. 1(d), W is formed as a first conductive layer in the contact window 5.
Select and grow all7. At this time, the W film 7 is heated to such an extent that the heights of the surface of the W film 7 and the surface of the silicon oxide film 3 are almost the same.
For selective growth of the W film 7, for example, WF
, /H, mixed gas at a temperature of around 300°C. Finally, as shown in FIG. 1(, ), Au wiring 8 as a second conductive layer is formed to complete the process.

According to the above structure, the W film 7 and n
Since the contact area of the type diffusion layers 2 and 6 is clearly increased compared to the conventional method, the contact resistance is definitely reduced. For example, when the depth of the groove is 1 μm, the contact area becomes 5 μm 2 from the conventional 1 μm 2 and the contact resistance becomes about 175 as compared to the conventional one.

Note that Wall or Mo film can be used as the first conductive layer, and AfL can be used as the second conductive layer.

Wiring made of A2 alloy, Cu, Cu alloy, etc. can be used.

Effects of the Invention As described above, according to the present invention, contact resistance can be reduced without increasing chip size.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views showing the conventional manufacturing process. 1...p-type silicon substrate, 2...n-type diffusion layer, 3...
...Silicon oxide film, 5...Contact window (ill)
, 6...n-type diffusion layer, 7...W film (first conductive layer), 8...AM wiring (second conductive layer). Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A step of digging a groove in a semiconductor substrate through a diffusion layer formed on the semiconductor substrate, and a step of forming a diffusion layer of the same conductivity type as the semiconductor diffusion layer in the semiconductor substrate inside the groove,
A method for manufacturing a semiconductor device, comprising the steps of selectively growing a first conductive layer only within the trench, and forming a second conductive layer on the first conductive layer.