JPS61204690A - Scanning circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scan circuit used for addressing of matrix type display devices, solid-state imaging devices, and the like.

[Summary of the invention]

The present invention provides a complementary type scan circuit with a small number of elements for use in matrix display devices, solid-state imaging devices, etc. ICT
It consists of:

[Prior art]

FIG. 7 shows a conventional scan circuit. Figure (α) shows a master-slave type D flip-flop, which forms the basic cell of a conventional scan circuit. <h> in the figure is a shift register constructed using the basic cells 1, 2, 3, and 4 shown in (α) in the figure, and this constitutes a conventional scan circuit. Conventional scan circuits require at least 20 transistors per output, even excluding buffer circuits for driving lines in matrix display devices and the like. Further, as is clear from the figure, two shift register transfer locks, φ and 7, are required.

[Problems and objects to be solved by the invention] In matrix display devices (e.g., active matrix liquid crystal panels provided on a transparent substrate) and solid-state imaging devices, scan circuits can be fabricated on the same substrate using a manufacturing process compatible with pixel elements. The following points are especially important when trying to build on the above.

(+1 Simplify the circuit configuration of the scan circuit,
To reduce the number of components and the area of the active region.

(11) Silicon thin film (for example, polycrystalline silicon).

It is difficult to construct a clock buffer using thin II) transistors made of amorphous silicon (such as amorphous silicon) in terms of driving ability. Therefore, it is desirable that the number of required clocks be small.

An object of the present invention is to provide a scan circuit that satisfies the above two points and is suitable for being constructed on the same substrate as a pixel element.

[Means for solving problems]

As shown in FIG. 1, it consists of at least a P-type FKT11 to which a clock signal is input to the gate, a P-type FET Ti2 to which transferred data is input to the gate, and an N-type FET13 to which a reset signal is input to the gate. A first basic cell, at least an N-type FET 16 to which a clock signal is input to the gate, an N-type FET 15 to which the transferred data is input to the gate, and an N-type FET 15 to which the reset signal is input to the gate. A scan circuit is constituted by a data transfer circuit in which a second basic cell consisting of an FXT 14 is alternately repeated, and decoders 17 to 21 consisting of logic gates based on IPET.

[Effect]

In FIG. 1, the outputs 22-27 of each basic cell are reset to the initial state by a reset signal. Next, the data to be transferred is transferred in synchronization with the clock signal, so that the output of each basic cell is sequentially inverted to a state opposite to the initial state. Further, decoders 17 to 21 detect the inversion edges of each of the basic cells to form scan pulses.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram for explaining the present invention in detail. In the figure, 6 is a clock signal line for inputting a clock signal for data transfer, and 7 is a diagram for setting the scan circuit in an initial state. A reset signal line is used to input a reset signal for resetting, 8 is a data input terminal to be transferred, 9 is a positive power supply line, and 10 is a negative power source line.In addition, a P-type F to which a clock signal is input to the gate. 'FiT11. The first basic cell 30 is constituted by a P-type ?KT12 to which transferred data is input to the gate and an N-type PK'l'13 to which a reset signal is input to the gate.Similarly, a clock signal is input to the gate A second basic cell 31 is constituted by an N-type FET 16 to which data to be transferred is input to the gate, an N-type FET 15 to which the data to be transferred is input to the gate, and a P-type ? , the first basic cell and the second basic cell are alternately repeated, and the output terminals 22 , 25 of each basic cell.

#24.25, 26.27! As shown in Figure 1, it is connected to the input terminals of decoders 17, 18, 19, 20, and 21.

Decoders 17, 19, 21. . . . are AND gates and decoders 18, 20 . . . . is composed of NOR gates. The scan circuit of the present invention shown in FIG. is a thin film transistor (hereinafter abbreviated as TPT) or single crystal MO5FET
It is.

FIG. 3 is a diagram showing another embodiment of the present invention. The figure shows an exclusive OR game as a decoder) 32, 33,
This is a scan circuit constructed using 34, 35, and 36.

Next, the present invention will be explained in detail. In Figure 2, 37
1 is a reset signal, 38 is input data to be transferred, and 39 is a clock signal, which are connected to the reset signal lines 7. and 39 shown in FIG. 1, respectively. Transferred data input terminal 8. Clock signal 1M6
is applied to In Figure 2, 40, 41.42.4
5.44 is the output terminal 22 of each basic cell in FIG.
23. It is a timing diagram showing how the state changes at 24.25.26. At time 49, the reset signal 37 falls to low level, so that the terminal 2
2, 24.26 are low level, terminals 23, 25.27
is initially set to a high level. Next, at time 50, the transferred input data 38 falls to a low level, and at time 51, the clock signal 39 falls, thereby inverting the state of the terminal 22 to a high level.

Further, at time 52, the clock signal rises, and the state of the terminal 25 is inverted to low level. below,
Similarly, in synchronization with the falling and rising edges of the clock signal 39, the terminals 24, 25, 26, 27, . . .
The states of ... are sequentially reversed.

As a result of the above, the output terminal 53.5 of the scan circuit in FIG.
At 4, 56, and 57, scan pulses are sequentially output as shown at 45, 46, 47, and 48.

FIG. 4 is a diagram for explaining the operation of the scan circuit shown in FIG. 3. In Figure 5, each input terminal 6.7
．． 8, signals 39, 57, and 58 are input. This is exactly the same as that explained in FIGS. 1 and 2. Output terminals 65, 64, 65 . of each basic cell. The change in state in ...... is also 68.69, 70. As shown in . . . , this is the same as the above embodiment. At this time, in FIG. 3, the scan circuit outputs 58, 59, 60, 61
．． 62, as shown at 75, 74 and 75, 76 in FIG. 4, so that output pulses with a pulse width twice that of the previous embodiment can be obtained.

In addition, in Fig. 1, Fig. 2, Fig. 3, and Fig. 4, IF
Reverse the ET's PN and reverse the positive and negative of the power supply,
Furthermore, it goes without saying that even if the polarities of the clock signal, reset signal, and input data to be transferred are reversed, this does not go against the spirit of the present invention.

Next, an application example of the present invention will be described.

FIG. 5 shows an example in which the scanning circuit of the present invention is applied to an active matrix liquid crystal display device, which is constructed by providing a TNT array on a transparent substrate and driving a liquid crystal. In the figure, a pixel matrix 77 is composed of a TFT 7B, a liquid crystal cell 9, and the like. Further, reference numeral 80 denotes a scan circuit of the present invention, which operates to sequentially select the analog switch array 81 using TIFT and take in image data from the image data input terminal 82 into the pixel matrix 77. On the other hand, 85 is also a scan circuit of the present invention, which sequentially selects the scan lines 84 in the pixel matrix. Here, the scan circuits 80 and 85 are provided on the same substrate as the pixel matrix 77.

FIG. 6 is a diagram showing a cross-sectional structure of the active matrix substrate of FIG. 5. In FIG. 6, 85 is a transparent substrate, 86 is a first silicon thin film, 87 is a gate insulating film, 88 is a second silicon thin film, 89 is an interlayer insulating film, 90 is a pixel electrode and A transparent conductive film that forms wiring. In addition, 91 is an N type (P type) TUF in the pixel matrix.
92 and 93 indicate a P-type (N-type) TIPT and an N-type (P-type) TIFT that constitute a scan circuit.

[Effects of the Invention] The scan circuit of the present invention has the following features including the decoder.
The number of components per bit is extremely small, about 10 FETs, and only one lock is required for data transfer, and an inverted clock is not required.

For this reason, the scan circuit can be formed in a small area, making it possible to achieve high yields and low costs when the scan circuit is built on the same substrate as the pixel elements of IJ display devices and solid-state imaging devices. can be guaranteed.

In addition, because only one clock is required, T? Suitable for forming a scan circuit with T.

Further, since the operation of the data transfer circuit of the scan circuit of the present invention is a dynamic operation in which charge is stored in a capacitor and the state is maintained, there is no through current and the power consumption is extremely low.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention. FIG. 2 is a timing diagram of a scan circuit for explaining the operation of the embodiment of FIG. 1. FIG. 3 is a configuration diagram showing another embodiment of the present invention. Figure 4 shows #! FIG. 4 is a timing diagram for explaining the operation of the embodiment shown in FIG. 3; FIG. 5 is a configuration diagram showing an example of application of the present invention. FIG. 6 is a sectional view of FIG. 5. FIGS. 7(α) and 7(b) are conventional scan circuit diagrams. that's all

Claims (2)

[Claims] (1) In a scan circuit configured with FETs and which transfers data to be transferred in synchronization with a clock signal, at least a P-type FET in which the clock signal is input to the gate
ET and a P-type FET into which the transferred data is input to the gate.
and an N-type FET to which a reset signal is input to the gate; at least an N-type FET to which the clock signal is input to the gate; and an N-type FET to which the transferred data is input to the gate. and a second basic cell consisting of a P-type FET whose gate receives a reset signal, and the first basic cell and the second basic cell are alternately repeated. A scan circuit characterized by consisting of a circuit. (2) The P-type FET and the N-type FET are thin film transistors, and the scan circuit is formed on the same substrate as a thin film transistor array in an active matrix liquid crystal panel. The scan circuit according to item 1.