JPS61202472A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61202472A JPS61202472A JP4407885A JP4407885A JPS61202472A JP S61202472 A JPS61202472 A JP S61202472A JP 4407885 A JP4407885 A JP 4407885A JP 4407885 A JP4407885 A JP 4407885A JP S61202472 A JPS61202472 A JP S61202472A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- region
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000007772 electrode material Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000010884 ion-beam technique Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- -1 hydrogen ions Chemical class 0.000 abstract description 11
- 150000002500 ions Chemical class 0.000 abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 9
- 239000001257 hydrogen Substances 0.000 abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 6
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 22
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 11
- 229910052786 argon Inorganic materials 0.000 description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 8
- 230000001133 acceleration Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000001994 activation Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000004691 decahydrates Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- SYHGEUNFJIGTRX-UHFFFAOYSA-N methylenedioxypyrovalerone Chemical compound C=1C=C2OCOC2=CC=1C(=O)C(CCC)N1CCCC1 SYHGEUNFJIGTRX-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果型トランジスタ等の半導体装置の製造
方法に係り、特にサブミクロン・オーダの短ゲート長を
有するゲート電極の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device such as a field effect transistor, and particularly to a method of forming a gate electrode having a short gate length on the order of submicrons.
大規模な計算機能を持つ電子計算機にはシリコンに比べ
て動作速度が大幅に向上されるガリウム砒素電界効果ト
ランジスタ（ＧａＡｓＦＢＴ）が用いられる。Gallium arsenide field effect transistors (GaAsFBTs) are used in electronic computers with large-scale calculation functions, as their operating speed is significantly improved compared to silicon.
かかる電子計算機においてその計算規模は益々増大する
傾向にあり、これに伴ってＧａＡｓ ＦＥＴに対し一層
の速度向上が期待されており、そのためにサブミクロン
・オーダの短ゲート長を有するゲート電極が容易に且つ
安定に形成出来るゲート電極の形成技術が要望されてい
る。The scale of calculations in such electronic computers tends to increase more and more, and as a result, it is expected that the speed of GaAs FETs will further improve, and gate electrodes with short gate lengths on the order of submicrons can be easily fabricated. There is a need for a technology for forming gate electrodes that can be formed stably.
従来ＧａＡｓＦＢＴにおけるゲート電極は、第２図（ａ
ｌ乃至（ｇ）に示す工程断面図を用いて以下に説明する
方法により形成されていた。The gate electrode in a conventional GaAs FBT is shown in Figure 2 (a
It was formed by the method described below using the process cross-sectional views shown in (1) to (g).
即ち先ず第２図（ａ）に示すように、半絶縁性ＧａＡｓ
基板１の表面部に図示しないレジスト・マスクを介して
イオン注入法によりｎ型チャネル層２を形成する。That is, first, as shown in FIG. 2(a), semi-insulating GaAs
An n-type channel layer 2 is formed on the surface of the substrate 1 by ion implantation through a resist mask (not shown).
次いで第２図（ｂｌに示すように、上記ＧａＡｓ基板１
上にゲート電極材料膜である例えば厚さ４０００人程度
０タングステンシリサイド（ＷＳｉ、）膜３を形成する
。Next, as shown in FIG. 2 (bl), the GaAs substrate 1
A tungsten silicide (WSi) film 3, which is a gate electrode material film, is formed thereon to a thickness of, for example, about 4,000.
次いで第２図（Ｃ）に示すように、上記ＷＳｉｘ膜３上
に厚さ５０００〜６０００人程度の二酸化シリコン（Ｓ
ｉＯ２）膜４を形成し、次いでこのＳｉｎｇ膜４上に厚
さ０゜８μｍ程度のレジスト膜５を形成する。ここでＳ
ｉＯ□膜４はＷ Ｓ ｉ、膜３をパターンニングする際
のマスクになる膜である。Next, as shown in FIG. 2(C), silicon dioxide (S
iO2) film 4 is formed, and then a resist film 5 with a thickness of about 0.8 μm is formed on this Sing film 4. Here S
The iO□ film 4 is a film that serves as a mask when patterning the W Si film 3.
次いで第２図（ｄ）に示すように、電子ビーム露光及び
現像を行ってレジスト・パターン１０５を形成する。Next, as shown in FIG. 2(d), electron beam exposure and development are performed to form a resist pattern 105.
次いで第２図（ｅ）に示すように、上記レジスト・パタ
ーン１０５をマスクにし三弗化メタン（ＣＨｈ）等のエ
ツチング・ガスを用いるリアクティブ・イオンエツチン
グ（ＲＩ Ｅ）処理によりＳｉＯ□パターン１０４を形
成する。Next, as shown in FIG. 2(e), the SiO□ pattern 104 is etched by reactive ion etching (RIE) using an etching gas such as trifluoromethane (CHh) using the resist pattern 105 as a mask. Form.
次いで第２図（ｆｌに示すように、レジスト・パターン
１０５を除去した後（除去しない場合もある）、上記Ｓ
ｉ０ｇパターン１０４をマスクにし四弗化炭素（ＣＦ４
）十酸素（０，）よりなるエツチング・ガスを用いるＲ
ＩＥ処理によりＷＳｉｘ膜３をパターンニングし、Ｓｉ
ｎ、パターン１０４を除去してＷ Ｓ ｉ ｘゲート電
極１０３を完成させる方法であった。Next, as shown in FIG. 2 (fl), after removing the resist pattern 105 (in some cases it may not be removed), the above S
Using the i0g pattern 104 as a mask, carbon tetrafluoride (CF4
) R using an etching gas consisting of ten oxygen (0,)
The WSix film 3 is patterned by IE processing, and Si
n, the pattern 104 was removed to complete the WSi x gate electrode 103.
なおＦＥＴは、この後第２図（ｇ）に示すように、上記
ＷＳｉＸゲート電極１０３をマスクにしシリコン（Ｓｉ
）をイオン注入し、所望の活性化処理を行ってゲート電
極１０３に自己整合したキャリア濃度１０１１１ｅ１１
” ’程度のｎ″″型ソース領域６及びｎ＋型ドレイ
ン領域７を形成し、ソース領域６及びドレイン領域７上
に金ゲルマニウム（ＡｕＧｅ） ／金（Ａｕ）よりなる
電極８及び９を形成して完成する。As shown in FIG. 2(g), the FET is then fabricated using silicon (SiX) using the WSiX gate electrode 103 as a mask.
) is ion-implanted, and a desired activation process is performed to obtain a carrier concentration 10111e11 that is self-aligned to the gate electrode 103.
An n-type source region 6 and an n+-type drain region 7 of about "" are formed, and electrodes 8 and 9 made of gold germanium (AuGe)/gold (Au) are formed on the source region 6 and drain region 7. Complete.
然しなから上記のようにレジスト・パターンをマスクに
してゲート電極のパターンニングを行う従来の方法にお
いては、レジスト膜に露光を行う際の電子ビームの内部
散乱や、現像に際しての膨潤によって、レジスト・パタ
ーンに横方向の拡がりを生ずるために、０．５μｍ以下
のサブミクロン寸法のゲート長を有するゲート電極を形
成することが極めて困難であるという問題があった。However, in the conventional method of patterning the gate electrode using the resist pattern as a mask as described above, the resist film is damaged due to internal scattering of the electron beam when exposing the resist film and swelling during development. There is a problem in that it is extremely difficult to form a gate electrode having a submicron gate length of 0.5 μm or less because the pattern spreads in the lateral direction.
上記問題点は、半導体基板上にゲート電極材料膜を形成
し、該ゲート電極材料膜上に絶縁膜を形成し、該絶縁膜
に選択的にイオンビームを照射した後、該絶縁膜のエツ
チングを行って該絶縁膜のイオンビーム照射されなかっ
た領域を選択的に除去し、該絶縁膜の残留パターンをマ
スクにして該ゲート電極材料膜の選択エツチングを行う
工程を有する本発明による半導体装置の製造方法によっ
て解決される。The above problem is solved by forming a gate electrode material film on a semiconductor substrate, forming an insulating film on the gate electrode material film, selectively irradiating the insulating film with an ion beam, and then etching the insulating film. manufacturing a semiconductor device according to the present invention, comprising the step of: selectively removing a region of the insulating film that has not been irradiated with the ion beam; and selectively etching the gate electrode material film using the remaining pattern of the insulating film as a mask; Solved by method.
本発明の方法は絶縁膜に水素やアルゴン等のイオンを注
入すると、絶縁膜のエツチング・レートが減少するとい
う実験結果に基づいてなされたものである。The method of the present invention was developed based on the experimental result that the etching rate of the insulating film is reduced when ions such as hydrogen or argon are implanted into the insulating film.
第３図及び第４図はその実験結果を示すイオン注入量と
エツチング・レートの相関図で、第３図は注入イオンに
水素を用いた場合を、また第４図は注入イオンにアルゴ
ンを用いた場合を示している。なお注入エネルギーは水
素イオンの場合ＥＨ＝ １００ＫｅＶ 、アルゴン・イ
オン場合Ｅ ａ−＝ １５０ＫｅＶである。また第３図
におけるエツチング液には弗酸（ＨＰ）十水（ＨｚＯ）
＝ １ ： １０の混液を、第４図におけるエツチン
グ液にはＨＦ＋ＨｚＯ＝ １ ： ２０の混液を用いた
。また図中、Ｎｏ ＋ Ｍａｒはそれぞれのイオンの注
入量を示す。Figures 3 and 4 are correlation diagrams of the ion implantation amount and etching rate showing the experimental results. Figure 3 shows the case where hydrogen was used as the implanted ions, and Figure 4 shows the case where argon was used as the implanted ions. This shows the case where Note that the implantation energy is EH = 100 KeV for hydrogen ions, and E a - = 150 KeV for argon ions. In addition, the etching solution in Fig. 3 contains hydrofluoric acid (HP) and decahydrate (HzO).
A mixed solution of HF+HzO=1:10 was used as the etching solution in FIG. 4, and a mixed solution of HF+HzO=1:20 was used as the etching solution in FIG. Further, in the figure, No + Mar indicates the amount of each ion implanted.
これらの図は、イオン注入がなされないＳｉ０ｇ膜は０
．２μｍ／分程度のエツチング・レートを示すのに対し
て、’ｌ ＸＩＱＩ＆ａｍ−”程度水素イオンが注入さ
れた５ｉＯ１膜は０，１１μｍ／分程度に、また同程度
にアルゴン・イオンが注入されたＳｉｎ、膜は０．０１
５μｍ／分程度にそれぞれエツチング・レートが減少す
ることを示している。These figures show that the Si0g film without ion implantation is 0
．． While the etching rate of the 5iO1 film implanted with hydrogen ions to the extent of 'l , the membrane is 0.01
It is shown that the etching rate decreases to about 5 μm/min.
上記実験結果から本発明の方法においては、ゲート電極
材料膜上に絶縁膜を設け、この絶縁膜のゲート電極パタ
ーンに対応する領域に選択的に集束イオンビーム走査に
よりイオン注入を行い、これによってその部分だけエツ
チング・レートを減少せしめた後、この絶縁膜の全面エ
ツチング処理を行って、上記ゲート電極パターンに対応
し、エツチング・レートの減少せしめられている絶縁膜
のイオン注入領域を選択的に残留させ、この残留 □
絶縁膜パターンをマスクにしゲート電極材料膜の選択エ
ツチングを行いゲート電極を形成するものである。Based on the above experimental results, in the method of the present invention, an insulating film is provided on the gate electrode material film, and ions are selectively implanted into the region of the insulating film corresponding to the gate electrode pattern by focused ion beam scanning. After reducing the etching rate in only a portion of the insulating film, etching is performed on the entire surface of the insulating film to selectively leave the ion-implanted region of the insulating film where the etching rate has been reduced, corresponding to the gate electrode pattern described above. Let this residual □
The gate electrode is formed by selectively etching the gate electrode material film using the insulating film pattern as a mask.
集束イオンビーム走査によるイオン注入において注入領
域の横方向の拡がりは高々５００〜１００００程度で、
且つその拡がり幅もイオンの種類及び加速エネルギーに
よって定まるので、本発明の方法によれば０．２〜０．
５μｍ程度のサブミクロン寸法のゲート長を有するゲー
ト電極が、容易に且つ均一に形成出来る効果を生ずる。In ion implantation using focused ion beam scanning, the lateral extent of the implanted region is approximately 500 to 10,000 at most.
In addition, the width of the spread is also determined by the type of ion and the acceleration energy, so according to the method of the present invention, the width is 0.2 to 0.
A gate electrode having a submicron gate length of about 5 μm can be easily and uniformly formed.
そして又、本発明の方法によればレジスト・プロセスが
省略出来るので工程も簡略化される。Furthermore, according to the method of the present invention, the resist process can be omitted, so the process is also simplified.
以下本発明を、第１図（ａｌ乃至＜ｒｒに示す一実施例
の工程断面図、及び第３図に示す水素イオン注入量とＳ
ｉ０ｇ膜のエツチング・レートとの相関図、第４図に示
すアルゴン・イオン注入量とＳｉＯ，ｌｉミノエツチン
グレートとの相関図を用い、具体的に説明する。The present invention will be described below with reference to FIG. 1 (a process cross-sectional view of an embodiment shown in al to
A detailed explanation will be given using a correlation diagram between the etching rate of the i0g film and a correlation diagram between the argon ion implantation amount and the SiO, Li mino-etching rate shown in FIG.
なお企図を通じ同一対象物は同一符号で示す。The same objects are indicated by the same symbols throughout the plan.
本発明の方法を用いて例えばＧａＡｓＦＥＴを形成する
に際しては、
先ず第１図（ａＪに示すように、半絶縁性ＧａＡＳ基板
１の所定領域に図示しないレジスト・マスクを介して選
択的にＳｔをイオン注入し、所定の活性化処理を行い、
キャリア濃度Ｉ Ｑ ” ａｍ−’ 、深さ５００〜１
０００人程度のｎ型チャネル層２を形成する。When forming, for example, a GaAsFET using the method of the present invention, first, as shown in FIG. injection, perform the prescribed activation process,
Carrier concentration IQ "am-', depth 500~1
An n-type channel layer 2 of about 1,000 layers is formed.
次いで第１図（ｂ）に示すように、ゲート電極材料であ
る上記ＧａＡｓ基板１上にスパッタリング法により厚さ
４０００人程度０Ｗ Ｓ ｉ、膜３を形成する。Next, as shown in FIG. 1(b), a film 3 having a thickness of about 4,000 0W Si is formed on the GaAs substrate 1, which is a gate electrode material, by sputtering.
以上は従来方法と同じである。The above is the same as the conventional method.
次いで本発明の方法においては第１図（Ｃ）に示すよう
に、上記Ｗ Ｓ ｉ 、を膜３上に化学気相成長（ＣＶ
Ｄ）法により例えば厚さ９０００人程度０ＳｉＯ□膜１
０膜形０する。Next, in the method of the present invention, as shown in FIG.
D) For example, a 0SiO□ film 1 with a thickness of about 9000
0 film form 0.
ここでＳｉｎ、膜１０の厚さは後工程で注入されるイオ
ンの種類によって変えられ、上記厚さは水素イオン（Ｈ
＋）注入、即ちプロトン注入に適した値である。Here, the thickness of the Sin film 10 is changed depending on the type of ions implanted in a later process, and the above thickness is hydrogen ion (H).
+) injection, that is, a value suitable for proton injection.
（アルゴン・イオンＡ ｒ ＋を用いる際には４５００
人程度０厚さにする）
次いで第１図（ｄ）に示すように、上記Ｓｉｎ、膜１０
のゲート電極に対応する領域上を、例えば加速エネルギ
ー１００ＫｅＶ 、電流１００ｐＡ、ビーム・スポット
径０．１μｍの集束水素イオン・ビーム■ＢＨによって
６ Ｘｌ０−”ａｍ／ｓｅｅ程度の走査速度で一回走査
し、この領域のＳｉｎ、膜１０内に２ ＸＩＯｌｔｈａ
ｍ−”ａｔｏ＋程度の水素イオン（Ｈ＋）を注入する。(4500 when using argon ion A r +
Then, as shown in FIG. 1(d), the above-mentioned Sin, film 10
For example, a focused hydrogen ion beam BH with an acceleration energy of 100 KeV, a current of 100 pA, and a beam spot diameter of 0.1 μm is scanned once over the region corresponding to the gate electrode at a scanning speed of about 6 Xl0-” am/see. , Sin in this region, 2 XIOltha in the film 10
Hydrogen ions (H+) of about m-"ato+ are implanted.
この際５ｔ（ｈ膜１０内でのＨ＋の横方向の拡がりは約
０．１μｍ程度であるので、ＳｉＯ□膜１０内には幅０
．３μｍ程度の高濃度のＨ１注入領域１１が形成される
。At this time, since the lateral spread of H+ within the 5t (h film 10 is approximately 0.1 μm, there is no width within the SiO□ film 10).
．． A high concentration H1 implantation region 11 of about 3 μm is formed.
また拡がり寸法はイオンの種類と加速エネルギーによっ
て規定されるので、一定に抑えることは極めて容易であ
る。Further, since the spread size is determined by the type of ion and the acceleration energy, it is extremely easy to keep it constant.
（上記イオン注入をアルゴン・イオンＡｒ“を用いて行
えば、上記横方向の拡がりは０．０５μｍ程度に抑えら
れるので、幅０．２μｍ程度のイオン注入領域が形成で
きる。但しこの場合ＳｉＯ２膜１０の厚さは前述したよ
うに４５００人程度０厚、注入条件は加速エネルギー１
５０ＫｅＶ、電流１００ｐＡ、ビーム・スポット径０．
１μｍ、走査速度６ ＸＩＱ−”ａｍ／ｓｅｅ程度とす
る。）
次いで第１図（ｅ）に示すように、前記ＨＦ：Ｈ２０＝
１：１０の混液でウェット・エツチングを行って、上記
イオン注入の行われていない領域の５ｉｎｔ膜１０が完
全に除去されこの領域のＷ Ｓ ｉ、膜３を表出させる
。このエツチングが完了した時点でＷＳｉＸ膜３上には
、Ｈ３の注入によってエツチング・レートが減少せしめ
られた０、３μｍ程度の均一な幅を有する厚さ４０００
人程度０Ｗゲート電極パターンに対応するＳｉＯ□・パ
ターン１１１が残留する。(If the above ion implantation is performed using argon ions Ar, the lateral spread can be suppressed to about 0.05 μm, so an ion implantation region with a width of about 0.2 μm can be formed. However, in this case, the SiO2 film 10 As mentioned above, the thickness is about 4500 mm, and the implantation conditions are acceleration energy 1
50KeV, current 100pA, beam spot diameter 0.
1 μm and a scanning speed of about 6 XIQ-”am/see.) Next, as shown in FIG.
Wet etching is performed using a 1:10 mixed solution to completely remove the 5-inch film 10 in the region where the ion implantation has not been performed, and expose the W Si and film 3 in this region. When this etching is completed, the WSiX film 3 has a thickness of 4000 mm with a uniform width of about 0.3 μm, whose etching rate has been reduced by implanting H3.
A SiO□ pattern 111 corresponding to a 0W gate electrode pattern remains.
（前工程でアルゴン・イオンＡｒ″−を用いた場合は、
幅０．２μｍ程度の５ｉｆｔ・パターン１１１が残留す
る。）
なお第３図の実験結果によれば、イオン注入がなされな
いＳｉＯ□膜のエツチング・レートは２μｍ／分程度で
あるので上記エツチング時間は約４．５分程度となる。(If argon ion Ar''- is used in the previous step,
A 5ift pattern 111 with a width of about 0.2 μm remains. According to the experimental results shown in FIG. 3, the etching rate of the SiO□ film without ion implantation is about 2 μm/min, so the etching time is about 4.5 minutes.
（アルゴン・イオンＡｒ＋注入を用いる場合も同様であ
る）
次いで第１図（ｆ）に示すように、上記Ｓｉｎｇ・パタ
ーン１１１をマスクにし、ＣＦ４ ＋Ｑ、ガスを用いる
ＲＩＥ処理によりＷ Ｓ ｉ 、膜３を選択エツチング
する。(The same applies when argon ion Ar+ implantation is used.) Next, as shown in FIG. 1(f), using the Sing pattern 111 as a mask, W Si and film 3 are removed by RIE processing using CF4 +Q gas. Select and etch.
これにより０．３μｍ程度のゲート長を有するＷ Ｓ
ｉ、ゲート電極１０３が均一に形成される。As a result, W S with a gate length of about 0.3 μm
i. The gate electrode 103 is uniformly formed.
（アルゴン・イオンＡｒ＋を用いた場合はゲート長０．
２μｍ程度のゲート電極１０３が均一に形成される。）
ここで、本発明の方法によるサブミクロン寸法のゲート
長を有するゲート電極１０３の形成が完了する。(When using argon ion Ar+, the gate length is 0.
A gate electrode 103 of about 2 μm is uniformly formed. ) Here, the formation of the gate electrode 103 having a submicron gate length by the method of the present invention is completed.
以後第１図（ｇ）に示すように、従来通りの方法により
、ゲート電極３に整合してｎ゛型ソース領域６及びｎ゛
型ドレイン領域７を形成し、ソース電極８及びドレイン
電橋９を形成してＧａＡｓＦＥＴが完成する。Thereafter, as shown in FIG. 1(g), an n'-type source region 6 and an n'-type drain region 7 are formed in alignment with the gate electrode 3 by a conventional method, and a source electrode 8 and a drain bridge 9 are formed. is formed to complete the GaAsFET.
なお本発明の方法におけるエツチング・マスク用の絶縁
膜は、上記実施例に示すＳｉＯ２膜に限られるものでは
なく例えばＳｉＪ＊膜等も使用でき、ゲート電極材料も
上記Ｗ Ｓ ｉ ｘ膜に限られない。Note that the insulating film for the etching mask in the method of the present invention is not limited to the SiO2 film shown in the above embodiments, and for example, a SiJ* film can also be used, and the gate electrode material is also not limited to the above W Si x film. do not have.
また本発明の方法は上記実施例に示すＧａＡｓＦＥＴ以
外の電界効果トランジスタにも勿論適用される。Furthermore, the method of the present invention can of course be applied to field effect transistors other than the GaAsFET shown in the above embodiments.
以上説明のように本発明の方法によれば、０．２〜０．
５μｍ程度のサブミクロン寸法のゲート長を有するゲー
ト電極が、容易に且つ均一に形成出来るので、ＧａＡｓ
ＦＥＴ等の半導体装置の動作速度を向上し、且つ特性が
均一化する。As explained above, according to the method of the present invention, 0.2 to 0.
Since a gate electrode having a submicron gate length of approximately 5 μm can be formed easily and uniformly, GaAs
The operating speed of semiconductor devices such as FETs is improved and the characteristics are made uniform.
またレジスト・プロセスが省略されるので、製造効率が
向上する。Furthermore, since a resist process is omitted, manufacturing efficiency is improved.
第１図（ａｌ乃至（＆は本発明のゲート電極形成方法に
おける一実施例の工程断面図、
第２図（ａｌ乃至（勢は従来方法の工程断面図、第３図
は水素イオン注入量と二酸化シリコン膜のエツチング・
レートとの相関図、
第４図はアルゴン・イオン注入量と二酸化シリコン膜の
エツチング・レートの相関図である。
図において、
１は半絶縁性ＧａＡｓ基板、
３はタングステン・シリサイド層、
１０は二酸化シリコン膜、
１１は水素イオン注入領域、
１０３はタングステンシリサイドゲート電極１１１は二
酸化シリコン・パターン、
を示す。Figure 1 (al to (&) is a process cross-sectional view of one embodiment of the gate electrode forming method of the present invention, Figure 2 (al to (&) is a process cross-sectional view of a conventional method, and Figure 3 is a hydrogen ion implantation amount and Etching of silicon dioxide film
Figure 4 is a diagram showing the correlation between the amount of argon ions implanted and the etching rate of the silicon dioxide film. In the figure, 1 is a semi-insulating GaAs substrate, 3 is a tungsten silicide layer, 10 is a silicon dioxide film, 11 is a hydrogen ion implantation region, and 103 is a tungsten silicide gate electrode 111 which is a silicon dioxide pattern.
Claims (1)
極材料膜上に絶縁膜を形成し、該絶縁膜に選択的にイオ
ンビームを照射した後、該絶縁膜のエッチングを行って
該絶縁膜のイオンビーム照射されなかった領域を選択的
に除去し、該絶縁膜の残留パターンをマスクにして該ゲ
ート電極材料膜の選択エッチングを行う工程を有するこ
とを特徴とする半導体装置の製造方法。A gate electrode material film is formed on a semiconductor substrate, an insulating film is formed on the gate electrode material film, the insulating film is selectively irradiated with an ion beam, and the insulating film is etched to remove the insulating film. 1. A method of manufacturing a semiconductor device, comprising the steps of selectively removing a region not irradiated with an ion beam, and selectively etching the gate electrode material film using the remaining pattern of the insulating film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4407885A JPS61202472A (en) | 1985-03-06 | 1985-03-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4407885A JPS61202472A (en) | 1985-03-06 | 1985-03-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61202472A true JPS61202472A (en) | 1986-09-08 |
Family
ID=12681585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4407885A Pending JPS61202472A (en) | 1985-03-06 | 1985-03-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61202472A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06310491A (en) * | 1993-04-27 | 1994-11-04 | Nec Corp | Forming method for pattern on solid surface |
-
1985
- 1985-03-06 JP JP4407885A patent/JPS61202472A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06310491A (en) * | 1993-04-27 | 1994-11-04 | Nec Corp | Forming method for pattern on solid surface |
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