JPS61201343A - Method and device for controlling test pattern generation - Google Patents

Abstract

PURPOSE:To generates test patterns for devices to be tested at a high speed with small memory capacity by classifying the test patterns by kinds and accessing them independently. CONSTITUTION:The test patterns are classified by the kinds into scan patterns and primary patterns and stored previously in a pattern memory 17 by the kinds in the order of use during storage. Then, instructions are read out of addresses of a test sequence memory 11 under the control of a control part 13 and outputted to an address arithmetic part 12. The arithmetic part 12 generates information for specifying readout addresses of the pattern memory 17 by said instructions and accesses the pattern memory 17 independently by the kinds of the test patterns according to the generation order of the test patterns. Consequently, the test patterns generated by combining the scan patterns and primary patterns successively are obtained.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention efficiently generates various test pattern data for performing functional tests of large-scale logic circuits with complex functions by dividing them using a test pattern memory with a small capacity. The present invention relates to a test pattern generation control method and device.

[Background of the invention]

Conventionally, as a test pattern generation control method for efficiently generating test patterns using a test pattern memory with a small capacity, a method described in Japanese Patent Publication No. 54-39702, for example, is known. The conventional method shown here divides the test pattern memory corresponding to a plurality of input/output bins of the logic circuit under test, and independently and randomly accesses each divided memory to obtain a specified memory pattern. A test pattern is generated by the combination of However, this method performs memory partitioning corresponding to input/output bins, and does not recognize how to efficiently use the classification according to the type of test pattern, its storage order, and the time element of occurrence. Furthermore, no consideration is given to efficient and specific hardware means for generating straight patterns such as scan patterns and primary patterns depending on the type of test pattern.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an easy-to-control test pattern generation control method and apparatus that effectively stores a large number of test patterns in a test pattern memory and generates them efficiently. .

[Summary of the invention]

The present invention classifies test patterns into scan patterns (scan-in patterns and scan-out patterns) and primary patterns (primary input cover turns and primary output cover turns) according to the type of test patterns in a divided functional test of a device under test. Control information that identifies the type of test pattern is stored in advance in the order used during testing in dedicated or divided pattern memories (blocks) designated for each type of pattern, and in pattern generation sequence information that indicates the order in which test patterns are generated. This test generates a test pattern that sequentially combines the scan pattern and the primary pattern by independently accessing the pattern memory (block) for each type of test pattern according to the order in which the test patterns are generated using this information. A method and apparatus for controlling pattern generation.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 7, in comparison with a conventional method for testing a scan path type device.

First, FIG. 3 is a divided circuit diagram illustrating a scan path type test device to which an embodiment of the test pattern generation control method and apparatus according to the present invention is applied. In Fig. 3, the scanpath type device DUT generally has a circuit configuration that allows direct access to all storage devices (flip-flops F/'F) in a VLSI etc., and one of the methods for realizing this is shown in Fig. 1. F/F t
-F1 to F6 are connected in series to form a shift register configuration, so that the internal combinational logic circuit can be
It is possible to test by dividing into 3 sections.

Testing of such a scanpath-based device can be accomplished by the following steps. First, to test the shift register, apply a test pattern to the scan in bin SI, and
The normal operation of the shift register is confirmed by observing the test result in the scan out bin SO via F1 to F6. Next, the internal combinational logic circuit 1 is tested by applying a test pattern to the primary input bins PI (PII to PI3), and applying the test results of the combinational logic circuit 1 to the F2. It is taken in to F3 and taken out to the scan out bin SO via the shift register for observation.

Next, the test of the combinational logic circuit 2 is performed by inputting a test pattern from the scan-in bin SI to its inputs F1 to F3 of the current block using a shift register, and then transmitting the test results of the combinational logic circuit 2 to its inputs F1 to F3 of the current block φ. The data is taken into F6 and taken out to the scan-out bin SO via the shift register for observation. Next, the test of the combinational logic circuit 3 is performed at F4. A test pattern is input to F5 using the scan-in bin SI and a shift register, and the test result of the combinational logic circuit 3 is immediately observed at the primary output bin PO. Combinational logic circuit 1 surrounded by storage devices (F/F) in this way
- The internal circuit composed of 3 is fully independently taken out partially and 4
You can split it and test it.

FIG. 4 is an explanatory diagram showing one method of storing the test pattern of the scan path type test device divided into four as described above in FIG. 3 in the pattern memory. In FIG. 4, the test pattern of the device divided into four parts in FIG. ,
Test patterns (1) to (4) of diagonal lines and dots for shift register test and combinational logic circuit 1 to 3 tests
' are sequentially stored at memory address O-29.

This pattern memory 17 is designated as a memory address when each test pattern is generated to generate a test pattern, and this is applied to the scan-in pin SI and the primary input bin PI to obtain the output data of the scan-out pin SO and the primary output bin PO. The expected value patterns (1)'-(4)' of the scan out pin SO and the primary output pin PO stored in the pattern memory 17 are compared and determined using a tester. The test turn data stored in the pattern memory 17 in this way is @1# or @O#.
The data in the white part is not used during testing and is usually initialized data. Further, FIG. 5 is an explanatory diagram showing the address designation (generation) order (steps) for generating the test pattern of the pattern memory shown in FIG. 4. In FIG. 5, if we focus on the address designation given to the pattern memory 17 to generate the test pattern from the pattern memory 17 in FIG. Since only sequential access is required, address control for test pattern generation becomes easy. However, the pattern vector in Fig. 4, that is, the pattern depth x the number of bins n = 30 As the number of test patterns increases, a huge amount of memory is required, and the amount of memory that is not used effectively increases. Therefore, according to the present invention, the following method of sequentially storing each type of test pattern is used.

FIG. 6 is an explanatory diagram illustrating a method of sequentially storing each type of test pattern in a pattern memory in an embodiment of the test pattern generation control method and apparatus according to the present invention. In FIG. 6, a scan-in pin SI and a scan-out pin S are stored in the pattern memory 17 for each type of pattern.
O and primary input bin PI and primary output bin PO
The test patterns (11 to (4)') are sequentially stored in memory addresses O to 13 in the order of use, etc. FIG. 7 shows the address designation (generation) order for generating the test patterns in the pattern memory of FIG. (step).In FIG. 7, the pattern memory 1 of FIG.
Address specifications read from 7 are scan-in pin SI test pattern (1), scan-out pin SO test pattern (1)', primary human mold 7PI test pattern (2), and scan-out pin SO test pattern (2). Scan-in pin SI test pattern (
3) and scanout pin SO test pattern (31
', the scan-in pin SI test pattern (4), and the primary output bin PO test pattern (4), if generated by a pattern processor etc. according to the test sequence program in this order, the test pattern according to Figs. 4 and 5 will be generated. Equivalent test patterns can be generated.As the number of stages of the shift register in the test device (VLSI) shown in Fig. 3 increases, the number of scan test patterns for scan-in pin SI and scan-out pin SO increases. Memory can be dedicated for 17 scan test patterns.

FIG. 1 is a circuit diagram showing an embodiment of the test pattern generation control device according to the present invention, in which test patterns are generated in the order shown in FIG. This shows the circuit configuration. In Figure 1, 10
11 is a program counter; 11 is a test sequence memory in which sequence information (order information) for test pattern generation is provided with address control information for identifying the type of test pattern; 12 is an address calculation unit; 13 is an address control unit;
4-1 is a scan in bin SI address register, 14
-2 is the scanout bin SO address register, 14
-3 is the primary input bin PI address register, 14
-4 is the primary output pin PO address register, 15
1 is an address register selector, 16-1 to 16-4 are write controllers for each address register, and 17 is the same pattern memory as in FIG.

In this configuration, in the initial state, the program counter 10, address calculation section 12, and address registers 14-1 to 14
-4 all indicate address 0. Also, a register selector 15 that selects address registers 14-1 to 14-4 in advance.
The use settings of the address registers 14-1 to 14-4 are made by the following. At the start of pattern generation, the sequence information of address O in the test sequence memory 11 is NOP.
(No 0operation) and address control information LDA @ SI (Load Address '1
3. The address 0 that specifies the read address of the pattern memory 17 is loaded into the address calculation section by the (for 5 can-in Memory) command, and the S operation information is converted into a signal that selects the S air address register 14-1 in the control unit 13. Then, the write controller 16-1 sends a write clock signal to the S air address register 14-1, and the address O is written to the S air address register 14-1. In addition, other address registers 14-2 to 14-14
Since the write clock signal is not passed through -4, the initial value is address O. Above SI airless register 1
4-1, the pattern memory section (of the scan-in bin SI of the pattern memory 17) is
A scan-in pattern (initialized with the test pattern of FIG. 6) stored in address 0 of the memory block (Memory Block) is generated and applied to the scan-in bin SI of the device DUT of FIG. At this time, in accordance with the NOP command, the control unit 13 increments the program counter lOi+1 by the next clock signal and instructs the address 1 of the test sequence memory 11.

In this step, the sequence information of address 1 in the test sequence memory 11 is
mes ) and address control information INCA (Inc
rementAddress) instruction, this instruction sets the S air address register 14 set in the previous step.
-1, the address of the pattern memory 13 is given to the controller 1 while incrementing it by +1 five times.
3 instructs the program counter 10 to hold address 1, and the address calculation unit 12 uses the INCA instruction to hold address 1.
The address O loaded in the previous step is incremented by +1 and the completion of the process is notified to the counter in the control unit 13, thereby decrementing the value 5 of the counter loaded by the REP5 instruction by 1. At the same time, the address 1 incremented by the arithmetic unit 12 is similarly written to the S air address register 14-1, a scan pattern in address 1 of the pattern memory 17 is generated, and the device DU
Output to T. By repeating the above operation five times (for five clock signals), scan-in patterns at addresses 1 to 5 of the pattern memory 17 are generated and applied to the scan-in bin SI of the device DUT in FIG. 3. At this time, the value of the counter in the control unit 13 becomes 0, so the address 1 of the test sequence memory 11 is incremented by +1 to the program counter 10 to instruct address 2, and the address calculation unit 12 is made to stop counting addresses. . In addition, other address registers 14-2~
14-4 holds the initial state of address 0, and patterns in other pattern memory sections (memory blocks) of the pattern memory 17 are not generated.

In this step, the order information of address 2 in the test sequence memory 11 is
) and at L//C control information LDA B, 80 (
Load Address 'fifor 5can-
Out Memory ) instruction returns the previous address O.
In the same way as writing the address to the S air address register 14-1 executed in step , address 0 of the pattern memory 17 is written to the SO airless register 14-2, and the SO pattern memory section (memory A scanout pattern of address O of block) is generated. Also, with the clock signal of the next step, the REP of address 3 of the test sequence memory 11 is
5 and the INCA command, scan-out patterns of addresses 1 to 5 of the SO pattern memory portion of the pattern memory 17 are generated and output in the same manner. The expected value pattern of this scan-out pattern and the output data of the scan-out bin SO of the device DUT are compared with a tester, etc., and thereby the shift registers of F1 to F6 of the device DUT are subjected to a Niji test with the scan test pattern of the Iff class. . Note that normally, the guest pattern of this shift register requires 92m patterns depending on the number m of F/Fs.

In the next step, the order information of address 4 in the test sequence memory 11 is stored as NOP (No 0 operation).
) and address control information LDA ``a P I (L
oadAddress”aforPrimar7
-in Memory) command, the control unit 1
3, the write controller 16-3 sends a programming clock signal to the PI address register 14-3, and the address O loaded into the address calculation unit 12 is written to the PI address register 14-3. A primary input pattern of the PI pattern memory section (memory block) of the pattern memory 17 is generated, and the device DU
Primary input pin PI (PII~PI3) of T
is applied to Also, the clock signal of the next step is NO.
P and the LDA6SO command write address 6 to the SO airless register 14-2 that was selected again in the same way, and the scan-out pattern at address 6 in the SO pattern memory section of the turn memory 17 is generated. In the next step, the operation of the previous step is repeated 4 times (for 4 clock signals) by REP 4 and INCA commands.
Repeatedly, scan-out patterns at addresses 7 to 10 of the SO pattern memory section of the pattern memory 17 are generated and output. Expected value pattern of this scanout pattern and scanout pin SO of device DUT
The output data of the combinational logic circuit 1 is compared with the output data of the combinational logic circuit 1.

Thereafter, the combinational logic circuits 2 and 3 are tested in the same manner.

It should be noted that the test pattern generation control device having the above-mentioned configuration clearly enables straight reading of the stored test patterns as shown in FIG. In addition, simultaneous generation of all bin parallel test patterns is also possible using the LDA of the test sequence memory 11.
Address register 1 is set by specifying sphere SI, So, PI, PO or by external specification of register selector 15.
This can be easily done by selecting 4-1 to 14-4 'i simultaneously.

FIG. 2 is a circuit diagram showing another embodiment of the test pattern generation control device according to the present invention, in which the number of steps t of instructions stored in the test sequence memory 11 of FIG. , P.I.

The memory selector 18 separates the PO pattern memory section (memory block), decodes the record indicating the type of test pattern of the address control information in the test sequence memory 11, and stores the record in the address register 14-1.
~14-4' will be selected individually! ! The circuit configuration for selecting 0 pattern memory 17 ft is shown. In FIG. 2, for example, the NOP and LDA narrow SI instructions at address O of the test sequence memory 11 in FIG. U
TL 5 (person dvance until 5Addr
ess ) and LDA u SI instruction, and replace the NOP and LDA u So instructions at address 2 in Figure 1 and the REP 5 and INCA instructions at address 3 with ADV UTL 5 and LDA & 80 instructions, NOP and LDA\ at address 4 in Figure 1
The PI command is converted to ADV and LDA'aP at address 2 in Figure 2.
Replace it with the I instruction, NOP and LD at address 5 in Figure 1.
Replace the A6SO instruction and the REP 4 and INCA instructions at address 6 with the ADV UTLIO and LDA6SO instructions in FIG. 2, and replace the 7-step instructions in the test sequence memory 11 in FIG. The instructions are reduced to four steps in the sequence memory 11.

With this configuration, first, the address calculation unit 12 performs address calculation from the loaded address O by +1 increment up to address 5 using the ADV UTL 5 of the order information of the address O of the test sequence memory 11 and the LDA...SI command of the address control information. Then pattern memory 17
S selected by the memory selector 18 from SI information indicating the type of test pattern.
A scan-in test pattern from address 0 to address 5 of the SI pattern memory section (memory block) of the pattern memory 17 is generated eleven times via the I address register 14-1 and applied to the scan-in bin SI of the device DUT. Here, a comparator built in the control unit 13 compares the address incremented by the address operation unit 12 with the address 5 using the Anv UTL 5 instruction, and when the address reaches 5, the control unit 13 instructs the program counter 10 to the next step. At the same time, the address calculation unit 12 is made to stop incrementing. In the next step, using the ADVUTL5 and LDAuSO instructions, the address calculation unit 12 similarly increments and specifies the address from address O to address 5, and
Scan-out test patterns from address 0 to address 5 of the SO pattern memory section are sequentially generated from the information through the SO airless register 14-2 selected by the memory selector 18, and the expected value pattern of this scan-out test pattern and the scan The output data of the outbin SO is compared, and the shift registers F1 to F6 of the F/Fs are tested. Similarly, in the next step, ADV and L
The DA '1A PI instruction generates the primary input test pattern at address O in the PI pattern memory section, and the next step TE ADV UTLIO to LDA 6
A scan-out test pattern from address 6 to address 10 of the SO pattern memory section is generated again, and the expected value pattern of this scan-out test pattern is compared with the output data of the scan-out bin SO. is tested. Thereafter, combinational logic circuits 2 and 3 are tested in the same manner.

In this embodiment, the number of instruction steps in the test sequence memory can be reduced, and the write controllers 16-1 to 16-4
This eliminates the need for hardware. Note that this test pattern generation control device can also generate a straight pattern of the stored test patterns as shown in FIG. 4 or a parallel pattern for all bins. Also, test patterns can be generated in the same way by loops and jumps.

The above embodiments can be used not only for generating test patterns in logic testers, but also for generating test patterns in memory testers.

In addition, a similar effect can be obtained not only in a tester in which one row or one block of pattern memory is divided and arranged corresponding to one bin or multiple bins of the device under test, but also an independent Test pattern generation and hold (retention of previous pattern data) functions can be controlled in real time.

As described above, according to the embodiment of the present invention, the test pattern data stored in the pattern memory is arranged and used according to the type of test pattern, and the test pattern data in the pattern memory is arranged according to the type of test pattern. Since they can be accessed independently, it is possible to generate a large test pattern using a small capacity pattern memory and test sequence memory, and it is also possible to increase the speed.

〔Effect of the invention〕

As explained above, according to the present invention, the sequence information for test pattern generation can be compressed to about one-tenth of the conventional size in normal cases. In addition to making it usable with a small capacity, test pattern information is also stored in the pattern memory in a compressed form that is about a tenth of the size of conventional methods, and can be accessed independently for each type of pattern, making it much more convenient. It is possible to generate test patterns for the device under test with a small memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing one embodiment of a test pattern generation control device according to the present invention, FIG. 2 is a circuit configuration diagram showing another embodiment, and FIG. FIG. 4 is an explanatory diagram illustrating a pattern memory test pattern; FIG. 5 is an explanatory diagram illustrating the generation order of the test patterns in FIG. 4; FIG. 6 is a pattern memory test according to the present invention. FIG. 7 is an explanatory diagram showing an example of a pattern, and FIG. 7 is an explanatory diagram showing the order in which the test patterns of FIG. 6 are generated. 10...Program counter, 11...Test sequence memory, 12...Address calculation unit, 13...
Control unit, 14-1 to 14-4...address register,
15...Register selector, 16-1 to 16-4...
Write controller, 17... Pattern memory, 18...
Memory selector, SI...Scan-in bin, SO...
- Scan out bin, PI...Primary input bin, PO...Primary output bin.

Claims (1)

[Claims] 1. Various pattern data are sequentially stored independently in a dedicated or divided pattern memory according to the type of test pattern, and the read address of the pattern memory is independently controlled for each type of test pattern. A test pattern generation control method using a pattern processor. 2. A pattern memory in which various pattern data are sequentially stored independently in memory blocks dedicated or divided according to the type of test pattern, and control information for identifying the type of test pattern is added to the sequence information for generating the test pattern. A test pattern generation control comprising: information means; and a memory selector for independently controlling the division of the memory blocks for each type of pattern when the pattern processor controls the read address of the pattern memory based on the information. Device. 3. A pattern memory that sequentially stores various pattern data independently in dedicated or divided memory blocks depending on the type of test pattern, and control information that identifies the type of test pattern is added to the sequence information that generates the test pattern. an information means, and an address register selector and a write controller for controlling the division of the memory blocks independently for each type of test pattern when the pattern processor controls the read address of the pattern memory based on the information. Equipped with a test pattern generator.