JPS61198943A - Clock extracting circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction due to noise by applying synchronization to a delay circuit at each preset time. CONSTITUTION:The leading of an input signal DATA is given by D.FFs 2, 3 and a NAND gate 9 and a differentiation signal SD is outputted, then counters 7, 8 are set to an initial value E6 (hexadecimal number). The the counters 7, 8 count 12MHz clocks Sc and the output is inputted to a NAND gate 4 at a time when the count goes to an FC (hexadecimal) after 22 clock pulses are counted. Since the input signal DATA rises at each 2musec, it is detected again by the D.FFs 2, 3 and the NAND gate 9 and the differentiation signal SD is outputted. Thus, a high level signal SB is outputted from an AND gate 4 to a NOR gate 5 and a high level signal CK is outputted from a counter 6. Thus, malfunction due to noise is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to high-level data link control procedures (HD L
The present invention relates to a circuit that extracts a clock used in synchronous communication from data received in a synchronous communication method such as C).

[Conventional technology]

Conventionally, as shown in FIG. 4, there have been two methods for extracting a synchronization clock from the received data DATA and providing it to the transmission LSI 41 as a clock extraction circuit 42.

The first is a feedback control system commonly called a phase-locked loop (PLL) that synchronizes the phase of the input signal and output signal, and the second is a system that detects the edges of the input signal and uses a built-in This method adjusts and synchronizes the phase of the clock from the -/regeneration circuit.

An example of the circuit configuration using the latter method is shown in FIG. 5, and its timing chart is shown in FIG. - This differential signal S is output, and the output of the NOR gate 5 is further input to the counter 6 as a load signal SL of the counter 6. This counter 6 is set to a count value 04 when the load signal SX is input, and is a hexadecimal counter that counts the 12M)lz clock Sc from the 12KHz oscillator l, and the output bit of the fourth digit is set to the count value 04 of this clock extraction circuit. It is used as an output GK. That is, when the count value is from 08 to OF, a high level signal CK is output.

Therefore, 1 time 1. The count value of the counter 6 is set to 04, the count of the 12 MHz clock Sc is started, and at time t2 when the count value becomes 08, the output GK rises to a high level. Then, at time t3 when the count value becomes 00, the output G
As K falls to a low level, the ripple carry C is output from the counter 6, and the load signal Sr is again input to the counter 6, and the count value of the counter 6 is set to 04. Furthermore, the output CK rises to a high level at time t, . . . and these operations are repeated thereafter.

[Problem that the invention seeks to solve]

However, the former method using PLL has a problem in that the circuit becomes complicated. Furthermore, in the latter method, an example of which is shown in FIG. 5, the clock output CK is extracted by detecting only the rising edge (or falling edge) of the input signal DATA. If noise exists in the input signal DATA, the edge of this noise is captured and the differential signal S and the load signal S are output at time t4.
This causes a malfunction in which the signal L occurs and the output CK rises at time t6.

An object of the present invention is to provide a clock extraction circuit that is resistant to noise and has a simple configuration.

[Means for solving problems]

The present invention was created by paying attention to the fact that in systems having a PLL type clock extraction circuit, 2 bytes of 00 data are added to the head of transmitted (received) data. That is,
If the signal is sent using the NRZi method as shown in Figure 3, the signal will be 1.0 and 0. For example, if the transfer rate is IM,
It is noted that a rising edge always exists 2 JLsec after one rising edge of the signal.

In the clock extraction circuit of the present invention, the delay circuit receives the detection signal from the edge detection circuit for a predetermined period of time (2g, gec).
When the synchronization signal is output after , the counter is reset only when a detection signal is output again from the knee/jie detection circuit at the same time, and the output of this counter is used as the reception clock.

[Effect]

In addition, synchronization is performed at predetermined time intervals preset in the delay circuit, so even if noise occurs at other times, the counter will not be reset and malfunction will not occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock extraction circuit according to the present invention. This embodiment includes a hexadecimal counter 7.8, a Nant gate 9.10, and a hexadecimal counter 7.8 in addition to the conventional example shown in FIG. An inverter 11 is provided. Counters 7 and 8 count the lower digits and upper digits, and together they form a 256-decimal counter from 00 to FF, but when the differential signal S is input as a load signal, the count value E6 is set. 12 MHz clock Sc from 12 MHz oscillator 1
An output line is connected to the Nandts gate 10 so that the Nandts gate 10 is opened when the counted value is from FC to FF.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG. First, the rising edge of the input signal OAτA is captured by the D-free flop 2.3 and the Nantes gate 9, and the differential signal S is output at time t7.
Counter 7.8 is set to an initial value E8. Thereafter, the counter 7.8 outputs a 12 MHz clock pulse, counts 22 clock pulses, and at time t8 when the counted value becomes FC, the Nandt gate IO opens and a low level signal S^ is input to the AND gate 4.

On the other hand, approximately 2JL from the rise of the input signal DATA mentioned above.
Since the time of sec has elapsed, the input signal DAT must be
There is a rising edge of A, which is connected to D flip-flop 2.
3 and the Nantes gate 9, and a differential signal SL) is output at time t9. Therefore, the counter 7.8 is initialized, and the high level signal SI+ is output from the AND gate 4 to the NOR gate 5, and the high level signal GK is output from the counter 6 at time tlQ in the same manner as in the conventional example. Output.

Note that if the differential signal SI) is not output and the count value of the counter 7.8 becomes OO without being initialized, the counting at the counter 7.8 is stopped rL.

〔Effect of the invention〕

As described above, the present invention has the advantage that a clock for synchronization can be extracted without malfunctioning even if noise is included in an input signal with a simple configuration. A major technical issue in data transmission systems is how to prevent errors.

The present invention is very useful.

[Brief explanation of drawings]

@ Figure 1 is a configuration diagram showing an embodiment of the clock extraction circuit of the present invention, Figure 2 is a timing chart of the embodiment of Figure 1,
FIG. 3 is an explanatory diagram showing the principle of the present invention, FIG. 4 is a conceptual diagram of a clock extraction circuit, and FIGS. 5 and 6 are configuration diagrams of a conventional example.
This is a timing chart. ■...12 MHz oscillator. 2.3...D flip-flop. 4...And Gate, 5...Noah Gate 6.7
．． 8... Counter, 9, 10... Nantes Gate 11... Inverter. Figure 1, 2. >sec. ooooooo. Figure 3 Figure 4

Claims (1)

[Claims] A digital data clock extraction circuit includes an edge detection circuit that detects a rising or falling edge of the digital data and outputs a detection signal, and when the detection signal is input, a preset transfer is performed. a delay circuit that outputs a synchronization signal after a predetermined time determined from a rate; a logic circuit that outputs a reset signal when the detection signal and the synchronization signal are input simultaneously; and an oscillator that outputs a clock pulse. and a counter that is reset by the reset signal and counts the clock pulses, and uses an output of the counter as a reception clock.