JPS61198778A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor characterized by high degree of integration and less parasitic capacity, by etching away an insulating film, which is formed on the side wall of a pattern used for selective oxidation, and forming a base contact region and an emitter region by self-alignment. CONSTITUTION:In a P-type Si substrate 1, arsenic ions are implanted, and a high concentration N-type embedded layer 2 and an N-type epitaxial layer 3 are formed. An Si dioxide layer 12, an Si nitride layer 13 and an insulating film of an Si dioxide layer 14 are formed thereon. A part other than an element forming region is removed. Then, an Si nitride film 15 and the Si dioxide film 14 are formed. With the layers 14 and 15 as masks, an Si dioxide layer 16 is provided. Then, a polycrystalline Si layer 17 including B and the like is formed. Its protruded part is removed, and the surface layer of the layer 17 is oxidized and converted into an Si dioxide layer 18. Thereafter, a base region 20 is formed by the implantation of B. A pure polycrystalline Si layer 21 is formed only on the side wall of the layer 18. The layer 13 is removed, and an opening is formed. The opening 22 is expanded at the lower part. Then, an emitter electrode 24, a base electrode 25 and a collector electrode 26 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a planar bipolar semiconductor device.

[Conventional technology]

It is a well-known fact that in semiconductor devices, it is important to increase the degree of integration and increase the operating speed.

Incidentally, a planar type bipolar transistor in the prior art is generally as shown in a schematic cross-sectional view in FIG. 13. In the figure, 1 is a semiconductor substrate of one conductivity type, for example, p-type, 2 is a high impurity concentration buried layer of the opposite conductivity type, 3 is an epitaxially grown layer of the opposite conductivity type, for example, n-type, which constitutes a collector, and 4 is an element isolation region of one conductivity type. Reference numeral 5 denotes a diffusion layer of one conductivity type and constitutes the base, and numeral 6 denotes a diffusion layer of the opposite conductivity type and constitutes the emitter. Reference numeral 7 denotes a collector electrode lead-out region of the opposite conductivity type, and 8.9 and 1O are made of metal layers, which constitute the collector, base, and emifter electrodes, respectively. Note that 11 is a field insulating film.

[Problem that the invention seeks to solve]

In the Brainer type bipolar transistor having such a structure, the base region 5 must be made considerably larger than the emitter region 6 in order to ensure an insulating distance between the base electrode 9 and the emitter electrode IO. However, the active region that acts as a transistor is only the region along the p-n junction, especially the region directly under the emitter region 6, and the other region is the base electrode extraction region, so it is desirable that the size of the active region be as small as possible. .

However, as mentioned above, in the conventional brainer type bipolar transistor, the base region has to be made larger than the functionally necessary size, which is a constraint on improving the degree of integration, and at the same time, the parasitic capacitance increases. , which also had the disadvantage of limiting the operating speed.

This drawback can be largely eliminated if the emitter, base, and collector are stacked three-dimensionally to form a vertical structure. Various efforts have been made to develop vertical bipolar transistors formed three-dimensionally and methods for manufacturing the same.

[Means for solving problems]

The present invention meets this requirement, and its means include a step of forming a first insulating film, a second insulating film, and a third insulating film on a semiconductor layer of one conductivity type forming a collector; Section 3.2
, (2) remaining the insulating film only on the area where the element is to be formed and removing it from other areas; forming a fourth insulating film on the sidewall of the remaining insulating film 3.2.1; converting the surface layer of the semiconductor layer into a fifth insulating film in a region not covered by the third and fourth insulating films; removing the fourth insulating film; forming a conductive film and connecting the first conductive film and the semiconductor layer; removing the third insulating film; converting the surface layer of the first conductive film into a sixth insulating film. step 1: introducing impurities of opposite conductivity type to form a base opposite conductivity type region in the surface layer of the semiconductor layer; forming an opening in the second insulating film, forming a semiconductor layer of one conductivity type in the opening, patterning the semiconductor layer to form an emitter electrode, and forming an emitter electrode under the opening; A method of manufacturing a semiconductor device, comprising the step of reconverting the surface layer of the semiconductor layer to one conductivity type to form an emitter.

[Effect]

In the present invention, the pattern sidewall (3.2) used for selective oxidation is
This is based on the idea of etching away the fourth insulating film formed on the side walls of the insulating film of , l, and forming a base contact region and an emitter region in a self-aligned manner.

〔Example〕

A method of manufacturing a vertical bipolar transistor according to an embodiment of the present invention will be further described below with reference to the drawings.

Refer to FIG. 1. After forming a high concentration n-type buried layer 2 by ion-implanting n-type impurities such as arsenic into the surface of a p-type silicon substrate l,
A mold epitaxial layer 3 is formed. This n-type epitaxial layer 3 has a thickness of about 2μ, and an impurity concentration of 10
It is about 15C11-3.

A silicon dioxide layer (first insulating film) 12 with a thickness of about 50 nm, a silicon nitride layer (second insulating film) with a thickness of about 100 n+s, and a silicon dioxide layer (third insulating film) with a thickness of about 600 nm ) 14. These layers can be easily formed using the CVD method.

Refer to FIG. 2 Using a photolithography method, a silicon dioxide layer (third insulating film) 14, a silicon nitride layer (second insulating film) 13, and a silicon dioxide layer (first insulating film) +2 are formed. It is removed from areas other than the element formation area. This removal step is possible using a reactive ion etching method using trifluoromethane as the reactive gas.

Refer to Figure 3. After forming a silicon nitride layer (fourth insulation film) 15 to a thickness of about 300 nm on the entire surface of the substrate using the CVD method, a reaction using trifluoromethane as a reactive gas is performed. The silicon dioxide layer (third insulating film) 14, the silicon nitride layer [second insulating film] 13, and the silicon dioxide layer (second insulating film) 14, which remained in the element formation region after being removed using a chemical ion etching method,
It remains only on the side wall with the first insulating film) 12.

Referring to FIG. 4, the entire surface of the substrate is oxidized using the silicon nitride layers 14 and 15 as masks to form a silicon dioxide layer (fifth insulating film) 16 having a thickness of about 300 nm.

Refer to FIG. 5. Remove the silicon nitride layer 15 and form the n-type epitaxial layer 3.
to expose. This exposed area becomes the contact area of the base. This step can be carried out by rinsing with hot phosphoric acid. Base contact area is 0.3p
About m can be obtained.

Refer to Figure 6. A polycrystalline silicon layer (first conductive film) containing p-type impurities such as poron at a concentration of about 102°CI+-3.
It is formed to about 0n layer.

Refer to FIG. 7. Only the convex portions of the polycrystalline silicon layer (first conductive film) 17 are removed. This step is easily possible using bias sputtering.

Refer to FIG. 8. The silicon dioxide layer (third insulating film) 14 is etched away using an acid or the like, and the polycrystalline silicon layer (first insulating film) is removed by etching.
The surface layer of the conductive film (conductive film) 17 is oxidized to a thickness of about 300 nm to convert it into a silicon dioxide layer (sixth insulator M) 18.

In this step, a polycrystalline silicon layer (first conductive M)
The p-type impurity is also diffused in the region where t7 contacts the n-type epitaxial layer R3, and a P region (base contact region) 19 is formed.

Referring to FIG. 9, a p-type impurity such as poron is ion-implanted to form a base region. The depth of this base region 20 is approximately 0.31 Lm, and the impurity concentration is approximately 1017c-3.

Note that the depth of the base contact region 18 is 0.5 uL.
The impurity concentration becomes approximately 1020c layer -3.

Refer to FIG. 10. After a polycrystalline silicon layer 21 containing no impurities is once formed to a thickness of about 300 nm, it is removed using a reactive ion etching method using carbon tetrafluoride as a reactive gas. It remains only on the sidewalls of the silicon dioxide layer 18. In this step, silicon nitride layer (second insulating film) 1
3 is also partially removed to form an opening 22.

Refer to FIG. 11. The exposed portion of the silicon dioxide layer (fourth insulator) 12 is
The opening 22 is enlarged downward by removing it using hydrofluoric acid or the like.

Refer to FIG. 12. After forming a polycrystalline silicon layer containing a high concentration of n-type impurities such as arsenic, it is removed from areas other than the emitter electrode/wiring area, heat-treated, and the emitter 23 and emitter electrode/wiring 24 are removed.
to form. The thickness of the emitter 23 is 0.1 to 0.2 mm, and its impurity concentration is 1020 CI+-3.

Furthermore, the impurity concentration of the emitter electrode 24 is also 1020c11.
It will be about -3.

The base electrode 25 and the collector electrode 2B can be easily formed by forming a contact window using photolithography and depositing a metal such as aluminum thereon, as in the case of the prior art.

The vertical structure bipolar transistor manufactured through the following process has an extremely small emitter width of about 0.5 to tg and a base contact region of about 0.31 Ls, contributing to an improvement in the degree of integration. Furthermore, the 1°S raw capacity is also reduced, and the switching speed is improved by about 30% compared to the conventional technology.

〔Effect of the invention〕

As explained above, the method for manufacturing a semiconductor device according to the present invention is based on the pattern sidewalls (3.2.
This method is based on the idea of etching away the fourth insulating film formed on the sidewalls of the first insulating film to form a base contact region and an emitter region in a self-aligned manner. Higher integration, smaller parasitic capacitors, and significantly faster switching speeds.

[Brief explanation of drawings]

1 to 12 are cross-sectional views of a substrate after completion of the main manufacturing steps of a vertical bipolar transistor according to an embodiment of the present invention. FIG. 13 is a sectional view of a substrate of a planar bipolar transistor according to the prior art. ■...P-type semiconductor substrate, 2...N-type high impurity concentration buried layer, 3...N-type epitaxial layer, 4
11Φ・Element isolation region, 5... P-type diffusion layer (base), 6... N-type diffusion layer (emitter),
8・φ-Collector electrode. 9...Base electrode, 10...Fist emitter electrode, 11
-...field insulating film, 12... and silicon dioxide layer (first insulating film), 13... silicon nitride layer (
second insulating film), 14... silicon dioxide layer (third
15... silicon nitride layer (fourth insulating film), te... silicon dioxide layer (fifth insulating IPJ), 17--, polycrystalline silicon layer (first conductive film) ), 18... silicon dioxide layer (sixth insulating film), 19... p region (base contact region),
20... Base region, 21... Polycrystalline silicon layer (semiconductor layer), 22, Φ, opening, 23... Φ emitter, 24... Emitter electrode/wiring, 25 fist, e base electrode, 1st Bfl Figure 2 Figure 3 Figure 4 Figure 5 Figure 6! ! y Figure 7 Figure 1o Figure 11 @12rlJ Figure 13

Claims (1)

[Claims] a first insulating film on a semiconductor layer of one conductivity type forming a collector;
a step of forming a second insulating film and a third insulating film;
2. A step of leaving the first insulating film only on the region where the element is to be formed and removing it from other regions; a step of forming a fourth insulating film on the sidewalls of the remaining third, second, and first insulating films; converting the surface layer of the semiconductor layer into a fifth insulating film in a region not covered by the third and fourth insulating films; removing the fourth insulating film; a step of forming a first conductive film and connecting the first conductive film and the semiconductor layer; a step of removing the third insulating film; and a step of converting the surface layer of the first conductive film into a sixth insulating film. a step of introducing an impurity of an opposite conductivity type to form a base opposite conductivity type region in the surface layer of the semiconductor layer; a step of forming an opening in the second and first insulating films, forming a semiconductor layer of one conductivity type in the opening, patterning the semiconductor layer to form an emitter electrode, and forming an emitter electrode in the opening; A method for manufacturing a semiconductor device, comprising the step of converting the lower surface layer of the semiconductor layer again to one conductivity type to form an emitter.