JPH0571132B2 - - Google Patents
Info
- Publication number
- JPH0571132B2 JPH0571132B2 JP3909185A JP3909185A JPH0571132B2 JP H0571132 B2 JPH0571132 B2 JP H0571132B2 JP 3909185 A JP3909185 A JP 3909185A JP 3909185 A JP3909185 A JP 3909185A JP H0571132 B2 JPH0571132 B2 JP H0571132B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- region
- conductivity type
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 66
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 11
- 239000002344 surface layer Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 32
- 235000012239 silicon dioxide Nutrition 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- UNRFQJSWBQGLDR-UHFFFAOYSA-N methane trihydrofluoride Chemical compound C.F.F.F UNRFQJSWBQGLDR-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、プレーナ型バイポーラ半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a planar bipolar semiconductor device.
半導体装置において、集積度の向上と動作速度
の向上とが重要な要請であること周知の事実であ
る。
It is a well-known fact that an improvement in the degree of integration and an improvement in operating speed are important requirements for semiconductor devices.
ところで、従来技術におけるプレーナ型バイポ
ーラトランジスタは、一般に第１３図に概略断面
図を示す如きものである。図において、１は一導
電型例えばＰ型の半導体基板であり、２は反対導
電型の高不純物濃度埋め込み層であり、３は反対
導電型例えばｎ型のエピタキシヤル成長層であり
コレクタを構成し、４は一導電型の素子分離領域
である。５は一導電型の拡散層でありベースを構
成し、６は反対導電型の拡散層でありエミツタを
構成する。７は反対導電型のコレクタ電極引き出
し領域であり、８，９，１０は金属層よりなり、
それぞれ、コレクタ、ベース、エミツタの各電極
を構成する。尚、１１はフイールド絶縁膜であ
る。 Incidentally, a planar type bipolar transistor in the prior art is generally as shown in a schematic cross-sectional view in FIG. 13. In the figure, 1 is a semiconductor substrate of one conductivity type, for example, P type, 2 is a high impurity concentration buried layer of the opposite conductivity type, and 3 is an epitaxially grown layer of the opposite conductivity type, for example, N type, which constitutes the collector. , 4 are element isolation regions of one conductivity type. 5 is a diffusion layer of one conductivity type and constitutes a base, and 6 is a diffusion layer of the opposite conductivity type and constitutes an emitter. 7 is a collector electrode extraction region of the opposite conductivity type, 8, 9, and 10 are made of metal layers;
Each constitutes a collector, a base, and an emitter electrode. Note that 11 is a field insulating film.
（発明が解決しようとする問題点）
かゝる構造のプレーナ型バイポーラトランジス
タにおいては、ベース電極９とエミツタ電極１０
との絶縁距離を確保するため、ベース領域５はエ
ミツタ領域６よりかなり大きくせざるを得ない。
しかし、トランジスタ作用をなす活性領域はｐ−
ｎ接合に沿う領域特にエミツタ領域６の直下の領
域のみであり、それ以外の領域はベース電極引き
出し領域であるから、その大きさはできるだけ小
さいことが望ましい。(Problems to be Solved by the Invention) In the planar bipolar transistor having such a structure, the base electrode 9 and the emitter electrode 10
In order to ensure an insulating distance between the base region 5 and the emitter region 6, the base region 5 must be made considerably larger than the emitter region 6.
However, the active region that acts as a transistor is p-
It is only the region along the n-junction, especially the region immediately below the emitter region 6, and the other region is the base electrode extraction region, so it is desirable that its size be as small as possible.
ところが、上記せるとおり、従来技術における
プレーナ型バイポーラトランジスタにおいては、
ベース領域を機能的に必要とする大きさより大き
くせざるを得ず集積度を向上する制約となり、同
時に、寄性容量が大きくなるので、動作速度も制
限するという欠点があつた。 However, as mentioned above, in the conventional planar bipolar transistor,
This has the disadvantage that the base region has to be made larger than what is functionally necessary, which limits the degree of integration, and at the same time, the parasitic capacitance increases, which limits the operating speed.
かゝる欠点は、エミツタ・ベース・コレクタを
立体的に積層して形成して立型構造とすれば、か
なり解消されるので、エミツタ・ベース・コレク
タが基板表面に対して垂直な方向に積層され立体
的に形成されてなる立型構造のバイポーラトラン
ジスタとその製造方法を開発する努力が種々とな
されている。 These drawbacks can be largely eliminated if the emitter base collector is stacked three-dimensionally to form a vertical structure, so if the emitter base collector is stacked in a direction perpendicular to the substrate surface Various efforts have been made to develop vertical bipolar transistors formed three-dimensionally and methods for manufacturing the same.
本発明は、この要請に沿うものであり、その手
段は、コレクタをなす一導電型の半導体層上に第
１の絶縁膜、第２の絶縁膜、第３の絶縁膜を形成
する工程、該第３，２，１の絶縁膜を素子形成予
定領域上のみに残留しその他の領域から除去する
工程、第４の絶縁膜を、前記残留し第３，２，１
の絶縁膜の側壁に形成する工程、前記第３，４の
絶縁膜によつて覆われていない領域において前記
半導体層の表層を第５の絶縁膜に転換する工程、
前記第４の絶縁膜を除去する工程、反対導電型の
不純物を含む第１の導電膜を形成し、該第１の導
電膜と前記半導体層とを接続する工程、前記第３
の絶縁膜を除去する工程、前記第１の導電膜の表
層を第６の絶縁膜に転換する工程、反対導電型の
不純物を導入して前記半導体層の表層にベースを
なす反対導電型領域を形成する工程、半導体層
を、前記第１の導電膜の表層が転換された第６の
絶縁膜の側壁に形成する工程、前記第２，１の絶
縁膜に開口を形成する工程、該開口に一導電型の
半導体層を形成し該半導体層をパターニングして
エミツタ電極を形成し前記開口下部の前記半導体
層表層を一導電型に再転換してエミツタを形成す
る工程を含むことを特徴とする半導体装置の製造
方法にある。
The present invention meets this requirement, and its means include a step of forming a first insulating film, a second insulating film, and a third insulating film on a semiconductor layer of one conductivity type forming a collector; a step of leaving the third, second and first insulating films only on the area where the element is to be formed and removing them from other areas;
a step of converting the surface layer of the semiconductor layer into a fifth insulating film in a region not covered by the third and fourth insulating films;
a step of removing the fourth insulating film; a step of forming a first conductive film containing impurities of an opposite conductivity type; and a step of connecting the first conductive film and the semiconductor layer;
a step of converting the surface layer of the first conductive film into a sixth insulating film; and a step of introducing an impurity of an opposite conductivity type to form a base region of the opposite conductivity type in the surface layer of the semiconductor layer. forming a semiconductor layer on a side wall of a sixth insulating film in which the surface layer of the first conductive film has been converted; forming an opening in the second and first insulating films; The method is characterized by comprising a step of forming a semiconductor layer of one conductivity type, patterning the semiconductor layer to form an emitter electrode, and converting the surface layer of the semiconductor layer below the opening again to one conductivity type to form an emitter electrode. In a method of manufacturing a semiconductor device.
本発明は、選択酸化に使用したパターン側壁
（第３，２，１の絶縁膜の側壁）に形成された第
４の絶縁膜をエツチング除去して、ベース・コン
タクト領域とエミツタ領域とをセルフアラインで
形成するというアイデアにもとづくものである。
In the present invention, the base contact region and the emitter region are self-aligned by etching and removing the fourth insulating film formed on the sidewalls of the pattern used for selective oxidation (the sidewalls of the third, second, and first insulating films). It is based on the idea of forming
以下、図面を参照しつゝ、本発明の一実施例に
係る立型バイポーラトランジスタの製造方法につ
いてさらに説明する。
Hereinafter, a method for manufacturing a vertical bipolar transistor according to an embodiment of the present invention will be further described with reference to the drawings.
第１図参照
ｐ型シリコン基板１の表面に、ヒ素等ｎ型不純
物をイオン注入して、高濃度ｎ型埋め込み層２を
形成した後、ｎ型エピタキシヤル層３を形成す
る。このｎ型エピタキシヤル層３は厚さが2μm程
度であり、不純物濃度は1015cm-3程度である。Refer to FIG. 1. After forming a heavily doped n-type buried layer 2 by ion-implanting n-type impurities such as arsenic into the surface of a p-type silicon substrate 1, an n-type epitaxial layer 3 is formed. This n-type epitaxial layer 3 has a thickness of about 2 μm and an impurity concentration of about 10 15 cm −3 .
厚さ50nm程度の二酸化シリコン層（第１の絶
縁膜）１２と厚さ100nm程度の窒化シリコン層
（第２の絶縁膜）１３と厚さ600nm程度の二酸化
シリコン層（第３の絶縁膜）１４とを形成する。
これらの層はCVD法をもつて容易に形成しうる。 A silicon dioxide layer (first insulating film) 12 with a thickness of about 50 nm, a silicon nitride layer (second insulating film) 13 with a thickness of about 100 nm, and a silicon dioxide layer (third insulating film) 14 with a thickness of about 600 nm. and form.
These layers can be easily formed using the CVD method.
第２図参照
フオトリソグラフイー法を使用して、二酸化シ
リコン層（第３の絶縁膜）１４と窒化シリコン層
（第２の絶縁膜）１３と二酸化シリコン層（第１
の絶縁膜）１２とを、素子形成領域上以外から除
去する。この除去工程は、三フツ化メタンを反応
性ガスとする反応性イオンエツチング法を使用し
て可能である。Refer to Figure 2. Using a photolithography method, a silicon dioxide layer (third insulating film) 14, a silicon nitride layer (second insulating film) 13 and a silicon dioxide layer (first insulating film) are formed.
(insulating film) 12 is removed from areas other than on the element formation region. This removal step is possible using a reactive ion etching method using methane trifluoride as the reactive gas.
第３図参照
CVD法を使用して、300nm程度の厚さに窒化
シリコン層（第４の絶縁膜）１５を、一旦基板全
面に形成した後、三フツ化メタンを反応性ガスと
する反応性イオンエツチング法を使用して除去
し、素子形成領域に残留した二酸化シリコン層
（第３の絶縁膜）１４と窒化シリコン層（第２の
絶縁膜）１３と二酸化シリコン層（第１の絶縁
膜）１２との側壁のみに残留する。Refer to Figure 3 After a silicon nitride layer (fourth insulating film) 15 with a thickness of about 300 nm is formed on the entire surface of the substrate using the CVD method, a reactive gas using methane trifluoride is applied. The silicon dioxide layer (third insulating film) 14, the silicon nitride layer (second insulating film) 13, and the silicon dioxide layer (first insulating film) that were removed using the ion etching method and remained in the element formation region It remains only on the side wall with 12.
第４図参照
窒化シリコン層１４，１５のマスクとして基板
全面を酸化して厚さ300nm程度の二酸化シリコン
層（第５の絶縁膜）１６を形成する。Refer to FIG. 4. As a mask for the silicon nitride layers 14 and 15, the entire surface of the substrate is oxidized to form a silicon dioxide layer (fifth insulating film) 16 with a thickness of about 300 nm.
第５図参照
窒化シリコン層１５を除去してｎ型エピタキシ
ヤル層３を露出する。この露出された領域がベー
スのコンタクト領域となる。この工程は、熱リン
酸によるエツチングをもつて実行しうる。ベー
ス・コンタクト領域は0.3μm程度が得られる。Refer to FIG. 5. The silicon nitride layer 15 is removed to expose the n-type epitaxial layer 3. This exposed area becomes the contact area of the base. This step may be carried out by etching with hot phosphoric acid. The base contact area can be approximately 0.3 μm.
第６図参照
ボロン等ｐ型不純物を1020cm-3に含有する多結
晶シリコン層（第１の導電膜）１７を厚さ600nm
程度に形成する。Refer to Figure 6. A polycrystalline silicon layer (first conductive film) 17 containing p-type impurities such as boron at a concentration of 10 20 cm -3 is formed to a thickness of 600 nm.
Form to a certain extent.
第７図参照
多結晶シリコン層（第１の導電膜）１７の凸部
のみを除去する。この工程は、バイアススパツタ
法をもつて容易に可能である。See FIG. 7. Only the convex portions of the polycrystalline silicon layer (first conductive film) 17 are removed. This step is easily possible using the bias sputtering method.
第８図参照
フツ酸等を使用して二酸化シリコン層（第３の
絶縁膜）１４をエツチング除去し、多結晶シリコ
ン層（第１の導電膜）１７の表層を、300nm程度
の厚さに酸化して二酸化シリコン層（第６の絶縁
膜）１８に転換する。この工程において、多結晶
シリコン層（第１の導電膜）１７がｎ型エピタキ
シヤル層３と接触する領域でもｐ型不純物の拡散
が行なわれて、ｐ領域（ベースコンタクト領域）
１８が形成される。Refer to Figure 8. The silicon dioxide layer (third insulating film) 14 is etched away using hydrofluoric acid, etc., and the surface layer of the polycrystalline silicon layer (first conductive film) 17 is oxidized to a thickness of about 300 nm. The silicon dioxide layer (sixth insulating film) 18 is converted into a silicon dioxide layer (sixth insulating film) 18. In this step, p-type impurities are also diffused in the region where the polycrystalline silicon layer (first conductive film) 17 contacts the n-type epitaxial layer 3, forming a p-region (base contact region).
18 is formed.
第９図参照
ボロン等ｐ型不純物をイオン注入してベース領
域を形成する。このベース領域２０の深さは
0.3μm程度となり、不純物濃度は1017cm-3程度と
なる。なお、ベースコンタクト領域１９の深さは
0.5μm程度となり不純物濃度は1020cm-3程度とな
る。Refer to FIG. 9. A base region is formed by ion-implanting a p-type impurity such as boron. The depth of this base region 20 is
The thickness is approximately 0.3 μm, and the impurity concentration is approximately 10 17 cm −3 . Note that the depth of the base contact region 19 is
The thickness is approximately 0.5 μm, and the impurity concentration is approximately 10 20 cm −3 .
第１０図参照
不純物を含まない多結晶シリコン層２１を
300nm程度の厚さに一旦形成した後、四フツ化炭
素を反応性ガスとする反応性イオンエツチング法
を使用してこれを除去して、二酸化シリコン層１
８の側壁のみに残留する。この工程において、窒
化シリコン層（第２の絶縁膜）１３も一部除去さ
れ、開口２２が形成される。Refer to Figure 10. Polycrystalline silicon layer 21 containing no impurities
Once formed to a thickness of about 300 nm, it is removed using a reactive ion etching method using carbon tetrafluoride as a reactive gas, and the silicon dioxide layer 1 is removed.
It remains only on the side wall of 8. In this step, a portion of the silicon nitride layer (second insulating film) 13 is also removed, and an opening 22 is formed.
第１１図参照
二酸化シリコン層（第４の絶縁膜）１２の露出
部を、フツ酸等を使用して除去して、開口２２を
下方に拡大する。Refer to FIG. 11. The exposed portion of the silicon dioxide layer (fourth insulating film) 12 is removed using hydrofluoric acid or the like to enlarge the opening 22 downward.
第１２図参照
ヒ素等ｎ型不純物を高濃度に含む多結晶シリコ
ン層を形成した後、エミツタ電極・配線領域以外
から除去し、熱処理をなして、エミツタ２３とエ
ミツタ電極・配線２４とを形成する。エミツタ２
３の厚さは、0.1〜0.2μmとなりその不純物濃度は
1020cm-3となる。また、エミツタ電極２４の不純
物濃度も1020cm-3程度となる。See FIG. 12 After forming a polycrystalline silicon layer containing a high concentration of n-type impurities such as arsenic, it is removed from areas other than the emitter electrode/wiring area and heat treated to form the emitter 23 and the emitter electrode/wiring 24. . Emitsuta 2
The thickness of No. 3 is 0.1 to 0.2 μm, and its impurity concentration is
10 20 cm -3 . Further, the impurity concentration of the emitter electrode 24 is also approximately 10 20 cm -3 .
ベース電極２５、コレクタ電極２８は、従来技
術における場合と同様に、フオトリソグラフイー
法を使用してコンタクト窓明けをなし、そこにア
ルミニウム等の金属の蒸着をなして容易に形成し
うる。 The base electrode 25 and the collector electrode 28 can be easily formed by forming a contact window using photolithography and vapor depositing a metal such as aluminum thereon, as in the prior art.
以上の工程をもつて製造される立型構造のバイ
ポーラトランジスタは、エミツタ幅が0.5〜1μm
程度、ベース・コンタクト領域が0.3μm程度と極
めて小さくなり、集積度の向上に寄与する。ま
た、寄生容量も小さくなり、スイツチングスピー
ドは従来技術に比して30％程度向上する。 The vertical structure bipolar transistor manufactured using the above process has an emitter width of 0.5 to 1 μm.
The base contact area is extremely small, approximately 0.3 μm, contributing to an improvement in the degree of integration. Parasitic capacitance is also reduced, and switching speed is improved by about 30% compared to conventional technology.
以上説明せるとおり、本発明に係る、半導体装
置の製造方法は、選択酸化に使用したパターン側
壁（第３，２，１の絶縁膜の側壁）に形成された
第４の絶縁膜をエツチング除去して、ベース・コ
ンタクト領域とエミツタ領域とをセルフアライン
で形成するというアイデアにもとづいており、従
来技術に比して、集積度が向上し、寄生容量が小
さく、スイツチング速度が大幅に向上している。
As explained above, the method for manufacturing a semiconductor device according to the present invention etches and removes the fourth insulating film formed on the sidewalls of the pattern used for selective oxidation (the sidewalls of the third, second, and first insulating films). It is based on the idea of forming the base contact region and emitter region in a self-aligned manner, resulting in higher integration, lower parasitic capacitance, and significantly faster switching speed than conventional technology. .
第１図〜１２図は、本発明の一実施例に係る立
型バイポーラトランジスタの主要製造工程完了後
の基板断面図である。第１３図は従来技術に係る
プレーナ型バイポーラトランジスタの基板断面図
である。
１……ｐ型半導体基板、２……ｎ型高不純物濃
度埋め込み層、３……ｎ型エピタキシヤル層、４
……素子分離領域、５……ｐ型拡散層（ベース）、
６……ｎ型拡散層（エミツタ）、８……コレクタ
電極、９……ベース電極、１０……エミツタ電
極、１１……フイールド絶縁膜、１２……二酸化
シリコン層（第１の絶縁膜）、１３……窒化シリ
コン層（第２の絶縁膜）、１４……二酸化シリコ
ン層（第３の絶縁膜）、１５……窒化シリコン層
（第４の絶縁膜）、１６……二酸化シリコン層（第
５の絶縁膜）、１７……多結晶シリコン層（第１
の導電膜）、１８……二酸化シリコン層（第６の
絶縁膜）、１９……ｐ領域（ベースコンタクト領
域）、２０……ベース領域、２１……多結晶シリ
コン層（半導体層）、２２……開口、２３……エ
ミツタ、２４……エミツタ電極・配線、２５……
ベース電極、２６……コレクタ電極。
1 to 12 are cross-sectional views of a substrate after completion of the main manufacturing steps of a vertical bipolar transistor according to an embodiment of the present invention. FIG. 13 is a sectional view of a substrate of a planar bipolar transistor according to the prior art. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n-type high impurity concentration buried layer, 3...n-type epitaxial layer, 4
...Element isolation region, 5...p-type diffusion layer (base),
6... N-type diffusion layer (emitter), 8... Collector electrode, 9... Base electrode, 10... Emitter electrode, 11... Field insulating film, 12... Silicon dioxide layer (first insulating film), 13...Silicon nitride layer (second insulating film), 14...Silicon dioxide layer (third insulating film), 15...Silicon nitride layer (fourth insulating film), 16...Silicon dioxide layer (third insulating film) 5), 17...polycrystalline silicon layer (first
conductive film), 18... silicon dioxide layer (sixth insulating film), 19... p region (base contact region), 20... base region, 21... polycrystalline silicon layer (semiconductor layer), 22... ...Aperture, 23...Emitter, 24...Emitter electrode/wiring, 25...
Base electrode, 26...collector electrode.
Claims (1)
の絶縁膜、第２の絶縁膜、第３の絶縁膜を形成す
る工程、該第３，２，１の絶縁膜を素子形成予定
領域上のみに残留しその他の領域から除去する工
程、第４の絶縁膜を、前記残留した第３，２，１
の絶縁膜の側壁に形成する工程、前記第３，４の
絶縁膜によつて覆われていない領域において前記
半導体層の表層を第５の絶縁膜に転換する工程、
前記第４の絶縁膜を除去する工程、反対導電型の
不純物を含む第１の導電膜を形成し、該第１の導
電膜と前記半導体層とを接続する工程、前記第３
の絶縁膜を除去する工程、前記第１の導電膜の表
層を第６の絶縁膜に転換する工程、反対導電型の
不純物を導入して前記半導体層の表層にベースを
なす反対導電型領域を形成する工程、半導体層
を、前記第１の導電膜の表層が転換された第６の
絶縁膜の側壁に形成する工程、前記第２，１の絶
縁膜に開口を形成する工程、該開口に一導電型の
半導体層を形成し該半導体層をパターニングして
エミツタ電極を形成し前記開口下部の前記半導体
層表層を一導電型に再転換してエミツタを形成す
る工程を含むことを特徴とする半導体装置の製造
方法。1 A first layer is placed on a semiconductor layer of one conductivity type forming a collector.
a step of forming an insulating film, a second insulating film, and a third insulating film; a step of leaving the third, second, and first insulating films only on the region where the element is to be formed and removing them from other regions; The remaining third, second, and first insulating films are
a step of converting the surface layer of the semiconductor layer into a fifth insulating film in a region not covered by the third and fourth insulating films;
a step of removing the fourth insulating film; a step of forming a first conductive film containing impurities of an opposite conductivity type; and a step of connecting the first conductive film and the semiconductor layer;
a step of converting the surface layer of the first conductive film into a sixth insulating film; and a step of introducing an impurity of an opposite conductivity type to form a base region of the opposite conductivity type in the surface layer of the semiconductor layer. forming a semiconductor layer on a side wall of a sixth insulating film in which the surface layer of the first conductive film has been converted; forming an opening in the second and first insulating films; The method is characterized by comprising a step of forming a semiconductor layer of one conductivity type, patterning the semiconductor layer to form an emitter electrode, and converting the surface layer of the semiconductor layer below the opening again to one conductivity type to form an emitter electrode. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3909185A JPS61198778A (en) | 1985-02-28 | 1985-02-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3909185A JPS61198778A (en) | 1985-02-28 | 1985-02-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61198778A JPS61198778A (en) | 1986-09-03 |
| JPH0571132B2 true JPH0571132B2 (en) | 1993-10-06 |
Family
ID=12543402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3909185A Granted JPS61198778A (en) | 1985-02-28 | 1985-02-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61198778A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124564A (en) * | 1986-11-14 | 1988-05-28 | Toshiba Corp | Manufacture of semiconductor device |
-
1985
- 1985-02-28 JP JP3909185A patent/JPS61198778A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61198778A (en) | 1986-09-03 |
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