JPS61198354A - Lsi mode setting circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for any special input pin by adding a small quantity of hardware to the inside and outside of an LSI so as to use the firmware in common. CONSTITUTION:Plural mode settings are attained by adding gates 6, 7, 8, 9 and a flip-flop 10. When n-set of the mode setting flip-flops 10 are used, a maximum of 2<n> ways of modes are set. In order to change the mode even except resetting, a clock signal from an address decoder 11 and a mode data input from a data bus (DATA) are given to the mode setting flip-flop 10. When no mode change is required except resetting, the circuit above is not required and an RS flip-flop with a few cell number can be used for the flip-flop 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an LSI mode setting circuit for an LSI having a mode initial setting function.

In recent years, due to advances in semiconductor technology, LS for controlling peripheral devices, which are microprocessors and their peripheral families, has increased.
I can now be obtained cheaply. These ready-made LSIs
The components can be combined without adding an external logic circuit, and by organically combining them using their software instructions, a relatively high-performance microcomputer system can be constructed.

By the way, conventionally, when trying to operate the above-mentioned LSI in multiple modes, the following two modes were used to select one.
The traditional method was used.

One method is to provide a flip-flop for selecting a mode inside the LSI, allocate it to the input/output terminal of the iCPU, and set the mode on a one-to-one basis. other 1
One method is to set the mode by providing an input bin for mode setting on the LSI when the CPU cannot set the mode, such as when the LSI is used alone.

The former method is inappropriate when the mode must already be set when the LSI starts operating, and firmware often cannot be shared simply because the initial settings are different. Furthermore, the latter requires a dedicated input pin for mode setting9, and has the disadvantage that this pin is not used effectively.

[Purpose of the invention]

The present invention has been made in view of the above drawbacks, and is
It is an object of the present invention to provide an LSI mode setting circuit that allows commonization of firmware by adding a small amount of hardware inside and outside, and eliminates the need for a special input bin.

[Summary of the invention]

Currently, most LSIs use firmware to make initial mode settings, but some firmware
It is often possible to use them in common by removing the initial setting part. Therefore, it is very useful for the LSI itself to have a mode initial setting function. In view of this, the present invention includes a mode flip-flop in the LSI and several gates that control the set/reset of the mode flip-flop from mode data and reset signals, and also provides a mode flip-flop outside the LSI for a certain purpose via a database. An external additional circuit is provided which multiplexes the input signal to be used and the mode data to be set, and supplies the mode data at reset time and the input signal at other times to the LSI.

This eliminates the need to initialize the mode of the LSI using firmware, making it possible to standardize the firmware. Also, there is no need to provide a special input pin.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a diagram showing a circuit configuration inside an LSI showing an embodiment of the present invention, and only the characteristic parts of the present invention are extracted and shown. In the figure, 1 to 5 are LSI input/output covers;
6 is an inverter that inverts the mode input, and 7 is a reset circuit.

8 and 9 are mode setting flip-flops, NAND gates are used to set/reset 10, 10 is a mode setting flip-flop, and 11 is an LSI.
Address decoder for internal registers (not shown).

The embodiment of the present invention is an example of a case where there are two modes; however, by adding )y'-toro, 8.9.10, and a flip-flop 10, a plurality of mode settings can be performed. When there are n mode setting flip-flops 10, a maximum of 2n modes can be set.

In the embodiment of the present invention, the clock signal from the address decoder 11 and the mode data input from the data bus (DATA) are connected to the mode setting flip-flop 10 so that the mode can be changed even at times other than reset. However, if there is no need to change the mode other than during reset, this circuit is unnecessary and the mode setting flip 70.
Group 10 includes RS tie flip 7, which has a small number of cells.
0 tubes can be used.

When the LSI shown in FIG. 1 is used, FIG. 2 shows an example of an external circuit necessary to complete the present invention. An input signal X used for a certain purpose and mode data (here VCC or GND) are multiplexed by a selector 21 and input to an LSI 22 . The selector 2 is controlled so that mode data is output at the time of reset, and the input signal xt ratio is output at other times.

The embodiment shown in FIG. 3 is a case where mode data is input from the data bus (DATA), and the tristate buffers 31, 32, and 33 connected to the data path (DATA) are turned on. Data bus (DATA)
Output mode data on top. At this time, all other tristate buffers connected to the data bus (DATA) must be turned off to prevent data collision.

Assuming that mode data is output only at reset, the direction of the bidirectional data path buffer inside the LSI 34 is controlled so that it is input from the outside to the inside at reset. In Figure 1, mode data is data
In order to input from the path, connect from point ■-■ to point ■-0. Which pin of the LSI should be used to input the mode data is determined by considering whether the external circuit will be simple.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail using the timing chart shown in FIG. The timing chart shown in FIG. 4 shows the relationship between the reset signal input (RESET) and the mode signal input (MODE) input to the LSI. The time 1 kglcT from the fall of the reset signal until the mode setting data is determined indicates the mode data holding period until the reset signal rises.

When a reset is applied, a selector external to the LSI, that is, selector 21. in FIG. Mode data is input from a certain input pin of the LSI through the tri-stepper 31, 32, and 33 in FIG. After the mode data is confirmed, set the mode using Nantes gates 8 and 9 f70
set or reset. toAv+ts
When the reset signal is raised after +ct time has elapsed, both the outputs of the Nant gates 8 and 9 are set to the "T (IGH") level, and the multiple mode setting is completed. Required timing conditions are listed below.

(”) taxes > toxv + tB!H7
+ Gate delay inside the LSI (2) taxr > mode flip-flop 10 set/reset minimum pulse width (3) t HL D holds data in the mode setting flip-flop 10 considering the gate delay inside the LSI Take enough time to

〔Effect of the invention〕

As explained above, according to the present invention, LS is
There is no need to initialize the I mode. This means that
It is necessary to change the firmware when the mode selection or mode setting in the initial setup does not affect the firmware operation flow due to differences in hardware (for example, changing the control string due to different types of memory). This makes it possible to standardize firmware without having to use the same software. Furthermore, since the mode is set at reset, the output pin will not be in an undefined state due to a difference in mode. Furthermore, since the mode data input is multiplexed, there is no need to provide a special input pin, and therefore it can be used with any type of LSI.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an internal circuit configuration of an LSI that is an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing embodiments of an external circuit added to the outside of the LSI shown in FIG. 1. , 4th
The figure is a timing chart showing the operation of the embodiment of the present invention. 1.2,3,4.5...I/O buffer, 6゜7...
・Inverter, 8.9... NAND gate, 10...
Mode setting function, f-flop, 1...address decoder, 21...selector, 31, 32゜33...tri-state buffer, 22.34...LSI Patent attorney Patent attorney Suzue Takehiko Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) An external circuit that multiplexes the input signal and mode data obtained via the data bus, and is controlled to output the mode data at reset and the above input signal as valid at other times, and the input signal obtained from this external circuit. an LSI to which a multiplexed signal and a reset signal input are supplied; at least one mode flip-flop in the LSI in which the mode data is stored; and the mode data and reset signal obtained from the external circuit. An LSI mode setting circuit comprising several gates in an LSI that control setting/resetting of flip-flops. (2) The mode flip-flop is supplied with a clock signal from an address decoder built into the LSI and mode data obtained via a data bus, and the mode data is set even at times other than reset. The LSI mode setting circuit described in Range 1.