JPS61196348A - Input output control device - Google Patents

Abstract

PURPOSE:To prevent that the path of long waiting time is timed out by priority- processing the interruption from the long path to wait for the final status report. CONSTITUTION:When an IOC (input output control device) receives input output instructions through respective paths 0-3, then, the numbers of paths 0-3 and the machine numbers of an IOD 3 (0) - 3 (n) are outputted from a MPX 8, successively written and stored to the address of a memory circuit 5 designated. The MPX 8 successively outputs the output from a usual writing counter 7 to the memory circuit 5 as a writing address, and when the IOC 1 receives an idling signal IDL which outputs during the next control processing action waiting in the idling condition, the output is read and changed over to a counter 6 side. Namely, during the period, the writing data on the address of the memory circuit 5 designated by the reading counter 6 are successively read. A control part 4 in the IOC 1 executes the interruption control for the final status report in accordance with the order read from the memory device 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention prioritizes unreported execution completion statuses corresponding to input/output commands issued from a host device through a path to an input/output device, starting from a path with a long waiting time. It relates to an input/output control device for processing.

As the usage of information processing systems has become more sophisticated and complex, the processing efficiency and operational efficiency of system control have become more demanding.

For example, a system configuration in which input/output devices (e.g., storage devices such as magnetic tape devices) are controlled by multiple (e.g., 4 or 6) central processing units (hereinafter referred to as CPUs) has been put into practical use. However, in the case of such a system configuration, system control becomes more sophisticated and complex, and the processing efficiency and operating efficiency of system control are pursued more strictly.

Generally, a plurality of input/output devices (hereinafter referred to as IOD) are connected under an input/output control device (hereinafter referred to as 10C). In addition, the IOC has a CPU-compatible path for transferring control signals and data to and from the CPU.
Control commands for control commands and command completion reports for control commands (
The final status report (also known as the final status report) is conducted through this path.

Further, since instructions from a plurality of CPUs are issued asynchronously, the IOC controls the plurality of instructions and causes the 100 to execute them. For example, when input/output commands for multiple 100s are issued from multiple paths, each TOD reports execution command completion, that is, final status report, through the path that received the command. In order to do so, it is necessary to efficiently control such final status reporting.

[Prior art and problems to be solved by the invention] FIG. 2 shows a diagram of an input/output control system.

The system shown in Figure 2 is TOD3 (0
)~1003 (n) to four CPIJ2(0)~C
It is controlled through path O to bus 3 from PIJ2(3).

For example, from CPU2 (0) to 1003 through path 0
Assume that an input/output command is issued for (0). still,
The input/output command here means a detachment command.

Also, the disconnection command is l0D3 (0) ~l0D3
This is a command in which l0C1 reports the final status via path θ to bus 3 in response to an interrupt from (n).
For example, a rewind operation is a target of this command.

The CPU 2 (0) uses software to monitor the time from when an input/output command is issued until the final status is reported in units of paths θ~3. Also, l0CI is the other path 1
It also accepts similar input/output commands, write/read commands, etc. from 3 to 3, and performs control according to the commands.

On the other hand, instructions issued from CPU2 (0) to CPII2 (3) have processing priority depending on the degree of urgency. For example, there are various instructions that are processed immediately after the instruction is issued, and The final status report for a command) belongs to a lower priority.

Therefore, for example, under the control of the control unit 4 in the l0CI, a timeout may occur depending on the situation while another command with a higher priority is processed and the final status report is performed, and the final status report cannot be made, which is recognized as a failure by the l0CI. occurs.

In particular, since the final status report is processed on a voluntary basis,
Paths 0 to 3 with a long elapsed time for which the final status has not been reported for input/output commands (disconnection commands) are not necessarily processed first. has the problem that it may time out and be terminated.

[Means for solving problems]

The present invention aims to realize a new input/output control device that solves the above problems, and the problems are as follows.
A storage means for storing the time at which an input/output command was instructed in the input/output device is provided for each of the plurality of passes, and the progress is stored in the storage means between the passes where the execution completion status for the input/output command has not been reported. This problem is solved by the input/output control device according to the present invention, which compares time lengths and interrupts and reports the execution completion status in order of the longest stored time length.

[Effect]

That is, the time at which an input/output command was issued for each path is memorized for each bus, and priority is given to the path that has been kept waiting the longest among buses that have not yet reported the final status for the input/output command. The final status is controlled to be reported based on the priority order to prevent a path with a long waiting time from timing out.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 1 shows a block diagram of an embodiment of an input/output control device according to the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Next, the operation of this embodiment will be explained. In this embodiment, it is assumed that a subsystem having four paths O to 3 as shown in FIG. 2 is configured.

When 10CI receives an input/output command (disconnection command) through each path O~3, the number of the path O~3 at that time and 10
Machine numbers from 03(0) to 3(n) (for example, #0 to #N)
are outputted from the multiplexer 8 (hereinafter referred to as MPX8), and sequentially written to and stored in designated addresses of the memory circuit (RAM) 5.

The MPX8 normally outputs the output from the write counter 7 as a write address to the memory circuit 5 in sequence, and outputs the output while waiting for the next control processing operation when the 10C1 is in an idling state, that is, in a state where no actual control processing is being performed. When receiving the idle signal IDL, the output is switched to the read counter 6 side.

That is, in the waiting period for the next control processing operation (this period becomes the period in which the final status can be reported), the write data (numbers of paths 0 to 3 and l0D3 ( 0) to 3(n) machine numbers) are read out sequentially. Further, the control section 4 in the l0CI performs interrupt control for final status report according to the order read out from the memory circuit (RAM) 5.

For example, if 1003 (0) of path O is read first, path 0 on the output side of memory circuit (RAM) 5 is set to "l", output sides of paths 1 to 3 are set to "0", and the path θ~ By specifying the priority of 3 and reading the OD machine number as #0, the final status report from 1003 (0) through path 0 is processed with the highest priority, and cpU2 (0
) also recognizes that there is a final status report interrupt, giving priority to path 0.

In this way, the order of the addresses specified by the read counter 6 becomes the priority order of the final status report, and the final status report is made in order, and the counter value of the write counter 7 and the counter value of the successive counter 6 are compared in the comparator circuit 9. If they match, the comparison circuit 9 outputs a predetermined signal to the control unit 4, and the final status report is completed.

Further, the predetermined signal outputted from the comparison circuit 9 is sent to the write counter 7 and the read counter 6, and resets the respective counter values.

〔Effect of the invention〕

According to the present invention as described above, by prioritizing interrupts from paths that have been waiting for a final status report for a long time, it is possible to prevent the software of the central processing unit from timing out due to a long waiting time for not reporting the final status. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an input/output control device according to the present invention, and FIG. 2 is a diagram of a human output control system. In the figure, l is IOC, and 2(0) to 2(3) are CPUs. 3(0) to 3(n) are roo, 4 is a control unit, 5 is a storage circuit, 6 is a read counter, 7 is a write counter, 8 is MPχ, and 9 is a comparison circuit, respectively. Figure j

Claims (1)

[Claims] A device that has a plurality of paths for receiving and receiving signals from a plurality of higher-level devices, receives commands from the plurality of higher-level devices through the paths, and controls a plurality of connected input/output devices. A storage means is provided for each of the plurality of passes to store the time at which an input/output command is instructed in the input/output device, and the history is stored in the storage means between the passes in which the execution completion status for the input/output command has not been reported. An input/output control device characterized in that time lengths are compared and the execution completion state is reported by interrupt in order of the longest stored time length.