JPS61195127U - - Google Patents
Info
- Publication number
- JPS61195127U JPS61195127U JP5900985U JP5900985U JPS61195127U JP S61195127 U JPS61195127 U JP S61195127U JP 5900985 U JP5900985 U JP 5900985U JP 5900985 U JP5900985 U JP 5900985U JP S61195127 U JPS61195127 U JP S61195127U
- Authority
- JP
- Japan
- Prior art keywords
- input
- logic gate
- output terminal
- terminal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5900985U JPS61195127U (sk) | 1985-04-19 | 1985-04-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5900985U JPS61195127U (sk) | 1985-04-19 | 1985-04-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61195127U true JPS61195127U (sk) | 1986-12-05 |
Family
ID=30585035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5900985U Pending JPS61195127U (sk) | 1985-04-19 | 1985-04-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61195127U (sk) |
-
1985
- 1985-04-19 JP JP5900985U patent/JPS61195127U/ja active Pending
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