JPS61190969A - Semiconductor integrated circuit microprocessor - Google Patents

Abstract

PURPOSE:To vary and add the functions of circuits easily by executing a layout in which a comparatively fixed circuit, which is hardly changed functionally, and a circuit easy to be functionally altered additionally are separated in the longitudinal or lateral direction in a chip. CONSTITUTION:A layout method in which the whole layout of a chip is divided into two to the left side and the right side as represented by a chain line 315 and the whole is divided into two to upper and lower sections by control circuits 303 and 308 as represented by a chain line 316 is adopted. The left side of the chain line 315 is laid out by circuits, functions thereof are hardly changed, [a command decoder circuit 301, a micro-program ROM 302, an arithmetic operation (command) execution control circuit 303 and an arithmetic operation (command) execution circuit 304], and the right side of the chain line 315 is laid out by circuits, additional functions thereof are easy to be altered, (command control systems 305-308 and input/output control systems 309 and 310). Since layouts on the left and right sides of the chain line 315 mutually have no effect, layouts can be executed completely independently, and the method is extremely advantageous.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an optimal layout method within a chip in an LSI such as a microprocessor.

[Background of the invention]

In general, when it comes to manufacturing semiconductor LSIs, advances in microfabrication technology have led to high-density packaging, and in-chip layouts have been changed to make signal lines (polysilicon or first grade metal wiring) as short as possible to increase speed. Ingenuity. Based on this idea, a layout method for a MOS-LSI microprocessor as shown in FIG. 1 has been proposed in the prior art, for example, in US Pat. . In Figure 1, each rectangular frame (112 to 152) is a circuit block with a unit function, and the blocks are laid out densely along the signal flow n as shown by the arrows. There are n. However, with the conventional method shown in Figure 1, when adding a new functional circuit with higher microprocessor performance, there is no room for interrupts in the layout, and the layout must be completely changed. It has its drawbacks. For example, FIG. 2 shows a microprocessor circuit related to the layout of the present invention described later, which includes the conventional microprocessor functions shown in FIG. 1, but FIG. 2 shows an additional circuit 20 not shown in FIG.
6 O-0(Operand-Cache-0hac
he; associative memory), 207 ■-O (In5tru
ction-Cache), 211 μm ROM
(Micro-Program ROM). These additional circuits are a method used as a means to increase the high-speed performance of a microprocessor.

In this way, the layout method in Fig. 1 is similar to 206 in Fig. 2.
．． If there are additional circuits 207 and 211, there is no room for interruption at all in terms of layout, and normally the entire layout must be changed.

[Purpose of the invention]

An object of the present invention is to provide a basic layout method common to general microprocessors that allows for easy modification and addition of circuit functions, in order to solve the problems in the conventional microprocessor layout method as described above. This is what we tried to provide.

[Summary of the invention]

The basic feature of the present invention is to perform a layout in which a relatively fixed circuit whose functionality is rarely changed and a circuit whose functionality is easily added and changed are separated vertically or horizontally within a chip. The basic layout is extremely flexible and meets the above objectives.

[Embodiments of the invention]

Embodiments of the present invention are shown in FIG. 3 below, and FIG. 2 and xi
A comparative explanation will be given using figures.

FIG. 3 is a microprocessor layout diagram of the present invention. Fig. 2 is a circuit configuration diagram of Fig. 3.
Figure @3 (and Figure 1) will be explained from the figure. In Figure 2, most of each block circuit is a common bus line 201 within the chip.
(address bus) and 202 (data bus).

The input/output buffer circuits 203 and 204 are connected to 311 (
124, 120, and 130) in FIG. Second
In the figure, the interrupt signal and input/output signal control circuit 205 is located at 309 in FIG. 3 (138, 142, and 152 in FIG.
In the figure, the cache memories 206 and 207 are replaced by 310 and 307 in FIG. 3 (not shown in FIG. 1), and the instruction register 208 and its control circuit 209 in FIG.
06, 308 (146, 148, 150 and 1 in Figure 1)
42), the instruction decoder circuit 210 in FIG. 2 is located at 301 in FIG. 3 (144 in FIG. 1), and the microprogram 0M211 in FIG. 2 is located at 302 in FIG. 3 (not shown in FIG. 1).
In FIG. 2, the arithmetic execution circuit 213 and its control circuit 212
are 304 and 303 in Figure 3 (322.128 in Figure 1,
134 and 136), and the clock pulse generation circuit 214 in FIG. 2 corresponds to 312 in FIG. 3 (140 in FIG. 1).

Now, compared to the conventional layout shown in FIG. 1, the layout of the present invention shown in FIG. 3 has two main features.

The first is a layout method in which the overall layout of the chip is divided into two on the left and right as represented by a chain Is 315, and the second is a layout method in which the entire layout of the chip is divided into two on the left and right, as represented by a chain Is 316.
In 08, the layout method is to divide the entire layout into two, top and bottom. The first feature is that the left side of the chain line 315 is laid out with circuits with few changes in function (instruction decoder circuit 301, micro program ROM 302, arithmetic (instruction) execution control circuit 303, and arithmetic (instruction) execution circuit 304). The circuit on the right side is easy to change functions (
The layout consists of the instruction control system 305 to 308 and the input/output control system 309 and 310). The advantage of this layout/out method is that the layouts on the left and right sides of the chain line 315 do not affect each other, so the layouts can be completely independent, which is very advantageous. The circuit layout can be expanded to the right of the chain line 315 depending on the size of the circuit function. Therefore, the layout method is very clear, the design is easy, and the development time is shortened (
Incidentally, in the conventional layout method shown in FIG. 1, the overall layout cannot be determined until the entire circuit is determined, and it is expected that the design and development time will be longer. ). Next, the second feature mentioned above is that the control circuits 303 and 308 (or 309
may be included. ) is mainly composed of random logic (irregular logic) circuits, and you do not need to worry much about the layout shape, whereas other circuits (301 to 312
) That is, registers, arithmetic circuits, ROM%PLA (Pro
When a regular circuit such as a grammable logic array (grammable logic array) is laid out in a regular shape, the layout area becomes smaller. However, in this case, the layout size of each rule circuit will be different, so it is necessary to adjust the overall layout. In FIG. 3 of the present invention, the control circuits 303 and 308, which are irregular circuits as described above, are connected to the center dashed line 311 of the overall chip layout.
The shape of the layout is adjusted so that it is consistent with the following.

According to this layout method, the layout of each of the above-mentioned regular circuits can be relatively freely arranged vertically in two directions along the chain line 316 in the figure.
Since the layout can be done relatively freely in the direction of division, layout design becomes easier and the development period can be shortened.

〔Effect of the invention〕

According to the layout method of the present invention, it is easy to add and change circuit functions, the layout shape of the regular logic circuit is relatively free, and the layout of the entire FFC chip can be easily developed in a short time. .

[Brief explanation of drawings]

FIG. 1 is an overall chip layout diagram of a conventional microprocessor, FIG. 2 is a circuit diagram of a microprocessor related to the present invention, and FIG. 3 is an overall chip layout diagram of a microprocessor according to the present invention. 301... Instruction decoder circuit, 302... Micro program ROM, 303... Control circuit for the operation execution circuit 304, 304... Operation execution circuit, 305.306.
...Instruction register circuit, 307...Instruction cache (associative memory), 308...305.306 control circuit,
309...I/O signal control circuit, 310...Operand cache (associative memory), 311...I/O signal buffer circuit, 312...Clock pulse/ll/l/(1/llr/ X) Ward 3 31ri

Claims (1)

[Scope of Claims] 1. An instruction execution circuit whose main circuit is a data storage circuit and a group of numerical calculation circuits, an execution control circuit that controls this instruction execution circuit, and an instruction decoder circuit that generates input signals for the execution control circuit. and a ROM (Read Only) that generates microinstruction signals that assist the instruction decoder circuit.
A first circuit group including at least one of the above-mentioned instruction execution circuit, execution control circuit, instruction decoder circuit, and ROM, in which at least one of the memory) circuits is arranged in the vertical or horizontal direction of the chip, and includes at least one of the instruction execution circuit, execution control circuit, instruction decoder circuit, and ROM. A semiconductor integrated circuit microprocessor characterized by employing a layout method in which a second circuit group having an instruction data storage circuit, a clock generation circuit, an input/output signal control circuit, etc. and a chip can be divided into two in the vertical or horizontal direction. . 2. In the overall layout of the chip, a control circuit mainly consisting of irregular logic circuits was used, and other regular circuits such as memory and arithmetic circuits were divided into two in the vertical or horizontal direction of the chip. A semiconductor integrated circuit microprocessor according to claim 1, characterized in that: