JPS6118989B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting the frequency of an electrical signal.

Conventionally, as a method for detecting the frequency of a pulse signal, for example, a reference clock pulse having a period longer than that of the pulse signal to be detected is prepared, and the pulse signal generated during one period of the reference clock pulse is calculated. A device that obtains a count value according to the frequency of the pulse signal, and a reference clock pulse having a shorter period than the pulse signal to be detected is prepared, and the reference clock pulses generated during one period of the pulse signal are counted. In this way, a count value corresponding to the period of the pulse signal is obtained, and then the reciprocal of the count value is obtained to find the frequency. Here, in the above method, the resolution is determined by the reciprocal of the period of the reference clock pulse; for example, if the period of the reference clock pulse is 1 second, the resolution is 1 Hz, and if the period of the reference clock pulse is 0.1 second, the resolution is 10 Hz. Become. Therefore, for accurate detection, the period of the reference clock pulse should be made longer. However, in this method, the value obtained is the average frequency over one period of the reference clock pulse, so as the period of the clock pulse becomes longer, it becomes impossible to detect small changes in frequency (that is, the response deteriorates), and as a result, the resolution decreases. However, it was not possible to achieve both the above and the responsiveness. In addition, in the above method, the frequency of each individual pulse of the detection target pulse can be known, so the responsiveness is good.
Furthermore, by shortening the period of the reference clock pulse, the resolution can be improved as much as possible, and both resolution and responsiveness can be satisfied, but the circuit for converting the count value tends to be complicated and expensive. There was a drawback.

This invention was made in view of the above points,
By combining the above-mentioned methods, the present invention aims to provide a frequency detection device that does not require a complicated reciprocal conversion circuit and has both resolution and responsiveness.

According to this invention, the period of the pulse to be detected is first measured by the method described above, and based on the period information, a pulse signal having a frequency several times that of the pulse to be detected is generated. The frequency is determined by counting the pulse signals using the method described above. That is, in this invention, by using the final method, there is no need for a complicated reciprocal conversion circuit, and by using the method, the frequency of the pulse signal to be detected can be multiplied several times, and then counting can be performed using the method described later. Therefore, it is possible to perform high-resolution detection even if the time per processing is shortened (that is, even if the responsiveness is improved) compared to counting using the original method.

The present invention will be described in detail below based on an embodiment of the accompanying drawings.

In FIG. 1, an input pulse P is a frequency detection target signal in the present invention, and is, for example, a pulse as shown in FIG. 2a. This input pulse P is input to the one-shot circuit 1, and in synchronization with its rising edge, the waveform is shaped into a constant pulse width as shown in FIG. 2b. Further, the output pulse of the one-shot circuit 1 is further applied to the one-shot circuit 2, which generates a pulse as shown in FIG. 2c in synchronization with the falling edge of the one-shot circuit 2.

The reference clock generator 3 is a circuit for generating a reference clock pulse cp of a constant frequency, which is used as a reference clock for detecting the frequency of the input pulse P in the present invention. To be more specific, the reference clock pulse cp is a reference pulse for executing the above method (detecting the period of the input pulse P) on the input pulse p, and based on the execution result, the reference clock pulse cp is It is a reference pulse for creating a pulse with a frequency, and furthermore, the frequency of the input pulse P is finally detected by performing the above method on a pulse having a frequency several times that of the created input pulse P. It is also the reference pulse for This reference clock pulse CP is, for example, a pulse having a considerably higher frequency than the input pulse P, as shown in FIG. 2d.

First, detection of the period of the input pulse P will be explained.

The reference clock pulse cp generated from the reference clock generator 3 is frequency-divided by 1/N by a frequency divider 4 and applied to the count input of a counter 5. The output pulse of the one-shot circuit 2 is applied to this counter 5 as a reset signal. Therefore, counter 5
counts the reference pulse cp1 generated from the frequency divider 4 during one period of the input pulse P. Specifically, the frequency of the input pulse P is F _p and the period is T _p (=1/F _p ), the frequency of the reference clock pulse cp is F _cp and the period is T _cp , and the frequency division of the frequency divider 4 is When the ratio is N, the count value C ₅ of the counter 5 in one period of the input signal P becomes C ₅ =T _p /T _cp ·N −(1). The count value _C5 of this counter 5 is written into the latch circuit 6 by the output pulse of the one-shot circuit 1 immediately before the counter 5 is reset. Therefore, the latch circuit 6 stores the cycle information of the input pulse P one cycle before.

A comparator 7 and a switch 8 to which the outputs of the counter 5 and latch circuit 6 are individually applied select one value depending on the magnitude relationship between the memory content _C5 of the latch circuit 6 and the ever-changing count value of the counter 5. Although this will be described later, the following explanation will be given assuming that the stored content _C5 of the latch circuit 6 is directly applied to the comparator 9 via the switch 8.

The comparator 9 generates a pulse having a frequency several times that of the input pulse P. That is, the counter 10 counts the reference clock pulse CP and adds the counted value to the comparator 9, and the comparator 9 uses the counted value of the counter 10 as the content stored in the latch circuit 6.
When it matches _C5 , it outputs a match pulse Pn. The comparator 9 applies this coincidence pulse Pn to the counter 10, and resets the counter 10 every time the counted value of the counter 10 matches the stored content _C5 of the latch circuit 6. Here, if the time required for matching is _T2 , the count value _C5 becomes _C5 = _T2 / _Tcp- (2). Therefore, the time T ₂ is T ₂ =C ₅ ·T _cp -(3), and by substituting the above equation (1) into this equation, it becomes T ₂ =T _p /N - (4). Therefore, if the frequency of the coincidence pulse Pn is F ₂ , then F ₂ =1/T ₂ =N/T _p =N・F _p −(5), and the frequency of the coincidence pulse Pn is N times that of the input pulse P. I can see that I am getting used to it. In addition, Figure 2 h
shows the coincidence pulse Pn.

Next, detection of the frequency of the input pulse P multiplied by N (execution of the above method) will be described.

The reference clock pulse cp generated by the clock generator 3 is divided by 1/M with a division period of 12.
The one-shot circuit 13 inputs this reference pulse CP2, and shapes the reference pulse CP2 into a constant pulse width in synchronization with its rising edge as shown in FIG. 2J. Further, the output pulse of the one-shot circuit 13 is applied to the one-shot circuit 14, and from the one-shot circuit 14, a second pulse synchronized with the falling edge of the pulse is sent.
A pulse as shown in Figure k is generated. The output of this one shot circuit 14 is applied to the counter 11 as a reset signal. Further, the output coincidence pulse Pn of the comparator 9 is added to the count input of the counter 11. Therefore, counter 11 is frequency divider 1
The coincidence pulse output from the comparator 9 during one cycle of the output pulse cp2 of 2 (i.e., the input pulse P
(pulses with a frequency N times higher than Pn) will be counted. For example, if the frequency division ratio of the frequency divider 12 is M, the count value C ₁₁ of the counter 11 becomes C ₁₁ =T _cp・M/T ₂ −(6), and in this equation, T ₂ is calculated from equation (4) by T ₂ =T _p /N=1/NF _p -(7), and by substituting this into the above equation (6), C ₁₁ =T _cp ·M·N·F _p -(8). The count value _C11 of this counter 11 is set to the latch circuit 1 by the output pulse of the one-shot circuit 13 immediately before the counter 11 is reset.
5 is written. In equation (8), T _cp M N is a constant, so the output of the latch circuit 15 is
Frequency information of the input pulse P updated every cycle T _cp ·M always appears. For example, in the example of Fig. 2, the output of the latch circuit 15 is the number of coincidence pulses Pn (h in the figure) included in the previous processing time T _cp ×M, so it becomes as shown in l in the figure, and eventually , the frequency information of the input pulse P can be obtained with a delay of only about one cycle of the input pulse P.

The output of the latch circuit 15 can be directly converted into a digital signal, or can be sent to a digital-to-analog converter 16.
is extracted as an analog signal via

Next, the functions of the comparator 7 and the switch 8 will be explained.

When the frequency F _p of the input pulse P gradually decreases, its period T _p naturally becomes gradually longer. In this invention, the latch circuit 6 stores the previous cycle, and this memory is not rewritten until the next pulse P is input.
When the period T _p of the input pulse P gradually becomes longer, a gap occurs between the period stored in the latch circuit 6 and the actual period T _p of the input pulse P. Therefore, when the period T _p of the input pulse P gradually increases in this way, the period T p of the actual input pulse P
When _p becomes longer than the previous cycle stored, it is more accurate to provide actual cycle information than to continue to provide the previous cycle information. Therefore, the comparator 7 compares the outputs of the counter 5 and the latch circuit 6, and if the content of the counter 5 is smaller than the content of the latch circuit 6, the comparison output SC
(shown in Figure 2 f) is set to "0" and the output of the switch 8 is connected to the output of the latch circuit 6. Conversely, if the content of the counter 5 is greater than the content of the latch circuit 6 (the current cycle is (when the period becomes longer than the cycle), the comparison output SC is set to "1" and the output of the switch 8 is switched to the output of the counter 5. For example, in Fig. 2, the period T _p of the input pulse P becomes shorter from section A ₂ to section A ₃ , so the comparison output
SC (f in the figure) remains at "0" and the output of the switch 8 is switched to the output of the latch circuit 6 as shown in g in the figure. However, the period T _p of the input pulse P tends to become longer from section A ₃ to section A _4. Therefore, at the beginning of _section A ₄ , the switching device 8 However, when the contents of the counter 5 become larger than the contents of the latch circuit 6 at a certain point, the comparison output SC of the comparator 7 rises to "1" as shown in FIG. As a result, the switching device 8
The output of is switched to the output of the counter 5 as shown in FIG. Therefore, in this case, the time required for the output of the switching device 8 and the output of the counter 10 to match in the comparator 9 gradually becomes longer, and the period of the matching pulse Pn also increases as shown in FIG. 2h.
As shown in the figure, the length gradually increases, and the latch circuit 15
The frequency information obtained from the digital-to-analog converter 16 gradually decreases as shown in FIG. 2l and m. In FIG. 2m, the broken line represents frequency information obtained when the output of the latch circuit _C5 is always applied to the comparator 9 without providing the switching function as described above. and from section A ₄ to section A ₅
As the counter 5 is reset, the comparison output SC falls to "0" again, and the output of the switch 8 is switched to the output of the latch circuit 6 (the final value of the counter 5 in section _A4 ).

As explained above, according to the present invention, first, a pulse is generated by multiplying the frequency of the input signal, and the number of pulses is counted at a certain reference time to obtain frequency information of the input signal.
Even if the same reference pulse is used, the resolution is relatively improved compared to the method of directly counting the input signal to obtain frequency information. Therefore, even if the period of the reference pulse is shortened to some extent (that is, even if the response is improved), frequency detection can be performed with high resolution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of FIG. 1. 1, 2, 13, 14... one shot circuit, 3
...Reference clock generator, 4, 12... Frequency divider,
5, 10, 11... Counter, 6, 15... Latch circuit, 7, 9... Comparator, 8... Switch, 16
...Digital-to-analog converter.

Claims (1)

[Scope of Claims] 1. A first counter that receives a frequency detection target signal and counts first reference pulses of a predetermined period generated within one cycle of the input frequency detection target signal; the first counter; a storage circuit that holds the count value for the next cycle of the frequency detection target signal; a switching circuit that compares the count value of the first counter with the value stored in the storage circuit and selects the larger value; a second reference pulse having a period of 1/N of the first reference pulse;
a second counter that counts reference pulses; and a comparison circuit that compares the value selected by the switching circuit with the count value of the second counter, and outputs a matching pulse each time they match to clear the second counter. and a third counter that repeatedly counts the coincidence pulses generated within a predetermined reference period, and obtains frequency information of the frequency detection target signal based on the count value of the third counter. .