JPS61189719A - Non-cyclic digital filter - Google Patents

Abstract

PURPOSE:To reduce an error of quantization by adding a constant 2L to the output of a digital filter when the number of taps of the digital filter is set at K with the arithmetic word length set at L bits respectively. CONSTITUTION:A constant generator 6 which produces a constant 2LK(1/2L) consisting of the number of taps K and the number of arithmetic bits L of a delay line 3 and an adder 7 which obtains the sum of the output Yi of an adder 5 and a constant K(1/2L) produced from the generator 6 and outputs it to a digital filter output terminal 2 are added to a conventional non-cyclic digital filter (1-dot chain line area). Then the signals supplied to the digital filter from an input terminal 1 are filtered by the line 3, coefficient multipliers 41-4k and the adder 5. This output signal Yi is added with the constant K(1/2L) and this sum Zi is outputted to the terminal 2.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an acyclic digital filter.

[Conventional technology]

The output (real number) Yi of a general acyclic digital filter with K and the number of taps at time l is expressed as follows.

In equation (1), Cj is the coefficient of the j-th tap (real number)
and Xlj is the signal value (real number) of the j-th tap at time 1. Here, the coefficient C' is expressed in two's complement N-bit (including polarity signal) fixed-point format,
Similarly, it is assumed that the signal value Xlj is expressed in M-bit double complement format and fixed point format. In this case, the product CJXij of the coefficient Cj and the signal value XiJ is (N+M−
1) It will be expressed in bits. If this is expressed as L bits (L(N+M-1)) by truncating, a quantization error Δj will occur.This quantization error generally has a probability density function P(Δj) as shown in Figure 2. Therefore, the average value Δj and the variance Δjt of the quantity difference Δj are expressed as in the following equation.

and is a constant that does not depend on the tap position j.

Since the above-mentioned quantization error Δj appears in the multiplication output at each tap (−), a quantization error occurs in the output of the digital filter.Here, the quantization error Δj for each tap is a general Since there is no correlation with
Digital filter quantization error Δ; to Δj
・・・・・・・・・(5)=-ix(1-+-
3K)Σ72 ・・・・・・・・・(6)(5
) and (6), it can be seen that the mean-factor-variance II 14 becomes smaller as the number of bits increases and as the number of taps K decreases.

[Problem that the invention seeks to solve]

In this way, in conventional acyclic digital filters, the quantization error Δ whose average and variance are shown in equations (5) and (6), respectively, occurs at the digital filter output due to the truncation operation of the multiplication results. It had some problems.

In addition, the larger the number of taps K of the digital filter, the larger the quantization error Δ, so when using a digital filter with a large number of taps, the operation word length (L bits) must also be increased in order to reduce the quantization error Δ. It needed to be bigger.

An object of the present invention is to improve the above-mentioned problems and provide an acyclic digital filter with small quantization errors.

[Means for solving problems]

First, the present invention will be explained in detail.

As can be seen from equation (5), it is thought that the quantization error Δ of the output of the digital filter has a distribution biased toward the negative side by Ki. Therefore, consider adding 7' to the output of the digital filter (2).

This value has the number of taps and the number of bits as parameters, but the number of taps and the number of bits can be set to certain specific values in each digital filter. If the quantization error of the output of the digital filter L filter to which this constant K is added is E, then E=Δ0Kg
・・・・・・・・・(7) Therefore, this quantity is the mean E and variance E of 1 difference E! is the following = O...
(8) From equations (9) and (6), the output of the digital filter has a constant of 0, the variance is the conventional value, +3K, and the quantization error is reduced.

The acyclic digital filter of the present invention has an L adder which adds a constant K to the sum of each multiplication result truncated to L bits, where K is the number of taps of the delay line.

〔Example〕

Examples of the present invention will be described.

FIG. 1 is a block diagram showing an embodiment of an acyclic digital filter according to the present invention. This embodiment has a digital filter input terminal 1 and taps T1 to TK, and is connected to a delay line 3 and taps T1 to Txl2, which output signals Xl to XIK from each tap T, to TK, and has a coefficient of C1. -Coefficient multiplier 4, which is CK. ~4 and these coefficient multipliers 4. ~4 each output C1X1. Adder 5 that adds up CK Output Yi of generator 6 and adder 5 and constant generator 6
The digital filter output terminal 2 (equipped with an adder 7 that outputs two outputs) takes the sum Zi of the constant generated by 7r and 7r.

Next, the operation of this embodiment will be explained.

The signal input to the digital filter from input terminal 1 is filtered by delay line 3, coefficient multipliers 41 to 4, and adder 5, and the output signal yt is filtered by adder 7 (=therefore, by constant generator 6). = is added to the generated constant, and this sum Zi is output to the digital filter output terminal 2.

〔Effect of the invention〕

As explained above, the present invention has the effect of reducing quantization errors by adding the constant K to the output of the acyclic digital filter.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an acyclic digital filter according to an embodiment of the present invention, and FIG. 2 is a diagram showing a probability density function of quantization error. 1......Digital filter input terminal 2...Digital filter output terminal 3...Delay line 4,~
4K...Coefficient multiplier

Claims (1)

[Claims] It has a delay line that delays an input signal expressed in two's complement format and fixed point format and outputs the signal from a plurality of taps, and has a two's complement number that is preset for each tap. An acyclic digital signal that multiplies the signal from each tap by each coefficient expressed in fixed-point format, rounds down these multiplication results to a predetermined number of bits, adds them together, and uses this sum as the output signal. In the filter, the number of taps of the delay line is K, and the predetermined number of bits is L.
An acyclic digital filter comprising: an adder that adds a constant K (1/2^L) to the output signal, and outputs the addition result of the adder.