JPS6118782B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital arithmetic control device, and more particularly to a digital arithmetic control method for correcting truncation errors during integer arithmetic.

In a feedback control system that performs digital calculations, calculation errors caused by truncation or loss of digits caused by integer calculations become a particularly serious problem when calculations such as division or integration are performed in subsequent stages.

As an example of a conventional digital arithmetic device, an example of a first-order delay element arithmetic device is shown in FIG. In the figure, x is an arbitrary input signal value, z is a feedback signal value, 20 is a subtracter that forms a deviation value between x and z, and 10 is a subtracter that forms the deviation value ε ₁ , which is the output of 20, by an arbitrary coefficient G _1. A divider 21 is the output of 10, which is the quotient _ε2 after division and the feedback signal value z.
y is the output value of 21, and 30 is a memory for forming z from y.

In addition, Fig. 2 shows the response characteristic B of y when a step input is applied to x in the conventional method shown in Fig. 1, and the theoretical value A of y of z when the calculation in Fig. 1 is performed with real numbers. This is what is shown.

As is clear from the comparison in FIG. 2, when a digital arithmetic device that mainly performs integer operations performs digital operations that have division and addition functions in the feedback loop as shown in FIG. Since the remainder at the time of division is rounded down in the case of integer operations, the value of y, which is the final operation result, reaches y = x - (G ₁ - 1) = z, and the deviation value ε ₁ , which is the output value of 20. Since ε ₁ = (G ₁ - 1) < G ₁ , the quotient ε ₂ which is the output of 10 will always be ε ₂ = (G ₁ - 1)/G ₁ = 0 after this point, and the value of y is Even if the number of operations increases, it will no longer increase.

Therefore, the error Δε between the calculation result y and the true value is given by Δε=x−(G ₁ −1)/x×100(%), so the calculation error Δε
has the disadvantage that it increases as x becomes smaller and G ₁ becomes larger.

Therefore, in order to improve the calculation accuracy, as shown in Figure 3, the input value x is multiplied by G ₀ and the calculation shown in Figure 1 is performed using the value
A method is adopted in which the output y is obtained by multiplying y′ again by 1/G ₀ . And usually at this time, x and
The relationship between x' is such that if x is a number with a length of 1 word, then x' obtained by multiplying _{by 0} will be a number with a length of 2 words.
G ₀ is set. (Hereafter, this method will be referred to as the double-precision calculation method.) However, even when using this double-precision calculation method, the relationship between x' and y' in FIG.
Since the relationship between and y is the same, the effect of truncation error when dividing by 10 cannot be completely eliminated. As a result, y' usually increases only up to y'=x'-(G ₁ -1) even in a steady state where the number of calculations has increased. Therefore, the final output value y in steady state is determined by cutting off the remainder when divided by 50, so y=y'/G ₀ =G ₀ x-(G ₁ -1)/G ₀ =x-1≠x becomes.

Therefore, even if the so-called double-length calculation method is adopted in which the calculations shown in Fig. 3 are performed according to the calculation flow shown in Fig. 7, the integer calculation result B will be in a steady state as shown in Fig. 4. also had the disadvantage that the value remains only 1 smaller than the input value x.

This is fine if only the calculation accuracy is a concern, as in the case of Figure 1 or Figure 3 with double-length calculation, but if an integral element is connected at the subsequent stage,
For example, in the case shown in Fig. 5, an adder 20' is provided at the matching point of the output signal y and the step input x, and the difference signal y' is input to the integral element _S1 to obtain the output y''. In other words, y and x should originally match, but if, for example, bits are truncated in the divider 10, y'≠0 even after a certain amount of time has passed. Then, the integral element performs the integration, and finally y'' overflows, and the influence on the next stage becomes large. If only the calculation accuracy is a problem, it is possible to improve the accuracy by using double-length calculations, but this is limited to an error of 1 bit, and even though complex double-length calculations are performed, y ′≠0 and 1
Since a bit error remains, the phenomenon of overflow of y'' due to the integral operation by S ₁ cannot be avoided. Even if y' = 0 exists, it is divisible by the signal of x, for example, by dividing by 10. Generally, y'≠0 only when the numerical relationships are as follows.

SUMMARY OF THE INVENTION An object of the present invention is to improve the drawbacks of the prior art and to provide a digital calculation control method that does not cause errors due to truncation or the like in digital calculations.

The present invention is characterized in that calculation precision is improved by extracting the remainder, which was conventionally discarded during division, and using this as a new feedback signal value.

In other words, the truncation error is detected, the error is fed back and corrected to the input signal, and the correction is performed several times until the output signal matches the input signal.
In some cases, overshoot may occur, but in the end y'=0 as shown in FIG. 5, which has the characteristic of eliminating any adverse effects on the integral element.

FIG. 6 shows one embodiment of the present invention, and in this figure, parts equivalent to those in FIGS. 1 and 3 are given the same symbols and numbers. 15,4 in Figure 6
0 and 31 extract the remainder upon division, 15 is a multiplier, 40 is a subtracter, and 31 is a memory for forming a feedback signal Δx. Also the 8th
The figure shows an example of the input/output characteristics of the present invention shown in FIG. 6, and the same symbols as in FIGS. 2 and 4 are given to the same parts.

The example of the present invention shown in FIG. 6 shows an example of a first-order lag special operation using integer operations. The value z of one operation step before
By performing addition and subtraction with the value Δx before the calculation step, the deviation value ε ₁ ε ₁ =x−z+Δx (1) is formed.

The divider 10 receives this deviation value ε ₁ and performs the calculation ε ₂ =ε ₁ /G ₁ (2). Since the operation in equation (2) is an integer operation, only the quotient at the time of division is obtained for _ε2 , and the remainder is discarded.

Therefore, by using the multiplier 15 and the subtractor 40 and performing the calculation Δx'=ε ₁ -ε ₂ ·G ₁ (3), the remainder upon division by 10 can be extracted from Δx'. This remainder extraction calculation result Δx' is naturally obtained from the remainder after the deviation value ε ₁ has been found, so Δx' is temporarily stored in the memory function 31.
The result is stored in , and used to form a deviation value by 20 as Δx in the next calculation.

Therefore, for example, even if the deviation value ε _1o at the nth operation step becomes 0<ε _1o <G ₁ and the division result by 10 becomes ε _2o =ε _1o /G ₁ =0, the remainder at this time Δx′ _o = Since ε _1o −ε ₂ n×G ₁ = ε _1o is added to the next calculation step, the deviation value ε _1o+1 in the next calculation step is ε _1o+1 = x _o+1 −z _o+1 + ε _1o , the previous remainder ε _1o will increase. As a result, the output value y is in a steady state where x = y as the number of calculation steps advances, that is,
In order to reach ε ₁ = 0, the calculation error seen in the conventional method (i.e., x =
y) can be completely eliminated.
Further, FIG. 7 shows a calculation flow for executing the calculation blocks of FIG. 5.

FIG. 8 shows the response characteristics when a step input is applied to x using the embodiment of the present invention shown in FIG. Curve A represents the response characteristic obtained by real number type calculation. As shown in the figure, the characteristic curve C has a shape that is approximately rounded off from A.
Moreover, in a steady state, the input value is completely equal to the output value, and offset errors in the steady state, as seen in the conventional system, can be completely removed.

Next, as another embodiment of the present invention, FIG. 9 shows an embodiment in which the present invention is processed by so-called computer software. In order for a computer program to extract the remainder during division according to the present invention and to use this value as a feedback signal for the next calculation step, when a normal division instruction is executed, a register for finding the quotient and a register for finding the remainder are required. Therefore, the remainder can be extracted by adding an instruction to temporarily store the contents of the latter register in an arbitrary storage area after executing this division instruction. In addition, in order to retrieve the remainder upon this division as a feedback signal value, the content of the storage area that has already been stored, that is, the remainder, is loaded into the former register, and x and z
This can be easily accomplished by adding two instructions: an addition instruction to add to the deviation value from

The effects of the present invention described above are particularly advantageous when, in a digital arithmetic device, when it is necessary to obtain a control output by an operation in which the result of division is fed back in some way to the input side of the system that requires division, truncation at the time of division is possible. It is possible to minimize the influence of errors and improve the accuracy of the calculation results, that is, the control output.

Another effect is that when the present invention is implemented by software, the method of the present invention is based on single-precision arithmetic, so it can be easily implemented even when the input signal x is double-precision. Furthermore, in the case of the conventional double-precision arithmetic method, if the input signal x is double-precision, the calculation is required to be treated as quadruple-length. As a result, the amount of software has been significantly reduced.
The effects of reducing processing time and increasing accuracy can be obtained at the same time.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the conventional method, Fig. 2 is a diagram showing the characteristics of the conventional method, Fig. 3 is a schematic diagram showing the conventional method, Fig. 4 is a diagram showing the characteristics of the conventional method, and Fig. 5 is a diagram showing the characteristics of the conventional method. When combined with an integral element, FIG.
7 is a flow diagram, FIG. 8 is a diagram showing the characteristics of FIG. 6, and FIG. 9 is an example of a flow diagram. DESCRIPTION OF SYMBOLS 10... Divider, 20... Adder/subtractor for forming a deviation value, 30... Memory for output value feedback, 31... Memory for remainder feedback during division, 15... Multiplier, 40... Subtractor.

Claims (1)

[Claims] 1. In calculation control including digital calculations in which truncation errors occur, a truncation error is detected in the first calculation, the detected truncation error is stored in a storage device, and is stored in the storage device in the next calculation step. A digital calculation control method characterized in that a calculation signal is compensated by reading out a truncation error amount and processing it as one of the input signals.