JPS61187665A - Charge detection circuit - Google Patents

Abstract

PURPOSE:To attain to simplify a circuit, by bringing a clamp switch to a continuity state simultaneously with or prior to the cutting-off of a reset switch. CONSTITUTION:When a reset switch 3 and a clamp switch 7 are brought to a continuity state at time t1, the signal charge of a contact 2 is reset and the sound terminal 6B of a connection condenser 6 is clamped. The switch 3 is cut off at time t2 and reset noise voltage is generated in the contact 2 but, because the switch 7 is in the continuity state, the reset noise voltage appearing at the second terminal 6B of the condenser 6 is rapidly clamped and output signal voltage V0 almost contains no reset noise voltage. The clamp 7 is cut off at time t3 and the clock voltage V1 of CCD changes and the clock voltage V1 applied to the final transmission electrode, to which clock voltage is applied, among transmission electrodes in CCD is returned to the original state at the time t1. By this method, the circuit can be simplified.

Description

TECHNICAL FIELD This invention relates to charge detection circuits, and more particularly to improvements in correlated double sampling circuits.

Background Art Floating diffusion amplifiers (FDs) are generally used for charge detection in CODs.
A) is often used. However, FDA has rear 1st noise. In order to reduce the above reset noise, correlation 2
Heavy sampling techniques are well known.

The operation of the correlated double sampling method is to first turn on the reset switch to reset the stray capacitance, then turn off the reset switch and then turn on the clamp switch to clamp the second end of the connected capacitor. Then, the signal voltage is input to the above stray capacitance, and then the output signal voltage is sampled and held in the sample-and-hold circuit.

Japanese Patent Application No. 58-191197 filed by the present applicant is an earlier application of the present invention.

DISCLOSURE OF THE INVENTION The above correlated double sampling method C is abbreviated as CDS below. ) is FDA reset noise and first stage MOS
Since it can reduce the l/r noise of the amplifier, it is an effective charge detection circuit for COD. However, the drawbacks of the CDS mentioned above are that its circuit configuration and its operation are complicated, and these problems are the reason for the delay in its widespread use. The present invention is to improve the above-mentioned drawbacks of CDS. A specific object of the present invention is to develop a charge detection circuit that does not generate reset noise and has a simple structure and simple operation. The basic feature of the present invention is that in the well-known COD charge detection circuit structure consisting of a stray capacitance, a reset switch, an amplifier, a connecting capacitor, and a clamp switch, the clamp switch is made conductive at the same time or before the reset switch is cut off. shall be. In this way, the reset noise voltage generated in the stray capacitance immediately after the reset switch is cut off is immediately clamped by the clamp switch. An important advantage of the present invention is that the conventional CD
The sample and hold circuit required in S can be omitted. A second advantage of the present invention is that the substantial signal output period can be extended by omitting the sample and hold circuit and by overlapping the operations of the reset switch and clamp switch. This effect is particularly useful in high-speed operating devices such as two-dimensional solid-state image sensors. In one embodiment of the present invention, the above stray capacitance is an output signal line of a one-dimensional or two-dimensional MC)S solid-state image sensor.

As will be explained later, according to this embodiment, the SZN ratio of a one-dimensional or two-dimensional MO9 solid-state image sensor can be improved.

Other features and advantages of the invention are illustrated by the following examples.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cylindrical block diagram of a correlated double sampling circuit disclosed in US Pat. No. 3,781,574. The output contact of CGD I is the first of diffusion junction diode 4.
The first end 2 is connected to the reset switch 3.
The first end of the sense amplifier 5 is connected to the input end of the sense amplifier 5. The output terminal of the amplifier 5 is connected to the first terminal of the connecting capacitor 6, and the second terminal of the connecting capacitor is connected to the first terminal of the clamp switch 7.
and the input end of the amplifier 8. The output terminal of the amplifier 8 is connected to the first terminal of the capacitor 10 and the amplifier 1! via the sampling switch 9. connected to the input end of the

Sampling switch 9 and capacitor 10 constitute a sample and hold circuit. FIG. 2 is a clock voltage diagram of the correlated double sampling circuit of FIG.

A first period 1'1 in which the reset switch operates, a second period T2 in which the clamp switch operates, a third period T3 in which signal charge is transferred from the transfer gate of the COD to the stray capacitance (contact) 2, and a sampling switch 9 in operation. The fourth periods are arranged in order. What should be noted in the conventional correlated double sampling circuit illustrated in FIG. 1 is that the clamp switch 7 is turned on after the reset switch 3 is turned off. As a result, the second end 6B of the connecting capacitor 6 receives and receives the reset noise voltage from the contact 2 during the period from when the reset switch 3 is cut off until the clamp switch is turned on. However, the above reset noise voltage appearing at the second end 6B of the connecting capacitor 6 is not transmitted to the output contact 12 because the sampling switch 9 is cut off. Simplification or speeding up of the configuration and operation of the correlated double sampling circuit shown in FIG. 1 has been required in the field of solid-state image sensing devices. The input voltage sampled and held at the input terminal of the amplifier 11 is the signal voltage immediately before the sampling switch 9 is cut off, and naturally, the thermal voltage (abbreviated as sampling noise) that appears in the capacitor IO when the sampling switch 9 is cut off. )Vt=(KT/C)[
0,5]. ([] specifies an exponential term.) In order to make the above sampling noise 10% of the above reset noise, the capacitance of the capacitor 10 is equal to or larger than that of the junction diode 4. It is necessary to have 00 times the capacity. For example, if the capacitance of junction diode 4 is 0.027PF, capacitor 10
must have a PF of 2.7. By setting the voltage amplification factors of amplifiers 5 and 8 to substantially 1 or more, the capacitor capacity can be reduced. However, since the amplifier 5 is generally built into a COD chip, a MOS source follower amplifier is used, and its amplification factor is 1. In a CCD solid-state imaging device, which is a very important application for CDS, the signal voltage at the contact point 2 is approximately IV or higher, and a large amplification factor cannot be given to the amplifier 8. FIG. 3 is an equivalent circuit diagram of an embodiment of a circuit that solves the above problems of the conventional correlated double sampling circuit, and FIG. 4 is a clock voltage diagram thereof.

FIG. 3 has a structure in which the sampling switch 9, capacitor 10, and amplifier II are omitted from the correlated double sampling circuit of FIG. The amplifier 5 is a two-stage source follower MOS amplifier, the clamp switch 7 is a MOS switch, and the amplifier 8 is a one-stage source follower MOS amplifier. These are built into the same chip as CGDI.

The driver element 5A and load element 5B constitute a first-stage source follower amplifier, and the driver element 5C and load element 5D constitute a second-stage source follower amplifier. Similarly, the driver element 8A and the load element 8B constitute an output source follower amplifier.

The operation of this correlated double sampling circuit will be explained below. At time L1, the reset switch 3 and the clamp switch 7 are made conductive. As a result, the signal charge on the contact 2 is reset and the second end 6B of the connecting capacitor 6 is clamped. Then, at time [2], the reset switch 3 is shut off.

As a result, a reset noise voltage is generated at the contact 2, but since the clamp switch 7 is conductive, the reset noise voltage appearing at the second terminal of the connecting capacitor 6 is quickly clamped, and the output signal voltage Vo is almost the same. Does not include. At time t3, the clamp switch 7 is cut off, and CC
The clock voltage (1) of D changes and signal charges are transferred from CGDI to contact 2.

The clock voltage V1 applied to the last transfer electrode to which a clock voltage is applied among the transfer electrodes of the CCDI is at time t!
to return to its original state. An important feature of this embodiment is that the change in clock voltage VRG at time t2
Due to the conduction of the output contact 8C, there is almost no effect on the output contact 8C. However, reset switch 3 and clamp switch 7 are N-channel MOS) transistors, and C0D
I is an N-channel COD. Of course, it is also possible for the reset switch 3 to become conductive after the clamp switch 7 is completely conductive, or it is also possible for the clamp switch 7 to be conductive at the point where the reset switch 3 is disconnected.

At time L3, the clamp switch is shut off and the CCD
Signal charge transfer from I to contact 2 is started at the same time. However, since the signal charge transfer described above is delayed in time from the shutoff of the clamp switch, there is almost no clamping of the signal voltage.

Of course, it is also possible to cut off the clamp switch in advance. In FIG. 3, amplifier 5 is a two-stage source follower amplifier, and has a voltage amplification factor of about 1. However, the SN ratio can be sufficiently improved by reducing the capacitance of the contact 2 and increasing the capacitance of the connected capacitor. That is, by shutting off the clamp switch 7, a thermal voltage remains at the second end 6B of the connected capacitor.

Now, if the connection capacitor 6 is 0.225PF and the capacitance of the contact 2 is 0.025PF, the reset noise voltage of the clamp switch 7 will be 1/3 of the reset noise voltage of the reset switch 3. Therefore, if the number of reset noise electrons of clamp switch 7 is evaluated (converted) using contact 2, then
It becomes 21 electrons.

In order to reduce 1/r noise, it is preferred that the MOS transistors in each source follower amplifier be of bulk channel type. FIG. 5 is a sectional view of one embodiment of the connection capacitor 6. 5xlO[15] atoms/2 on the surface of the CC P-type substrate
N shadow area 14 of XIO[161 atoms/CC and IO[20
Create N10 region I5 of 1 atom/CC. ■) Insulating film on the shape base and plate 13 surface! Gate electrode 1G is formed via 3A. The two gate electrodes 16 are then used as the second end 6B of the connecting capacitor. This has the advantage that the capacitance of the connected capacitor does not change depending on the signal voltage state. Since a large amount of MOS:g can be used, the area of the connected capacitor can be reduced.

It is also possible to arrange a second gate electrode on the gate electrode 16-A via an insulating film, and connect the second gate electrode of letter L to the first end 6Δ. FIG. 6 is an equivalent circuit diagram of one embodiment of a MOS transfer sensor filed by the present applicant, the details of which are disclosed in Japanese Patent Application No. 58-191197. To explain briefly, the vertical signal line 18 of the MOS transfer sensor is connected to the stop capacitor 19. No.! Transfer gate 20. Bias capacitor 21. Second transfer gate 22. It is connected to a horizontal signal line 25 via a horizontal transfer circuit consisting of a horizontal scanning capacitor 23 and a potential barrier transfer gate 24. The horizontal signal line 25 is reset by the reset switch 3. The amplifier 5, connection capacitor 6, clamp switch 7, and amplifier 8 are the same as in FIG. However, amplifier 5
is a grounded source amplifier with an amplification factor of 2 or more. The horizontal scanning circuit 17 scans the gate electrode of the horizontal scanning capacitor, and the signal charge is transferred from the channel 23 to the horizontal signal line 25 over the potential barrier 24. However, in FIG. 6, only one vertical signal line is shown. Comparing FIG. 6 with FIG. 3, it will be understood that the contact 2 in FIG. 3 is equivalent to the horizontal signal line 25 in FIG. Therefore, it can be seen that the correlated double sampling circuit of the present invention disclosed in FIGS. 31 and 4 can be used in the MOS transfer sensor of FIG. As a result, from the COD of FIG. 3, the reset noise voltage of the horizontal signal line, which has a relatively large proportion compared to the signal voltage, can be removed. For a detailed explanation, please refer to the above-mentioned patent application. For example, VDD is 10V
SVSS+, tOV, and VR are +6V.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing a conventional correlated double sampling circuit, and FIG. 2 is a clock voltage diagram thereof. FIG. 3 is an equivalent circuit diagram of an embodiment of the correlated double sampling circuit of the present invention. FIG. 4 is a clock voltage diagram of FIG. 3. Figure 5
4 is a sectional view of one embodiment of the connection capacitor shown in FIG. 3. FIG. Figure 6
FIG. 1 is an equivalent circuit diagram representing one embodiment of the present invention. Kasumi 4 8/3 p Procedural amendment [spontaneous] 1. Indication of the case 憫J Deju V Kaki d Wada 2007 2qlj6
92, Name of the invention, 萄・旉 4 yo sho 3, Relationship with the case of the person making the amendment Patent applicant address: 3054 CI Hongo, 2-37 Kamisha, Meito-ku, Nagoya City
, Reasons for the amendment order L 5. Number of inventions increased by the amendment 7. Contents of the amendment As shown in the attached document, between the 9th line and the 1st O line of the last page of Specification 11) (i.e. [3. Inventions -1, the following explanation will be added after the last line of ``Detailed explanation of CDS''.The advantages of the present invention are summarized as follows.The first tri point is that the sample and hold circuit can be omitted, which simplifies the circuit,
214. Chip cost and power consumption can be reduced. The sample-and-hold circuit, which operates at high speed, requires a high-speed analogue amplifier and a high-power resistance amplifier and capacitor, and its design is different from the conventional cylindrical design. The second disadvantage of the present invention is that the operation period of the sample and hold circuit (sample and hold period) can be omitted, and the clamp circuit can be shut off immediately by shutting off the set switch 7, so the stability period (of the solid-state image sensor) To the output field 1
(The period in which 25 or 2 is in a floating potential state with no signal type CI) can be shortened. As a result, the reset period, stability period, and signal output period can be extended.
The design of the clock circuit becomes simple and the operation of each circuit becomes stable. The third advantage is sampling noise (high frequency aliasing noise) that occurs when the sample and hold circuit is cut off.
can be removed. Additional description of the embodiments illustrated in the drawings is provided below. In the COD solid-state image sensor (or hybrid solid-state image sensor) incorporating the reset noise removal circuit shown in FIG.
The output source follower amplifier 8 is an MO9I-transistor or J-FI', 'I' in which noise must be removed and signal charges travel in the bulk channel region.
(also i, tsIT) is preferably used. In addition, in FIG. 3 or 6, the source follower amplifier 5 or 8 and the voltage amplification amplifier 5 are P-channel type F E
If configured with T, the power supply voltage can be reduced. In FIG. 3, it is of course possible to install the connection capacitor 6 and clamp switch 7 outside. In FIG. 6, when the voltage amplification amplifier 5 is built into the solid-state image sensor, in order to keep the amplification factor constant, the signal voltage 5 fed back from the external downstream amplifier is injected into its source electrode terminal via a resistor. It is preferable that In FIG. 6, when the reset switch 3 and the voltage amplification amplifier 5 are installed externally, it is naturally preferable that the first stage amplifier 5 is a high input resistance amplifier (for example, an I FET amplifier).

Claims (4)

[Claims] (1), comprising a stray capacitance, a reset switch, an amplifier, a coupling capacitor and a clamp switch, the above signal charge is injected, the above stray capacitance is connected to the input end of the above amplifier, and the output end of the amplifier is a first end of the coupling capacitor, and a second end of the coupling capacitor connected to a first end of the clamp switch;
And the above stray capacitance is the first one of the above reset switch.
A charge detection circuit connected to an end of the charge detection circuit, wherein the clamp switch is made conductive at the same time as or before the reset switch is cut off. (2) The charge detection circuit according to item 1, wherein the clamp switch is made conductive at the same time as or before the reset switch. (3) The above coupling capacitor is a MOS capacitor, and the gate electrode disposed on the insulating film is the second end, and the semiconductor surface region under the above gate electrode is the first end. The charge detection circuit according to item 1, characterized in that: (4) The charge detection circuit according to item 1, wherein the stray capacitance is an output signal line of a one-dimensional or two-dimensional MOS solid-state image sensor.