JPS61187383A - Manufacture of semiconductor light emitting element - Google Patents
Manufacture of semiconductor light emitting elementInfo
- Publication number
- JPS61187383A JPS61187383A JP60027844A JP2784485A JPS61187383A JP S61187383 A JPS61187383 A JP S61187383A JP 60027844 A JP60027844 A JP 60027844A JP 2784485 A JP2784485 A JP 2784485A JP S61187383 A JPS61187383 A JP S61187383A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- light emitting
- etching
- substrate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000000206 photolithography Methods 0.000 claims abstract description 8
- 238000000605 extraction Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 238000003486 chemical etching Methods 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 241000102542 Kara Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に半導体発光素子の製造方法の改良に関し特に光
取り出し面の形成に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an improvement in a method of manufacturing a semiconductor light emitting device, and particularly relates to the formation of a light extraction surface.
半導体発光素子は電気、光変換効率が高く、まt1注入
電fif調に工って発光強度の変調が極めて容易に行な
えるところから、近年光フアイバ通信用の光源として実
用化が進められている。GaAs/GaAlAsあるい
uInk/InGaAsP 等の化合物半導体を組成
とするこのような光フアイバ通信用の半導体発光素子に
発光効率を高めるための二重へテロ接合構造t−育して
いる。Semiconductor light emitting devices have high electrical and optical conversion efficiency, and the light emission intensity can be modulated extremely easily by modifying the t1 injection current, so in recent years they have been put into practical use as light sources for optical fiber communications. . A double heterojunction structure has been developed in such a semiconductor light emitting device for optical fiber communication, which is composed of a compound semiconductor such as GaAs/GaAlAs or uInk/InGaAsP, in order to increase luminous efficiency.
面発光型発光ダイオードとしてA I G a A s
二重へテロ接合結晶食用い友バラス型発光ダイオードで
は活性層内部で発光した光を活性層Jニジバンドギャッ
プの小さなGaAs 基板で吸収されないように発光
領域近くのGaAs基板を取り除き活性層よりバンドギ
ャップの大きな透明なA jt’ x G aニーx
A sクラッド層(ウィンド層)を通して外部に取り出
している。As a surface-emitting light emitting diode, A I Ga As
In a double heterojunction crystal edible semiconductor type light emitting diode, the GaAs substrate near the light emitting region is removed to prevent the light emitted inside the active layer from being absorbed by the GaAs substrate with a small band gap in the active layer. The big transparent A jt' x G a knee x
It is taken out to the outside through the A s cladding layer (wind layer).
従来光り取り出し面に第2の主表面11に蒸着されり金
属層をフォトリングラフィと化学エッチングにエリ除去
して蕗呈し九半導体基板をホールエツチングすることに
1って設けていた。Conventionally, a metal layer deposited on the second main surface 11 is removed by photolithography and chemical etching to form a metal layer on the light extraction surface, and then a semiconductor substrate is hole-etched.
この工うな従来例では第3図に示す工うにホールエッチ
の深さが40〜60μrn Icお工んでいると深さに
応じて横方向にも半導体基板1がエツチングされ、光取
り出し面90ホール径にエツチング開始前後100μm
φ工りも約2倍近い大きさになりそのため金属層がひさ
し状に形成され、光取り出し面9部分に樹脂をドーム状
にモールドする場合に上記の金属層のひさしに樹脂が垂
れ下がった状態となり、光取り出し面の大部分に完全に
入りにくい欠点が見られた。又、気泡が発生し易くその
気泡粒にエフ発光出力の減少の要因ともなり、さらにぼ
ボンデング時においてひさし部分に荷重を加え7t4合
ベレットを破損する原因にもなっていto
〔問題点を解決するための手段)
本発明の目的に上述の欠点を除去する半導体発光素子を
製造する方法を提供することにある。In the conventional example shown in Fig. 3, the depth of the hole etching is 40 to 60 μrn. When etching the semiconductor substrate 1, the semiconductor substrate 1 is also etched laterally depending on the depth, and the diameter of the hole 90 on the light extraction surface is 40 to 60 μrn. 100 μm before and after starting etching
The φ machining is also about twice as large, and as a result, the metal layer is formed in the shape of an eaves, and when molding resin into a dome shape on the light extraction surface 9, the resin hangs down on the eaves of the metal layer. , the defect that it was difficult for the light to enter completely was observed in most of the light extraction surface. In addition, air bubbles are likely to occur, and these air bubbles cause a decrease in the light emitting output.Furthermore, during bonding, a load is applied to the eaves, causing damage to the 7t4 pellet. An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device that eliminates the above-mentioned drawbacks.
本発明によれば二重へテロ接合構造を有する半導体ウェ
ハー14の第2の主表面に光1vLり出し面を設ける工
程において、N2の主表面に蒸着された金属層に円形パ
ターンとその円形パターンと同心状のド+ナツ型パター
ンとを形成し、円形及びドーナツ型パターン部分に露出
している金属層をエツチングしておき、フォトリングラ
フィ[工って最初の円形パターンのみt−m出させその
部分を選択エッチすることにエフ金属層のひさしを形成
しないで元取り出し面を形成できることを特徴とする半
導体発光素子の製造方法が得られる。According to the present invention, in the step of providing a light 1VL exit surface on the second main surface of the semiconductor wafer 14 having a double heterojunction structure, a circular pattern is formed on the metal layer deposited on the N2 main surface. A concentric dot-shaped pattern is formed, and the metal layer exposed in the circular and donut-shaped pattern portions is etched, and then photolithography is performed to expose only the first circular pattern. A method for manufacturing a semiconductor light emitting device is obtained, which is characterized in that by selectively etching that portion, an original extraction surface can be formed without forming an overhang of the F metal layer.
次に図面を参照して本発明を説明する。 Next, the present invention will be explained with reference to the drawings.
N1図に本発明の一実施例から得られる半導体発行素子
の断面図、第2図に実施例の主要工程の断面概略図であ
る。製造される半導体発光素子はn−GaAsからなる
半導体基板1上にエピタキシャル成長され2n−Alo
Loρa (L 7 A sからなるウィンド層2、P
−Al o、 o a G”0.97ASからなる活性
層3、P−AJ 13 G a (h yAs カラ6
ル閉じ込め/14゜P−AJ、□5Gao、85As
からなる電極形成層5t−もってなる通常工く知ら
れた二重へテロ接合構造と電流性入部開口61Cよって
電流狭窄を行なう已■法からなる絶縁膜7. Or −
kl−Ti −P、t −Au からなるP制電極層
8.光取り出し面9.Au−Ge−Ni 合金からな
るn側電極10から構成されている。FIG. N1 is a cross-sectional view of a semiconductor light emitting device obtained from an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of the main steps of the embodiment. The semiconductor light emitting device to be manufactured is epitaxially grown on a semiconductor substrate 1 made of n-GaAs.
Loρa (wind layer 2 consisting of L 7 A s, P
-Al o, o a Active layer 3 consisting of G"0.97AS, P-AJ 13 Ga (h yAs Kara 6
le confinement/14°P-AJ, □5Gao, 85As
An insulating film 7 consisting of an electrode forming layer 5t consisting of a conventionally known double heterojunction structure and a current confinement method using a current conductive entry opening 61C. Or-
P suppressing electrode layer 8 consisting of kl-Ti-P, t-Au. Light extraction surface 9. It is composed of an n-side electrode 10 made of an Au-Ge-Ni alloy.
本実施例は半導体発光素子の中の発光ダイオードと呼ば
れるものでPII1111L極層9に正、n側電極10
に負の電圧全印加して電流性入部開口6から活性層30
発光領域3aへ電流を注入すると波長約0.85μmの
発光が得られ、その光に光取り出し面10から外部へ取
り出される。This embodiment is a semiconductor light emitting device called a light emitting diode, and a PII1111L pole layer 9 has positive and n side electrodes 10.
A full negative voltage is applied to the active layer 30 from the current entry opening 6.
When a current is injected into the light emitting region 3a, light with a wavelength of about 0.85 μm is obtained, and the light is extracted to the outside through the light extraction surface 10.
本実施例の主安部形放を述べると第2図(N7に示した
。Cりに半導体基板1上へ上記2〜5の各層をエピタキ
シャル成長した後第2図+blに示す通りCVD法にエ
リ絶縁膜7t−約0.3μm堆積してフォトリングラフ
ィと化学エツチングで電流注入部開ロ6t−形成したの
ち真空蒸着法にエリP側電極層8とn側電極1oが設け
である。この時半導体基板1にn側を極10の形成前に
研摩工程で約40〜60μmの厚さにしである。The main ABE shape release of this example is shown in Figure 2 (N7). After epitaxially growing the layers 2 to 5 above on the semiconductor substrate 1, the area is insulated by CVD as shown in Figure 2+bl. After the film 7t is deposited to a thickness of approximately 0.3 μm and a current injection portion opening 6t is formed by photolithography and chemical etching, an edge P side electrode layer 8 and an n side electrode 1o are formed by vacuum evaporation. The n-side of the substrate 1 is polished to a thickness of approximately 40 to 60 μm prior to the formation of the pole 10.
第2図(C)でにフォトリングラフィと化学エツチング
により21E2の主表面110光取り出し面にあたる部
分に直径約100μmφの穴と同心状に内径180μm
φ外径220μmφのドーナツ状の輪を形成して半導体
基板1を露呈しである。第2図(d)に示しであるのは
第2図(C1で形成した面にフォトリングラフィで中心
部分に直径100μmφの穴を目合せして、その部分の
半導体基板lを例えばNH2OH:H2O2(1:30
) 溶液でエツチングして除去した状態である。6g
2図i6)にはフォトリングラフィに用いたレジストヲ
除去し友状態が示されている。In Figure 2 (C), a hole with a diameter of approximately 100 μmφ and a hole with an inner diameter of 180 μm are formed concentrically on the main surface 110 of 21E2 at the portion corresponding to the light extraction surface.
The semiconductor substrate 1 is exposed by forming a donut-shaped ring having an outer diameter of 220 μm. What is shown in FIG. 2(d) is that a hole with a diameter of 100 μmφ is aligned in the center using photolithography on the surface formed in FIG. (1:30
) It has been removed by etching with a solution. 6g
Figure 2 (i6) shows the state after removing the resist used in photolithography.
実施例では第2図(aに示すエリにエツチングにエフ横
波がりした穴の外径にあたる第2の主表面12上には金
属層が除去されており、第2図fe)に示した通り、金
属層のひさし金なくせるため、本実施例から得られる半
導体発光素子は従来例の欠点であうfc。樹脂のモール
ドにおいて、光取り出し面9を先金に包むことができ又
、気泡もた゛まりにくくなり、発光出力の減少を防げる
ことができる。さらにボンデング時に元取り出し部分へ
荷重を加えてペレットを破損する事故もなくなっ九。In the embodiment, the metal layer is removed on the second main surface 12 corresponding to the outer diameter of the hole in which the etched area shown in FIG. Since the overhang of the metal layer is eliminated, the semiconductor light emitting device obtained from this example has fc, which is a drawback of the conventional example. In the resin mold, the light extraction surface 9 can be wrapped in a metal pre-metallic material, and air bubbles are less likely to accumulate, thereby preventing a decrease in light emitting output. Furthermore, there is no longer any accident of damaging the pellet due to applying load to the original part during bonding.
最後に不発明を有する特徴を要約すれば金属層のひさし
が残らないので樹脂のモールド効果を高め光出力の減少
會防ぎ、ボンデング作業ミスをなくせる半導体発光素子
が得られることである。Finally, to summarize the inventive features, since there is no overhang of the metal layer, it is possible to obtain a semiconductor light emitting device that enhances the resin molding effect, prevents a decrease in light output, and eliminates mistakes in bonding work.
第1図に本発明の一実施例から得られる半導体発光素子
の断面図、第2図(a)〜(elrL−実施列にかかわ
る主要工程の断面概略因、@3図は従来例の半導体発光
素子の断面図である。
図中、1・・・・・・半導体基板、2・・・・・・ウィ
ンド層、3・・・・・・活性層、3a・・・・・・発光
領域、4・・・・・・閉じ込め層、5・・・・・・電極
形成層、6・・・・・・電流性入部開口、7・・・・・
絶縁膜、8・・・・・・P側′aL他層、9・・・・・
・光取り出し面、10・・・・・・n側電極、11・・
・・・・f42の主表面、12・・・・・・レジスト、
13・・・・・・金属層のひさし、14・・・・・・半
導体ウエノ〜−1である。Fig. 1 is a cross-sectional view of a semiconductor light emitting device obtained from an embodiment of the present invention, Fig. 2 (a) to (elrL- cross-sectional schematic diagram of the main steps involved in the implementation sequence), and Fig. 3 is a semiconductor light emitting device of a conventional example. It is a sectional view of an element. In the figure, 1... semiconductor substrate, 2... window layer, 3... active layer, 3a... light emitting region, 4...Confinement layer, 5...Electrode forming layer, 6...Current entry opening, 7...
Insulating film, 8... P side 'aL other layer, 9...
・Light extraction surface, 10... n-side electrode, 11...
...Main surface of f42, 12...Resist,
13...Metal layer eaves, 14...Semiconductor wafer ~-1.
Claims (1)
主表面に光取り出し面を設ける工程において前記第2の
主表面に形成された金属層に円形パターンと前記円形パ
ターンと同心状のドーナツ状パターンとを形成し、前記
パターン部分に露出している該金属層をエッチングして
おいて、フォトリソグラフィにより前記円形パターンを
露出し選択エッチングすることにより該金属層のひさし
を形成しないで前記光取り出し面を形成することを特徴
とする半導体発光素子の製造方法。In the step of providing a light extraction surface on the second main surface of a semiconductor wafer having a double heterojunction structure, a metal layer formed on the second main surface includes a circular pattern and a donut-shaped pattern concentric with the circular pattern. The metal layer exposed in the patterned portion is etched, and the circular pattern is exposed by photolithography and selectively etched to form the light extraction surface without forming an eaves of the metal layer. 1. A method for manufacturing a semiconductor light emitting device, comprising: forming a semiconductor light emitting device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60027844A JPS61187383A (en) | 1985-02-15 | 1985-02-15 | Manufacture of semiconductor light emitting element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60027844A JPS61187383A (en) | 1985-02-15 | 1985-02-15 | Manufacture of semiconductor light emitting element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61187383A true JPS61187383A (en) | 1986-08-21 |
Family
ID=12232222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60027844A Pending JPS61187383A (en) | 1985-02-15 | 1985-02-15 | Manufacture of semiconductor light emitting element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61187383A (en) |
-
1985
- 1985-02-15 JP JP60027844A patent/JPS61187383A/en active Pending
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