JPS61187350A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61187350A
JPS61187350A JP2784685A JP2784685A JPS61187350A JP S61187350 A JPS61187350 A JP S61187350A JP 2784685 A JP2784685 A JP 2784685A JP 2784685 A JP2784685 A JP 2784685A JP S61187350 A JPS61187350 A JP S61187350A
Authority
JP
Japan
Prior art keywords
leads
electrode
short circuits
leaks
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2784685A
Other languages
Japanese (ja)
Inventor
Masanori Matsuo
松尾　政則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2784685A priority Critical patent/JPS61187350A/en
Publication of JPS61187350A publication Critical patent/JPS61187350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent short circuits or leaks between leads by a method wherein a well or protrusion is provided in an insulating body positioned between electrode leadout leads soldered on one and same plane. CONSTITUTION:In a surface of an insulating body 1, for mounting a semiconductor element 5, whereto electrode leads 2 are bonded by means of a silver-copper eutectic alloy 3, a recess 7 or protrusion 8 is provided between the electrode leads 2. In this design, flow of solder is prevented in a circuit packaging process. Short circuits or leaks between leads due to adhesion of conductive foreign matters may be also prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子を搭載する容器に関し、特に電極引
出しリードの取付部形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a container in which a semiconductor element is mounted, and more particularly to the shape of a mounting portion of an electrode lead.

〔従来の技術〕[Conventional technology]

従来この種の半導体パッケージの電極引出しリードの接
着は、第３図及び第４図に示すように、半導体素子５を
載置し、素子５の電極を金属細線６を介して配線する配
線層４を有する絶縁基体１の配線層４は裏面まで延長さ
れ、＆面で同一平面上で複数の電極引出しり一ド２を例
えば銀銅共晶合金３等でａ−付けしていた。Conventionally, bonding of electrode lead leads of this type of semiconductor package has been carried out using a wiring layer 4 on which a semiconductor element 5 is mounted and the electrodes of the element 5 are wired via thin metal wires 6, as shown in FIGS. 3 and 4. The wiring layer 4 of the insulating substrate 1 is extended to the back surface, and a plurality of electrode lead-out leads 2 are attached on the same plane by a-type, for example, a silver-copper eutectic alloy 3 or the like.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

この種の半導体パッケージで高周波帯の素子を搭載する
感のは、素子の特性を最大限に生かすため、パッケージ
の寄生容量、寄生インダクタンスの減少を図９、可能な
限りの小型化を行なっている九め、電極引出しリード２
間の絶縁間隔が０．１〜０．２　ｍｍと非常に狭くなっ
ている。この几め、回路実装時の半田の流れ、微少な導
電性の異物又は絶縁面への汚れ付着等によりリード２間
の短絡及び電流リークを誘発するという欠点がある。The reason why high-frequency devices are mounted in this type of semiconductor package is to reduce the parasitic capacitance and parasitic inductance of the package in order to make the most of the characteristics of the device, and to make the package as compact as possible. Ninth, electrode extraction lead 2
The insulation gap between the two is extremely narrow at 0.1 to 0.2 mm. This method has the disadvantage that short circuits and current leaks between the leads 2 may be induced due to the flow of solder during circuit mounting, minute conductive foreign matter, or dirt adhering to the insulating surface.

〔問題点を解決する九めの手段〕[Ninth way to solve the problem]

本発明の半導体バクケージは例えば銀銅共晶合金で同一
平面にロー付けされている電極引出しリード間の絶縁基
体に凹部あるいは凸部を設けている。The semiconductor back cage of the present invention has a concave or convex portion on an insulating base between electrode lead leads soldered to the same plane using, for example, a silver-copper eutectic alloy.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

本発明の第１の実施例は、第１図に示すように半導体素
子５が載置されている絶縁基体ｌの銀銅共晶合金３で電
極引出しり一ド２が接着される面で電極引出しり一ド２
の間の絶縁基体に凹部７を設けている。第２の実施例は
、第２図に示すように、電極引出しり一ド２０間の絶縁
基体に凸部８を設けている。In the first embodiment of the present invention, as shown in FIG. 1, an electrode is formed on the surface of the silver-copper eutectic alloy 3 of the insulating substrate 1 on which the semiconductor element 5 is placed, to which the electrode lead 1 and the electrode 2 are bonded. drawer 1 door 2
A recess 7 is provided in the insulating base between the two. In the second embodiment, as shown in FIG. 2, a convex portion 8 is provided on the insulating base between the electrode lead-out doors 20.

〔発明の効果〕〔Effect of the invention〕

このように本発明は、複数の電極引出しリード間の絶縁
基体に凹部あるいは凸部を設けることにより、回路寮装
時の半田流れ導電性異物付着等によるリード間短絡ある
いは電流リークを防止できる効果がある。As described above, the present invention has the effect of preventing short circuits or current leaks between the leads due to solder flow and conductive foreign matter adhering during circuit board installation by providing recesses or protrusions in the insulating base between the plurality of electrode lead leads. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第【図及び第２図はそれぞれ本発明の各実施例による半
導体装置の縦断面図である。 第３図は従来の半導体パッケージの底面図、第４図は第
３図の縦断面図である。 １・・・・・・絶縁基体、２・・・・・・電極引出しリ
ード、３・・・・・・銀銅共晶合金、４・・・・・・配
線層、５・・・・・・半導体素子、６・・・・・・金属
細線、７・・・・・・絶縁基体の凹部、８・・・・・・
絶縁基体の凸部。1 and 2 are longitudinal cross-sectional views of semiconductor devices according to embodiments of the present invention, respectively. FIG. 3 is a bottom view of a conventional semiconductor package, and FIG. 4 is a longitudinal sectional view of FIG. 3. DESCRIPTION OF SYMBOLS 1...Insulating base, 2...Electrode lead, 3...Silver copper eutectic alloy, 4...Wiring layer, 5...・Semiconductor element, 6... Thin metal wire, 7... Concavity in insulating base, 8...
Convex portion of insulating base.

Claims (1)

【特許請求の範囲】[Claims] 　絶縁基体と電極引出しリードを有する半導体装置にお
いて同一平面上の電極引出しリード間に凹部あるいは凸
部を前記絶縁基体に設けたことを特徴とする半導体装置
。1. A semiconductor device having an insulating base and an electrode lead, wherein the insulating base is provided with a recess or a convex part between the electrode leads on the same plane.
JP2784685A 1985-02-15 1985-02-15 Semiconductor device Pending JPS61187350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2784685A JPS61187350A (en) 1985-02-15 1985-02-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2784685A JPS61187350A (en) 1985-02-15 1985-02-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61187350A true JPS61187350A (en) 1986-08-21

Family

ID=12232281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2784685A Pending JPS61187350A (en) 1985-02-15 1985-02-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61187350A (en)

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