JPS61184986A - Picture recording and reproducing method for character broadcasting - Google Patents

Abstract

PURPOSE:To prevent the worsening of the reproducibility of a color and luminance by converting the character signal packet overlapped at the television signal from parallel to serial for respective programs, synchronizing these to an inherent composite synchronizing signal, fetching plural programs simultaneously, applying a composite synchronizing signal to this and generating the video signal. CONSTITUTION:By a shifting signal outputted at a sampling clock generating circuit 3, the signal of parallel and serial converting circuits 5a, 5b...5n is simultaneously fetched, serially converted by a parallel-serial converting and feeding circuit 17, a composite synchronizing signal is overlapped at a mixing circuit 7 and outputted from an output terminal 9 as a new video signal. In the video signal, for example, the frequency, in which the frequency at the time of the input is 5.73MHz, goes to be the frequency of about 1.43MHz, and can be sufficiently recorded by the real time even for a VTR for the home. At the time of reproduction, the output of parallel and serial converting circuits 18a, 18b...18n of respective programs is rearranged in parallel by the signal synchronized with the time of 21H completion from a NAND gate 18, goes to be the same condition the data fetched at the time of the input and the output terminal 19 is successively outputted.

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention makes it possible to record character signal packets superimposed on a television signal in real time on a VTR with a narrow recording band, and to play it back again. This invention relates to a teletext recording and playback method.

"Prior art" The teletext signal superimposed on the television signal has a frequency of 5.7.
3MHz (unit period Tc given 175nsec), but the maximum recording frequency of a home VTR is 2.5 to 3MHz.
z It's not good. Therefore, the teletext packet data superimposed on the television signal can be transmitted to the home VTR in real time.
Conventionally, the teletext signal was received once, decoded by a decoder, and then converted to a video signal by a color encoder. Note that although it is possible to directly record teletext packet data in real time with a commercial wideband VTR, the VTR itself is expensive and is not common.

``Problems to be solved by the invention'' When using a home narrowband VTR, it was not only impossible to record teletext packet data in real time; Since it was converted into a video signal using an encoder, there was a problem in that the high frequencies were attenuated and the reproducibility of color and brightness deteriorated.

The present invention has been made to solve the above-mentioned conventional problems, and it generates a single composite synchronization signal, and synchronizes the transition from parallel to series. and mix the composite synchronization signal to generate a new devio signal and record it, and at the time of playback, similarly convert from serial to parallel based on the composite synchronization signal and convert it to the original character signal packet data. This is the method I used to do it.

"Function" Even if, for example, eight programs are superimposed on the vertical retrace line of the television signal, the code system does not allow
Since it only takes 192H, real-time processing at 1V is possible.

"Example" An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a superimposition circuit for superimposing a self-generated composite signal onto a teletext packet data signal superimposed on a television signal to obtain a new video signal.

In this superimposition circuit, (1) is a composite synchronization signal generation circuit that generates a unique horizontal synchronization (IH) composite synchronization signal as shown in FIG. The H position detection circuit that detects and outputs the H position of the horizontal synchronization signal for cueing, (3) is shown in Figure 4 (b).
), (4) is a Nantes gate, (5a) (5b) - (5n) are each 10H of one line of vertical retrace line. , 11H, 12H113H114H115
(6) is a parallel-to-serial conversion circuit for each program that converts teletext packet data superimposed on H116H and 21H from parallel to serial; (6) is a parallel-to-serial conversion circuit for each program (5);
a) Parallel-to-serial conversion and sending circuit for simultaneously taking in and sending out (5b)...(5n), (7) is a mixing circuit. Further, (8) is an input terminal for CPU data into which packet data has been taken in, and (9) is an output terminal for a generated video signal.

Next, FIG. 2 shows a video signal reproducing circuit formed by the superimposing circuit of FIG. 1. In this reproduction circuit, (
10) is a video signal input terminal, (11) is a level conversion circuit, (12) is a slicer for extracting only data,
(13) is a synchronization separation circuit; (14) is a horizontal synchronization signal H position detection circuit; (15) is a sampling clock generation circuit that generates a sampling clock signal as shown in FIG. 4(c); ) is Nantes Gate, (17
) is a serial-to-parallel conversion circuit that converts all serially arranged programs into parallel, and (18a) (18b) - (18n) converts the data for each program from serial to 192-bit parallel signals in the case of the code method. Serial-to-parallel conversion circuit for each program to be converted,
(19) is a CPU data output terminal.

Next, in the circuit configuration as described above, it is assumed that character signal packet data for, for example, eight programs are superimposed on one line of the vertical retrace line of the video signal and inputted from the input terminal (8). Then, in synchronization with the cue signal of the H position detection circuit (2), the parallel/serial conversion circuits (5a) (5b)...
5n), the data for each program is sequentially parallel-serial converted and stored.

In the sampling clock generation circuit (3),
) A clock signal of approximately 7 μsec as shown in FIG. 1 is output as a shift signal. By this shift signal, the signals of the parallel-to-serial conversion circuits (5a), (5b), . Mixed circuit (7
), the composite synchronization signal is superimposed on the composite synchronization signal and output from the output terminal (9) as a new video signal as shown in FIG. 3(a). In other words, this video signal had a frequency of 5.73 MHz (with a cycle of 175 ns) at the time of input, but the frequency has changed to a frequency of about 7 μsec, or about 1.43 MHz, making it possible to record in real time even on a home VTR. Become.

Next, reproduction of the video signal recorded as described above will be explained. Input terminal (10) of the reproducing circuit shown in Figure 2
When a video signal as shown in FIG. 3(a) is input to a video signal, it is sent to the slicer (12) via the level conversion circuit (11), and when sliced at a good slice level as shown in FIG. 3(a), the third Only data as shown in Figure (b) is extracted.

At the same time, the composite synchronization signal is separated by the synchronization separation circuit (13). In synchronization with this composite synchronization signal, the sampling clock generation circuit (15) outputs a sampling signal as shown in FIG. 4(c), and the horizontal synchronization signal H position detection circuit (14) outputs, for example,
A signal is output at the rising edge at the end. The slicer (12
), only the data signal is output, and this is the serial-to-parallel conversion circuit (
17). Then, this serial-parallel conversion circuit (17
) is input with a sampling clock signal as shown in FIG. 4(c) as described above, and at the rising edge of the clock signal, data for each program is sent to the serial/parallel converter circuits (18a), (18b)...(18n). Output. The outputs of the serial/parallel conversion circuits (18a) (18b) ・= (18n) for each of these programs are rearranged in parallel using a signal synchronized with the end of 218 from Nantes Gate (18), so this output data signal is The data is in the same state as the data taken in at the time of input, and is sequentially output to the output terminal (19).

"Effects of the Invention" As described above, the present invention generates character signal packet data inputted in synchronization with a unique composite synchronization signal as a video signal. Therefore, even if the packet data of 8 programs are superimposed, for example, in the case of the code method, the use of 1v (vertical synchronization period) H (horizontal synchronization period)
requires only 192H, and the sampling period of each H is 7μ
It is stable at about sec, and real-time processing at lv is sufficiently possible. In addition, in the case of the pattern method, 1
Since there are 272 bits in a packet, if every 2 bits of each packet are superimposed on IH, the sampling period is 3.5μ.
sec. Therefore, since the maximum recording frequency of a general home VTR is 3 MHz, it is possible to record in real time even with the above-mentioned cycle, and a single circuit can be made at a low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a superimposition circuit for obtaining a video signal according to the method of the present invention, FIG. 2 is a block diagram of a reproducing circuit for reproducing character signal packets from a video signal generated according to the present invention, and FIG. Figures (a) (b) are waveform diagrams of the video signal and data signal, Figure 4 (a) (b) (c)
is a waveform diagram of a composite synchronization signal and a sampling clock signal. (1)...Composite synchronization signal generation circuit, (2)
(14)...H position detection circuit, (3) (15)...
・Sampling clock generation circuit, (4) (16)・
...Nant gate, (5a) to (5n)...Parallel-serial conversion circuit, (6)...Parallel-serial conversion circuit and sending circuit, (7)...Mixing circuit, (8)...CPU Data input terminal, (9)...Video signal output terminal, (10)
... video signal input terminal, (11) ... level conversion circuit, (12) ... slicer, (13) ... synchronization separation circuit, (17), (18a) to (18n) ...
・Serial-to-parallel conversion circuit, (19)...CPU data output circuit.

Claims (2)

[Claims] (1) In a method for recording character signal packets superimposed on a television signal as a video signal on a VTR in real time and reproducing the generated video signal into the original character signal packet, the character signal packet superimposed on the television signal is converted from parallel to serial for each program, these are synchronized with a unique composite synchronization signal, multiple programs are simultaneously extracted, and a composite synchronization signal is added to this to generate a video signal. A teletext recording and playback method characterized by the following. (2) In a method for recording character signal packets superimposed on a television signal as a video signal on a VTR in real time and reproducing the generated video signal into the original character signal packet, the character signal packet superimposed on the television signal is converted from parallel to serial for each program, these are synchronized with a unique composite synchronization signal, multiple programs are simultaneously extracted, a composite synchronization signal is added to this to generate a video signal, and this A method for recording and reproducing teletext broadcasting in which a generated video signal is converted from serial to parallel based on the horizontal synchronization position of a horizontal synchronization signal and reproduced into the original character signal packet.