JPH07177533A - Video signal processor - Google Patents

Abstract

PURPOSE:To allow an operator to simply fetch a still picture picked up by a still video camera or the like to a personal computer as image data. CONSTITUTION:A signal read out of a floppy disk 1 is amplified by a head amplifier 3, a luminance signal and a chrominance signal are demodulated and their high frequency components are attenuated, and the resulting signals are respectively inputted to adders 7, 16. Furthermore, an ID signal recorded with a video signal is demodulated by an ID decoder 14 and synthesized with an operating state signal of the unit in a CPU 15 and the resulting signal is fed to a data encoder 9. The data encoder 9 encodes the signal by using a subcarrier fed from a subcarrier oscillator 13 in a predetermined timing based on a synchronizing signal fed from a synchronizing separator circuit 8. Then the encoded signal is added to the luminance signal and the chrominance signal at adders 7, 16, from which an output is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device.

[0002]

2. Description of the Related Art Conventionally, when a still image photographed and recorded by a still video camera or the like is taken into a personal computer as image data, a digitizer board is used to convert an analog video signal into digital data.

[0003]

However, in the above conventional example, when a general-purpose digitizer is used, the still video reproducing device is manually operated to confirm that the reproduced output image of the still video is stably output. While it was necessary to perform the digitizing operation. Therefore, in order to automatically perform these operations, a still video playback device and a system-dedicated digitizer communicate a communication line for giving various operation commands to the still video playback device and a still video operation state to the digitizer. It was necessary to secure each communication line.

In addition to these still video operating states, ID data such as the date of shooting, which is recorded together with the operating states in the still video format,
There is a problem in that the number of signal lines that must be provided for bidirectional communication between the digitizer and the still video playback device is large, the wiring is complicated, and the connection is erroneous, which is not practical.

[0005]

The present invention has been made to solve the above-mentioned problems, and in a signal processing device, a video signal including a first signal of a luminance system and a second signal of a color system. Input means, conversion means for converting the additional information of the video signal by using the first signal and / or the second signal, and the output of the conversion means by the first signal and / or And a synthesizing means for synthesizing the second signal.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

<< Embodiment 1 >> FIG. 1 shows a block diagram of a still video reproducing apparatus according to a first embodiment of the present invention. The floppy disk 1 is driven by a spindle motor 2 and rotates at a constant speed. The RF signal recorded on the floppy disk 1 is read by the magnetic head 3 and amplified by the head amplifier 4. The luminance (Y) signal + synchronization (S) signal in the RF signal is demodulated by the demodulator 5, attenuated in the high frequency range in the de-emphasis circuit 6, and then added by the adder 7.
And the sync separation circuit 8. The sync signal separated from the sync separation circuit 8 is input to the data encoder 9.

The color difference (RY, BY) signals are demodulated by the demodulator 10, attenuated in the high range by the de-emphasis circuit 11, and then synchronized by the chroma encoder 12 to obtain the chroma (C). Converted to a signal. The subcarrier oscillator 13 has a center frequency of 3.57954MH.
It oscillates a chroma subcarrier (f _SC ) of z and supplies f _SC to the data encoder 9 and the chroma encoder 12, respectively. Further, the RF signal includes an ID signal such as recording date and time together with the video signal.
It is demodulated by 4 and input to the CPU 15. The input ID signal is combined with the operation state signal of the entire device in the CPU 15 and supplied to the data encoder 9. The combined ID signal and operation state signal are based on the synchronization signal supplied from the synchronization separation circuit 8 in the data encoder 9 and at a predetermined timing, the subcarrier oscillator 1
It is encoded using the subcarriers supplied from H.3. The ID signal and the operation state signal converted into the video signal are input to the adders 7 and 16, and added to the luminance (Y) signal and the chroma (C) signal demodulated in the video signal, respectively, and output terminals 17 and 18 Is output.

Next, FIG. 2 shows a block diagram of the configuration of the data encoder 9. 3 and 4 show waveform diagrams of each part of the data encoder 9. The ID signal and the operation state signal input from the CPU 15 are serially transferred to 32b.
Write clock (WC to it line buffer 19
It is temporarily stored by L). The counter 20 is for timing to output the ID signal and the operation state signal at a predetermined timing, and the synchronization separation circuit 8 of FIG.
It is activated by the horizontal and vertical sync signals (FIGS. 3a, b) provided by The counter 20 resets the count value to "0" by the input of the vertical synchronizing signal b, and then counts up by 1 each time the horizontal synchronizing signal a is input. Then, when the count value is "8" and the period other than the horizontal blanking period starts from the trailing edge of the clock φ1 (FIG. 4f) described later and the clock φ1 counts 32 times, the encode enable (En) The signal is output (FIGS. 3c and 4c).

The frequency dividing circuit 21 divides f _SC (FIG. 4d) by 5 to generate two encoding clocks φ0 (FIG. 4e) and clock φ1 (FIG. 4f) having different phases. The clocks φ0 and φ1 are gated by the En signal by the AND gates 22 and 23, and read clock (RCL, FIG. 5g).
And Y data (FIG. 5h). Read clock is 3
It is used to sequentially read the data on the 2-bit line buffer 19, and when the read clock becomes “H”,
Read the ID signal and the operation state signal (FIG. 4i). This data signal is multiplied by f _{SC in the} AND gate 24 to become a burst-like signal (Fig. 5j), passes through the 3.58MHz band pass filter (BPF) 25, and becomes a burst waveform of only the fundamental frequency component of the subcarrier (Fig. 4k), and is output as chroma (C) data. FIG. 5 shows output waveforms obtained by superposing the Y data and the C data on the Y + S signal and the C signal in the adders 7 and 16 of FIG. 1, respectively. In FIG. 5, Y data and C data are superimposed on the 8th line counting from the input of the vertical synchronizing signal. 32 for Y data
They are equal-interval pulses emitted, and the presence or absence of the C signal at each pulse position constitutes 32-bit digital data.

Next, a decoding circuit on the digitizer side for reading the data multiplexed on the video signal will be described. FIG. 6 is a configuration block diagram of the decoding circuit.
7 and 8 show waveforms at various parts of the decoding circuit. In FIG. 6, the Y + S signal DC-reproduced by the clamp circuit 26 is input to the comparator 27 and the sync separation circuit 28, respectively. The reference voltage source 29 generates a reference voltage for the clamp circuit 26 and the comparator 27, and the comparator 27 extracts Y data higher than the center level of the Y data of the 8th line as shown by the dashed line in O of FIG. Figure 7
p) is input to the AND gate 30. On the other hand, the horizontal sync signal and the vertical sync signal (FIG. 7L, m) separated by the sync separation circuit 28 are supplied to the counter 31. The counter 31 outputs a decode enable signal (FIG. 7n) which becomes H only during the period of the 8th line from the input of the horizontal synchronizing signal. The decode enable signal is input to the AND gate 30, and the multiplexed Y data is passed only for the period of the eighth line and used as the write clock (WCL) of the 32-bit line buffer 32 (FIG. 7q).

On the other hand, the input C signal (FIG. 8r) is detected by the detection circuit 33, and the low pass filter (LPF) is detected.
At 34, the envelope is taken out, converted to digital data, and input to the 32-bit line buffer 32 (FIG. 8s).

As shown in FIG. 8, the decoded data (FIG. 8s) obtained from the chroma signal is sequentially written into the 32-bit line buffer 32 by the write clock (FIG. 8q) obtained from the Y data on the Y + S signal. Then, it is output by serial transfer to a CPU (not shown) on the digitizer side. In the case of the present embodiment, the decoded data is 11010010 ... From the beginning.

<Embodiment 2> FIG. 9 shows a block diagram of a still video reproducing apparatus according to Embodiment 2 of the present invention. The reproduction of the luminance (Y) signal + synchronization (S) signal and the encoding of the ID signal and the operation state signal are the same as those in the first embodiment, and therefore, the same portions will be denoted by the same reference numerals and description thereof will be omitted. The color difference (RY, BY) signal in the RF signal is demodulated by the demodulator 10, attenuated in the high frequency band in the de-emphasis circuit 11, and then input to the adder 35. C
The ID signal and the operation state signal output from PU15 are
In the data encoder 36, the subcarrier supplied from the subcarrier oscillator 37 is encoded at a predetermined timing based on the sync signal supplied from the sync separation circuit 8. Y of the encoded data
The data is added to the Y signal in the adder 7 and output from the output terminal 17. On the other hand, the R-Y data and the B-Y data are added to the color difference signal in the adder 35, then synchronized in the chroma encoder 38, and output from the output terminal 39 as a C signal.

Next, FIG. 10 shows a detailed view of the data encoder 36. The ID signal input from the CPU 15 is 32b
The operation status signal is 32 bits in the it line buffer 40.
It is temporarily stored in the line buffer 41 by the write clock (WCL). The counter 42 has a timing for outputting the encoded ID signal and the operation state signal at a predetermined timing, and operates by the horizontal and vertical sync signals supplied from the sync separation circuit 28 of FIG. After resetting the count value to "0" with the input, the count value is incremented by 1 each time the horizontal synchronizing signal is input. And the count value is "8"
In the period other than the horizontal blanking period, the En signal is output during the period starting from the trailing edge of the clock φ1 and counting 32 clocks φ1.

The frequency dividing circuit 43 divides f _SC by 5 to generate two encoding clocks φ0 and φ1 having different phases. The clocks φ0 and φ1 are gated by the En signal in the AND gates 44 and 45, and become the read clock (RCL) and Y data. Read clock is 3
It is used for sequentially reading the data on the 2-bit line buffers 40 and 41, and when the read clock becomes "H", the ID signal and the operation state signal are read. The ID signal is output as an RY signal, and the operation state signal is output as a BY signal. The two output signals are added to the color difference signal in the adder 35 shown in FIG. On the added color difference signals, H and L of the ID signal are output as the presence or absence of the RY signal component, and H and L of the operation state signal are output as the presence or absence of the BY signal component. FIG. 11 shows this color difference signal as a vectorscope. Both ID signal and operating status signal are L
At point a, then ID signal = H, operating state signal = L
At point b, ID signal = L, and operation state signal = H c
At the point, when both the ID signal and the operation state signal are H, the point becomes the point d.

Next, FIG. 12 is a configuration block diagram of a decoding circuit on the digitizer side according to the second embodiment. In FIG. 12, the Y + S signal DC-reproduced by the clamp circuit 46 is input to the comparator 47 and the sync separation circuit 48. The reference voltage source 49 generates a reference voltage for the clamp circuit 46 and the comparator 47, and the comparator 47 extracts the higher Y data portion at the center level of the Y data on the eighth line and inputs it to the AND gate 50. On the other hand, the horizontal and vertical sync signals separated by the sync separation circuit 48 are supplied to the counter 51, and the counter 51 obtains a decode enable signal which becomes Hi only during the period of the eighth line from the input of the horizontal sync signal. The decode enable signal is AN
8 times the multiplexed Y data input to the D gate 50
It is passed only during the period of the line and used as a write clock (WCL) for the 32-bit line buffers 52 and 53.

On the other hand, the chroma signal is returned to the color difference (RY, BY) signal in the chroma decoder 54, DC-reproduced in the clamp circuits 55 and 56, respectively, and then input to the comparators 57 and 58. The reference voltage source 59 generates a reference voltage for the clamp circuits 55, 56 and the comparators 57, 58. The comparator 57, 58 receives the input RY or BY signal and the reference voltage from the reference voltage source 59. To reproduce the ID signal or the operation state signal. The reproduced ID signal and operation state signal are respectively 32 by the write clock.
It is written in the bit line buffers 52 and 53. Then, the ID signal and the operation state signal on the line buffer are read by the read clock (RCL).

The method of transmitting / receiving data depending on the presence / absence of the RY signal and the BY signal has been described above.
Both the Y signal and the BY signal have polarities, and it is conceivable to superimpose H and L of data depending on the polarities. FIG. 13 shows a vector diagram in that case.

<< Embodiment 3 >> FIG. 14 shows a block diagram of a still video reproducing apparatus according to a third embodiment of the present invention. The chroma signal reproduction system is omitted. In FIG. 14, the Y signal in the RF signal read from the video floppy 1 is demodulated by the demodulator 60, attenuated in the high frequency range by the de-emphasis circuit 61, and then separated by the sync separation circuit 6.
2 and the adder 63. The sync separation circuit 62 separates the sync signal from the Y signal, and the data encoder 6
Supply to 4. In addition, the subcarrier oscillator 65 is a chroma subcarrier (f with a center frequency of 3.57954 MHz).
_SC ) and supplies 1 / 5f _SC to the data encoder 64. On the other hand, the ID signal in the RF signal is the ID decoder 6
6 is decoded and input to the CPU 67. The input ID signal is combined with the operation state signal of the entire device in the CPU 67 and supplied to the data encoder 64. Then, the ID signal and the operation state signal are encoded at a predetermined timing based on the synchronization signal supplied from the synchronization separation circuit 62 in the data decoder 64 and sent to the adder 63. Then, it is added with the Y signal in the adder 63, and is output from the output terminal 68 as digital data having an amplitude of 0IRE to 100IRE.

Next, FIG. 15 is a block diagram showing the structure of the data encoder 64, and FIG. 16 schematically shows the waveform of each part. In FIG. 15, the ID signal and the operation state signal from the CPU 67 are temporarily stored in the 32-bit line buffer 69 by the write clock (WCL). The counter 70 resets the count value at the start edge of the vertical synchronizing signal (FIG. 16b), and thereafter resets the horizontal synchronizing signal (FIG. 1).
Every time 6a) is input, it is incremented by one. When the count value becomes "8", the gate is opened (Fig. 16c), and the data read enable is performed during the period from the 10th count to the 42nd count of the 1 / 5f _SC clock supplied from the subcarrier oscillator 65 during this period. Output a pulse (Fig. 16d). Then, while the data read enable pulse d is ON, the 1 / 5f _SC clock is output as a read clock (FIG. 16e). 32 bit
The line buffer 69 outputs the stored ID signal and operation state signal in synchronization with the read clock (FIG. 16).
f). FIG. 17 shows the waveform when the ID signal and the operation state signal are added to the reproduced Y signal in the adder 63. In FIG. 17, the ID signal and the operation state signal are included in the effective horizontal video period of the 8th line from the input of the vertical synchronization signal. FIG. 18 shows only the 8th line at this time. Data starts from the point of 13.97 μsec, which is the 10th count of the 1 / 5f _SC clock from the fall of the horizontal synchronization signal, and is 58.67, which is the 42nd count.
Up to the point of μsec 3 at 1.397μsec pitch
It carries 2 bits of data. In the case of the present embodiment, the data is 10011101 ... 011 from the beginning.

Next, FIG. 19 shows a block diagram of the configuration of the signal input section of the digitizer. In FIG. 19, the input Y
The signal is DC-regenerated by the clamp circuit 71, then supplied to the input of an A / D converter (not shown) and also input to the sync separation circuit 72 and the comparator 73. The reference voltage source 74 generates a reference voltage for the clamp circuit 71 and the comparator 73. The comparator 73 outputs the reproduced Y signal to 50
By comparing with a reference voltage corresponding to IRE, H-
The binary data of L is input to the data decoder 75. Further, in the sync separation circuit 72, the horizontal and vertical sync signals are separated from the Y signal and similarly supplied to the data decoder 75. The data decoder 75 reads the output of the comparator 73 based on the supplied horizontal and vertical synchronization signals,
The data is sent to a CPU (not shown) or the like.

Next, FIG. 20 shows a block diagram of the structure of the data decoder 75 on the digitizer side for receiving this data, which will be described below. Based on the horizontal and vertical sync signals supplied from the sync separation circuit 72 of FIG.
In 6, the decode enable signal which becomes “H” is output only during the period of the 8th line from the input of the horizontal synchronizing signal, and the AND
Input to the gate 77. The Y signal output from the comparator 73 is passed through the AND gate 77 only for the period of the eighth line by the decode enable signal and is output as a write clock. The ID signal and the operation state signal once written in the 32-bit line buffer 78 by the write clock are read as serial data in synchronization with the read clock (RCL) from the CPU (not shown) that controls the digitizer.

<Embodiment 4> FIGS. 21 to 26 are a waveform diagram and a configuration block diagram of the present embodiment, and the block configuration of a still video reproducing apparatus and a digitizer is the same as in FIG.
4 and FIG. 21 shows one scanning line period in which an ID signal and an operation state signal are put, FIG. 22 is an enlarged view of a part of the ID signal and the operation state signal, and FIG. 23 is FIG.
4 is a block diagram of the data encoder 64 of FIG. 4, FIG. 24 is a waveform diagram of each part of the data encoder 64, FIG. 25 is a block diagram of the data decoder 75 of the digitizer, and FIG. 26 is a waveform diagram of each part of the data decoder 75.

Similar to the third embodiment, the ID signal and the operation state signal are on the 8th line counted from the vertical synchronizing signal.
As shown in FIG. 21, 32 bit data is put on any place other than the horizontal blanking period for about 35.76 μsec. There is about 1.12 μsec per 1 bit, which corresponds to 4 clocks of the chroma subcarrier f _SC (3.579545 MHz). As shown in FIG. 22, when each data signal is "1", it is "H" for about 0.84 μsec for f _SC 3 pulses, and then about 0.28 μ for f _SC 1 pulse.
It becomes “L” for the sec period. On the contrary, when the data is "0", it becomes "H" for about 0.28 µsec for one f _SC pulse, and then "L" for about 0.84 µsec for 3 f _SC pulses.
Becomes

Next, in FIG. 23, the ID signal and the operation state signal sent from the CPU are once written in the 32-bit line buffer 79 by the write clock (WCL). The frequency divider circuit 80 receives the input f _SC (see FIG. 24).
A) is divided to generate pulses φ0 and φ1 having duty ratios of 1: 3 and 3: 1 (FIGS. 24b and 24c). This 2
Φ0 of the two pulses is input to the AND gate 81 and gated by the enable signal (FIG. 17d) from the counter 82. This enable (En) signal becomes "H" based on the horizontal and vertical sync signals supplied from the sync separation circuit, except during the horizontal blanking period of the 8th line counted from the vertical sync signal. The gated signal is a 32-bit line buffer 8
3 read clock (RCL). The ID signal and the operation state signal (FIG. 24d) read by the read clock are used to control the data selector 84, and select "1" side when the read data is "L". In this case, the read data is 100 ...
The encoded data (FIG. 24e) is sent to the adder 63 of FIG. 14 and becomes the output Y signal.

Next, the decoding circuit of the digitizer to which the ID signal and the operation state signal are input will be described. Figure 2
5 is a block diagram of the configuration of the decoding circuit. The output of the comparator 73 in FIG. 19 is the 32 bit line buffer 8
Input to 5 while delay line of 500 nsec 8
6 is input. In the counter 87, the sync separation circuit 72
A data write enable (En) signal is generated on the basis of the horizontal synchronizing signal supplied from and is input to the AND gate 88. The AND gate 88 gates the data (FIG. 26a) delayed by the write En signal, and only 3 in one horizontal period of the 8th line counted from the input of the vertical synchronization signal.
Write clock (WC
L, FIG. 26b).

In the case of this embodiment, 10011 ...
・ It becomes a data string. The data once written to the 32-bit line buffer 85 is read clock (RCL) as in the case of the third embodiment shown in FIG.
ID signal and operation status signal are read by
Transmitted to. Although the example of putting 32-bit data on one line has been described above, the clock speed and the data length are not particularly limited as long as they are within the band of the luminance signal (4.2 MHz at NTSC). Further, it goes without saying that not only one line can be used for data, but also a plurality of lines can be used for data transmission in an ineffective screen portion.

[0029]

As described above, in the video signal processing device, the input means for inputting the video signal including the first signal of the luminance system and the second signal of the color system, and the first signal and / or A conversion means for converting the additional information of the video signal using the second signal, and an output of the conversion means for the first signal and / or the second signal.
By configuring with a synthesizing means for synthesizing with the signal of the above, there is no influence on the effective part of the signal, and it becomes possible to transmit digital data without adding a new signal line, and the device is small in size. It is possible to provide a signal processing device that is easy to use by reducing the cost and cost.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a still video (SV) playback device according to a first embodiment.

FIG. 2 is a configuration block diagram of a data encoder according to the first embodiment.

FIG. 3 is a waveform chart of each part of the data encoder of the first embodiment.

FIG. 4 is a waveform chart of each part of the data encoder of the first embodiment.

FIG. 5 is a waveform chart of each part of the SV reproducing apparatus according to the first embodiment.

FIG. 6 is a configuration block diagram of a decoding circuit according to the first embodiment.

FIG. 7 is a waveform chart of each part of the decoding circuit according to the first embodiment.

FIG. 8 is a waveform chart of each part of the decoding circuit according to the first embodiment.

FIG. 9 is a configuration block diagram of an SV reproducing device according to a second embodiment.

FIG. 10 is a configuration block diagram of a data encoder according to a second embodiment.

FIG. 11 is a vectorscope diagram of an output waveform of the SV reproducing device of the second embodiment.

FIG. 12 is a waveform chart of each part of the decoding circuit of the second embodiment.

FIG. 13 is a vectorscope diagram of an output waveform of the SV reproducing device of the second embodiment.

FIG. 14 is a configuration block diagram of an SV reproducing device according to a third embodiment.

FIG. 15 is a configuration block diagram of a data encoder according to a third embodiment.

FIG. 16 is a waveform chart of each part of the data encoder in the third embodiment.

FIG. 17 is an output waveform diagram of the SV reproducing apparatus according to the third embodiment.

FIG. 18 is a waveform chart of an 8H line of the output waveform of the SV reproducing device of the third embodiment.

FIG. 19 is a configuration block diagram of a signal input of the decoding circuit according to the third embodiment.

FIG. 20 is a configuration block diagram of a data decoder according to a third embodiment.

FIG. 21 is a waveform chart of the output of the SV reproducing apparatus of Example 4 in the 8th line of the total.

FIG. 22 is an enlarged waveform diagram of an ID signal and an operation state signal according to the fourth embodiment.

FIG. 23 is a configuration block diagram of a data encoder according to a fourth embodiment.

FIG. 24 is a waveform chart of each part of the data encoder in the fourth embodiment.

FIG. 25 is a configuration block diagram of a data decoder according to the fourth embodiment.

FIG. 26 is a waveform chart of each part of the data decoder in the fourth embodiment.

[Explanation of symbols]

9, 36, 64, 75 Data encoder 14, 66 ID decoder 15, 67 CPU 19, 32, 40, 41, 52, 53, 69, 78, 8
3,85 32-bit line buffer 20, 31, 42, 51, 70, 76, 82, 87 counter 21, 43, 79 frequency divider circuit 84 data selector

Claims (2)

[Claims] 1. An input unit to which a video signal including a first signal of a luminance system and a second signal of a color system is input, and the video signal using the first signal and / or the second signal. The video signal processing device, comprising: a conversion unit that converts the additional information of 1. and a combination unit that combines the output of the conversion unit with the first signal and / or the second signal. 2. Input means for inputting a synthetic signal obtained by synthesizing additional information of a video signal with a first signal of a luminance system and / or a second signal of a color system, and the synthetic signal inputted by the input means. And a separating means for separating the additional information of the video signal from the video signal processing device.