JPS61184793A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To hold an MIS type nonvolatile memory transistor (TR) in an erasure state by connecting the drain electrode of the MIS type nonvolatile memory TR to a power source and connecting the drain electrode of an MOS TR and the source electrode of an MOS type TR for bit line charging to the source electrode of the MIS type nonvolatile memory TR. CONSTITUTION:An MOS enhancement TR Q7 has its drain electrode connected to the power source and its source electrode connected to a bit line and inputs a write signal W at its gate electrode. The MOS enhancement TR Q7 is turned on with the write signal W in writing operation and a write voltage Vp is applied to the gate electrode of the MIS type nonvolatile memory TR Q4. When an MOS enhancement TR Q6 is in continuity state on with write data D at this time, the bit line connected to the source line of an MIS type nonvolatile memory TR Q4 is nearly at the same grounding potential.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory circuit using MIS type non-volatile memory transistors.

2. Description of the Related Art In general, a MIS type nonvolatile memory transistor has a structure in which a so-called trap center for trapping negative charges is specially formed in a gate insulating film under or in the vicinity of a gate electrode.

When a high electric field is fully applied to this MIS type non-volatile memory transistor insulating film through the gate electrode and charges are injected and retained at the center of the trap, a reverse charge is generated on the silicon substrate surface under the insulating film according to the amount of injected and retained charge. A channel is formed by inducing

This trapped charge has a memory property that it is retained without being disturbed unless a high electric field of opposite polarity to the above-mentioned electric field is applied to the gate electrode. For example, in the case of an N-channel MIS type nonvolatile memory transistor, a state in which positive charges are trapped in the edge film of the MIS type nonvolatile memory transistor is an erased state, and a state in which negative charges are trapped is a written state.0 MIS type nonvolatile memory in the erased state A conventional example of a circuit for writing transistor information will be explained.

The circuit configuration diagram is shown in FIG.

A power supply voltage Vp is applied to the gate electrode of the MIS type nonvolatile memory transistor Q1, and the drain electrode is connected to the load MO
The bit line, which is connected to the power supply through the S depletion type transistor Q2 and is the source electrode of the MIS type nonvolatile memory transistor Q1, is connected to the MO for write data input.
The write data D is connected to the drain electrode of the enhancement type transistor Q3, and the write data D is input to the gate electrode of the MOS enhancement type transistor Q3.
, the source electrode is grounded.

The operation of the circuit for writing all information into the MIS type nonvolatile memory transistor Q1 configured as described above will be described below.

During a write operation, a write voltage Vp is applied to the gate electrode of the MIS type nonvolatile memory transistor Q1. Here, when the MOS enhancement type transistor Q3 is conductive due to the write data D, the source electrode of the MIS type nonvolatile memory transistor Q1 becomes the ground potential.

At this time, since the write voltage Vp is applied to the gate electrode of the MIS type nonvolatile memory transistor Q1, a channel is formed on the substrate surface under the gate electrode.
The potential of the substrate surface becomes the ground potential, which is equal to the source electrode potential of the MIS type nonvolatile memory transistor Q1. Therefore, a high electric field is applied to the gate insulating film of the MIS type nonvolatile memory transistor Q1 through the gate electrode and the substrate. As a result, the MIS type nonvolatile memory transistor Q1, which was in the erased state, transitions to the written state.

On the other hand, if the MOS enforcement transistor Q3 is cut off by the write data D, then M
The bit line 0 L), which is the source electrode of the IS type non-volatile memory transistor Q1, is charged by the current supplied through the load MOS transistor Q2', and the bit line 0 L), which is the source electrode of the IS type non-volatile memory transistor
The source electrode potential of 1 is (write voltage Vp) - (MI
At this time, since the write voltage Vp is applied to the gate electrode of the MIS type nonvolatile memory transistor Q1, an inversion layer is formed on the substrate surface under the gate electrode. The potential of the substrate surface is equal to the drain electrode potential of MIS type nonvolatile memory transistor q1, and the power supply voltage V
becomes p. Therefore, the gate electrode potential of the MIS type nonvolatile memory transistor Q1 and the substrate surface potential are equal, no electric field is applied to the gate insulating film, and there is no change in the amount of charge trapped in the gate insulating film, resulting in an erased state. 7zMIS type nonvolatile memory transistor Q1 remains in the erased state.

Problems to be Solved by the Invention MIS type non-volatile memory IJ having the configuration as shown in the conventional example) In the write circuit of the transistor Q1, when the MOS enforcement type transistor Q3 is cut off by the write data D, The bit lines (B, L), which are the source electrodes of the MIS type nonvolatile memory transistor Q1, are charged only by the current supplied from the power supply through the load MOS depletion type transistor Q2'. However, the bit lines (B, L)
The time for the potential to reach (write voltage Vp) - (threshold voltage of MIS type nonvolatile memory transistor Q1),
A potential difference occurs between the gate electrode and the substrate surface of the MIS type nonvolatile memory transistor Q1, and this potential difference changes the amount of charge trapped in the gate insulating film of the MIS type nonvolatile memory transistor Q1. In non-volatile memory, where the charge retention lifetime is an important factor determining the reliability of memory function, 1 in the erased state
A major drawback is that the amount of charge trapped in the insulating film of the MIS type nonvolatile memory transistor changes due to a write operation that should keep the i1 type S type nonvolatile memory transistor in a fully erased state. Unfortunately, this problem is becoming more noticeable as the memory capacity increases and the load capacity of the bit line (BL) increases.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a writing circuit that can maintain an erased MIS type nonvolatile memory transistor in an erased state.

Means for Solving the Problems A feature of the semiconductor circuit according to the present invention is that the drain electrode of the MIS type nonvolatile memory transistor is connected to a power supply via a load, and the source electrode of the MIS type nonvolatile memory transistor is connected to the source electrode of the MIS type nonvolatile memory transistor. It is constructed by connecting the drain electrode of a kO8 type transistor for data input whose electrode is grounded, and the source electrode of a MOS type transistor for bit line charging whose drain electrode is connected to a power supply.

As a result, the MIS type nonvolatile memory transistor can be maintained in the erased state even during a write operation.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, Q4 is an MIS type nonvolatile memory transistor, Q5 is a MOS depletion type transistor for load, and Q6 is a MOS enhancement type transistor for inputting write data.

This circuit configuration is different from the conventional configuration shown in FIG. 2 because it is a bit line charging MOS enhancement type in which the drain electrode is connected to the power supply, the source electrode is connected to the bit line, and the write signal W is input to the gate electrode. This is because a transistor Q7e is provided.

The operation of the MIS type nonvolatile memory transistor write circuit configured as described above will be described below.

During the write operation, the write signal W turns on the MOS enhancement type transistor Q7, and the write voltage vp is applied to the gate electrode of the MIS type nonvolatile memory transistor Q4.

Here, when the write data D makes the MOS enforcement transistor Q6 conductive, the potential of the bit line, which is the source electrode of the kIs type nonvolatile memory transistor Q4, becomes approximately equal to the ground potential. At this time, write voltage Vpf: MIS type non-volatile memory applied to gate voltage (IJ) A channel is formed on the substrate surface under the gate electrode of transistor Q4, and the potential of the substrate surface is equal to the source electrode potential. Becomes ground potential. Therefore, a high electric field is applied to the gate insulating film of the MIS type nonvolatile memory transistor Q4 through the gate electrode.
The MIS type nonvolatile memory transistor Q4 transitions from the erase state to the write state in which negative charges are trapped.

On the other hand, when the write data input MOS enhancement type transistor Q6 is cut off by the write data D, the bit line (B, L) which is the source electrode of the MIS type non-volatile memory transistor Q4 is connected to the bit line charging MOS from the power supply. They are quickly charged by the current supplied through the enhancement type transistor Q7, and the potential of the bit lines B and L is (potential of the write signal W) - (MOS enhancement type transistor Q).
7+7) threshold voltage). Thereafter, the source electrode of the MIS type nonvolatile memory transistor Q4 is charged by the charge supplied from the power supply through the load MOS depletion type transistor qs2, and the potential of the source electrode is (write voltage Vp) - (MIS type nonvolatile memory transistor IJ). ) The threshold voltage of transistor Q4 is reached at )t. At this time, the MOS
Since the write voltage Vp is applied to the gate electrode of the MIS type nonvolatile memory transistor Q4, an inversion layer is formed on the substrate surface under the gate electrode, and the potential of the substrate surface is set to the MIS type nonvolatile memory transistor Q4. It is approximately equal to the drain electrode potential of Q4, and becomes the power supply potential Vp. Therefore, no potential difference is generated between the gate electrode of MIS type nonvolatile memory transistor Q4 and the substrate surface under the gate electrode. Therefore, MIS type non-volatile memory transistor Q4
There is no change in the amount of charge trapped in the gate insulating film, and the MOS type volatile memory transistor Q4 remains in the erased state.

As described above, by providing the bit line charging MOS enhancement type transistor Q7''f, the source electrode 'tf of the MIS type non-volatile memory transistor Q4 is vaguely charged during the write operation to maintain the erased state, and when the write operation starts, the MIS type nonvolatile memory transistor Q
The time during which an electric field is generated in the gate insulating film of Q4 can be sufficiently shortened compared to the conventional method, and the MIS type non-volatile memory transistor Q, which was in the erased state by the write operation,
It is possible to prevent the amount of charge trapped in the gate insulating film No. 4 from changing.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention has great practical effects because a MOS type nonvolatile memory transistor in an erased state can maintain an erased state even during a write operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a write circuit for an hIs type nonvolatile memory transistor in an embodiment of the present invention, and FIG. 2 is a block diagram of a write circuit for an MIS type nonvolatile memory transistor in a conventional example. Qll Q4...kO8 type non-volatile memory transistor, Q2. Q6...MOS depletion type transistor, Q3. Q61 Q7...
・MOS enhancement type transistor, vP...
...Writing power supply, 01,02...Capacity,
W: Write signal line, D: Data line, B, L: Bit line.

Claims (1)

[Claims] The drain electrode of the MIS type nonvolatile memory transistor is connected to a power supply via a load, and the bit line, which is the source electrode of the MIS type nonvolatile memory transistor, is connected to the source electrode of the MIS type nonvolatile memory transistor.
the first M for data input where the source electrode is grounded;
1. A semiconductor memory circuit characterized in that the drain electrode of an OS type transistor is connected to the source electrode of a second MOS type transistor for charging a bit line connected to a power source.