JP3554572B2 - Non-volatile semiconductor circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a nonvolatile semiconductor memory device having an electric write / erase function, and more particularly to a nonvolatile semiconductor circuit having improved data retention characteristics.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device, for example, a storage device called an electrically-erasable NOR flash memory disclosed in Japanese Patent Application Laid-Open No. 3-219496 has been developed. A conventional NOR type flash memory has been configured by arranging memory cells having a floating gate type field effect transistor structure in a matrix. Here, the control gate of each memory cell whose drain terminal is directly connected to the data line is connected to a different word line, and the source terminals of all the memory cells are directly connected to a common source line.
[0003]
Erasing of memory cell data is performed in word line units, by applying a negative voltage to the control gate of the memory cell, opening the data line, and applying a positive voltage to the source terminal. At this time, a high electric field is applied to the gate oxide film on the source terminal side of the memory cell, and electrons accumulated in the floating gate are pulled out to the source terminal by the Fowler-Nordheim tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases, and the erase operation is completed.
[0004]
The positive voltage applied to the source line in the erase operation is also applied to the source terminals of non-selected memory cells other than the memory cell selected in response to the erase command. In a non-selected memory cell, a weak electric field is applied to the gate oxide film from the floating gate in the direction of the source terminal, and a disturb phenomenon relating to the source terminal occurs in which electrons accumulated in the floating gate gradually escape. Therefore, it has been necessary to apply a positive voltage to the control gate of the non-selected memory cell in order to prevent the threshold voltage from lowering due to the emission of electrons.
[0005]
[Problems to be solved by the invention]
When an erase operation is performed, in a non-selected memory cell, different positive voltages are applied to the control gate and the source terminal, respectively, so that the non-selected memory cell is turned on, and the source terminal is connected to the drain terminal via the non-selected memory cell. A charging current for charging the capacity of the drain line flows. At the end of the erasing operation, the positive voltage applied to the source terminal becomes 0 V, so that a discharge current flows, in which the charges accumulated in the drain line are discharged to the source terminal side through the non-selected memory cells. Hot electrons are generated in the non-selected memory cells by the charge / discharge current, and electrons are injected into the floating gate. There is a problem that the injection amount of hot electrons increases in proportion to the number of times of erasing, and the threshold voltage increases.
[0006]
Regardless of the erase operation, generally, in the operation of extracting electrons from the floating gate using the diffusion layer end of the source terminal or the drain terminal of the memory cell, it is necessary to apply a positive voltage to the control gate of the unselected memory cell. As the number of times of writing and erasing increases, the amount of hot electrons injected increases, causing a problem that the threshold voltage increases.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following circuit configuration and system.
[0008]
For example, as shown in FIG. 1, in a memory array in which nonvolatile semiconductor memory cells having floating gates are arranged in a matrix, a plurality of memory cells arranged in parallel between data lines and source lines; MOS transistors are arranged in parallel with the memory cells, and each data line is connected to a source line via the MOS transistor.
[0009]
Further, in the operation of extracting electrons from the floating gate of the memory cell, a positive voltage is applied to the source line in advance, and a positive voltage is applied to the gate of the MOS transistor.
By turning on the MOS transistor, the voltage at the drain terminal is made substantially equal to the voltage at the source terminal. Thereafter, a positive voltage for disturb prevention relating to the above-mentioned source terminal is applied to the control gate of the unselected memory cell, and a negative voltage is applied to the control gate of the selected memory cell, thereby extracting electrons from the floating gate.
[0010]
On the other hand, after the pull-out operation is completed, first, the voltage of the control gate of the selected memory cell is set to 0 V, the voltage of the control gate of the non-selected memory cell is set to 0 V, and the voltage of the source is set to 0 V to charge the drain line. The generated charges are drawn to the source line side, and the voltage on the drain line side is set to approximately 0V. Further, the voltage of the gate of the MOS transistor inserted in parallel is set to 0 V, and the drain region is electrically separated from the source region.
[0011]
[Action]
In the present invention, before the operation of extracting electrons from the floating gate is started, the drain terminal and the source terminal of the non-selected memory cell are set to substantially the same voltage by the MOS transistor connected in parallel to the memory cell. Therefore, when a positive voltage is applied to the control gate of the unselected memory cell, a transient current does not flow through the unselected memory cell even when the threshold voltage of the unselected memory cell is low. As a result, the generation of hot electrons in unselected memory cells is suppressed, and no electron is injected into the floating gate.
[0012]
Also, when the operation of extracting electrons from the floating gate is completed, first, the voltage of the control gate of the selected memory cell and the non-selected memory cell is returned to 0 V, so that the drain terminal and the source terminal are kept at substantially the same voltage. Therefore, no transient current flows through the unselected memory cells. Thereafter, the source terminal voltage is set to 0 V, and the accumulated charge at the drain terminal is discharged via the MOS transistor. Then, the gate voltage of the MOS transistor is returned to 0 V.
[0013]
As described above, since charging and discharging of the drain terminal are performed through the MOS transistor provided in parallel with the memory cell, hot electron injection does not occur in the memory cell, and the threshold voltage does not change.
[0014]
【Example】
A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a circuit configuration of a nonvolatile semiconductor memory cell. Here, a NOR type memory cell is used as a nonvolatile semiconductor memory cell, and two bits for a word line and two bits for a data line are shown. However, the memory cells and the arrangement are not limited thereto.
[0015]
The control gates of the memory cells M11 and M21 connected to the data line D1 are connected to different word lines W1 and W2, and the source terminals are connected to the common source line together with the source terminals of the memory cells M12 and M22. N-type MOS transistors 1 and 2 are arranged between the data line and the source line in parallel with the memory cell, and the gates of the n-type MOS transistors 1 and 2 are connected to a common control line SG. Each data line is connected to a peripheral circuit 3 of a decoder and a sense amplifier, and each word line is connected to a decoder 4. In the NOR type memory cell, data writing is performed by hot electron injection at the drain end, and erasing is performed by tunnel emission of electrons from the source terminal side in word line units.
[0016]
An example of the voltage relationship of the control line SG at the time of rewriting and reading data of the memory cell M11 and an example of the timing at the time of erasing are shown below. At the time of writing data, the voltage of the data line D1 is set to, for example, 5V, and the word line W1 is set to 10V. Note that the common source line is at 0V. Here, the control line SG is maintained at 0 V, and the MOS transistors 1 and 2 are turned off. A current flows from the data line to the source line via the memory cell M11, and electrons are injected into the memory cell M11 by hot electron injection. In reading, the data line voltage is set to, for example, 1V, 5V is applied to the word line W1, and the control line SG is set to 0V. The data line voltage fluctuates according to the threshold voltage of the memory cell, and the fluctuation value is read by a sense amplifier.
[0017]
In the erase operation, a voltage is applied to each signal line according to the voltage timing chart shown in FIG. The data of all the memory cells connected to the word line W1 can be erased collectively. The data lines D1 and D2 are left open on the decoder side, and a voltage of about 5 V is applied to the source lines. At about the same time, 5V is applied to the control line SG, and the data lines D1 and D2 are charged from the source line side via the MOS transistors 1 and 2. After each data line is charged, for example, 5 V is applied to the word line W2 for the unselected memory cell, and -8 V is applied to the word line W1. With respect to M11 and M12, the word lines W1 and W2 are returned to 0 V after the time for emitting electrons from the floating gate to the source terminal side by the tunnel phenomenon has elapsed. Further, the source terminal is set to 0V, and after the electric charge accumulated in the data line via the MOS transistors 1 and 2 is drawn out to the source line, the control line SG is set to 0V.
[0018]
A second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a circuit diagram in the case of using a nonvolatile semiconductor memory cell that rewrites data using a tunnel phenomenon. In this embodiment, erasing is performed by injecting electrons into the floating gate using the tunneling phenomenon on the entire channel of the memory cell, and writing is performed using the tunneling phenomenon of electrons from the floating gate to the diffusion layer on the drain terminal side. Do. Here, the source lines S1 and S2 are separated by a MOS transistor connected to the signal line SS. As in the first embodiment, MOS transistors 1 and 2 are arranged in parallel with each memory cell.
[0019]
An example of a voltage relationship of the control line SG at the time of rewriting and reading data of the memory cell M11 and an example of a timing at the time of writing are shown below. When erasing data, the voltages of the source lines S1 and S2 are set to 0V, and the word line W1 is set to, for example, 15V. Here, the control line SG may be any of 0V to 5V. Electrons are injected from the channel side into the floating gates of all the memory cells on the word line W1, and the memory cell enters an erased state with a high threshold voltage state. In reading, the data line voltage is set to, for example, 1V, 5V is applied to the word line W1, and the control line SG is set to 0V. The data line voltage D1 fluctuates according to the threshold voltage of the memory cell, and this fluctuation value is read by the sense amplifier.
[0020]
FIG. 4 shows a timing chart of the voltage applied to each signal line for the write operation. When data is written to the memory cell M11 and the erase state is maintained in the memory cell M12, voltages of 5 V and 0 V are applied to the data lines D1 and D2 from the decoder side. At this time, SS is set to 0 V, and the source lines S1 and S2 are opened. Also,
SD is set to 7 V, and the voltage of the data line is applied to the drain terminal of each memory cell. Next, 5V is applied to the control line SG, and the data lines D1 and D2 are charged through the MOS transistors 1 and 2 to the source lines S1 and S2. After each data line is charged, for example, 5 V is applied to the word line Wn for the unselected memory cell, and -8 V is applied to the word line W1. With respect to M11 and M12, the word lines W1 and Wn are returned to 0 V after the time for emitting electrons from the floating gate to the drain terminal side by the tunnel phenomenon has elapsed. Further, the data lines D1 and D2 are set to 0V, the charges accumulated in the data lines via the MOS transistors 1 and 2 are drawn out to the data line, and finally the control line SG is set to 0V.
[0021]
In this embodiment, data writing is performed by lowering the threshold voltage of the memory cell by using a tunnel phenomenon between the drain-side diffusion layer region and the floating gate. Even in this case, as shown in the first embodiment, the voltage of the unselected word line needs to be set to, for example, 5 V, and the source line is charged via the memory cell connected to the unselected word line. . At this time, the threshold voltage may fluctuate due to the injection of hot electrons generated in the memory cell into the floating gate. However, as shown in the present embodiment, the MOS transistors 1 and 2 are turned off. By hot-charging the source line in advance, generation of hot electrons in the memory cell can be prevented.
[0022]
A third embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows a cross-sectional view of a memory cell and an outline of its operation. In the second embodiment, the writing of data into the memory cell is performed by using the phenomenon of electron tunneling from the floating gate to the diffusion layer on the drain side. In this embodiment, however, the data is written from the floating gate to the source diffusion layer side. This is done using the phenomenon of electron tunneling.
[0023]
That is, as shown in FIG. 4, after receiving a write operation command, 5V is applied to the data line D1, 0V is applied to the control line SS, and 7V is applied to SD. Here, the drain line in the block is connected to the data line, and the source line is separated from the common source line. Next, 7V is applied to the control line SG, and the voltage on the drain side of the memory cell appears on the source line S1 via the MOS transistor 1. Subsequently, -8 V is applied to a selected word line and 5 V is applied to an unselected word line. In the memory cell M1 on the selected word line W1, a high electric field is applied between the source terminal and the floating gate.
[0024]
Here, when the memory cell structure shown in FIG. 5 is adopted, the impurity concentration of the diffusion layer 18 on the source side is set to be higher than the impurity concentration of the diffusion layer 16 on the drain side by one digit or more. Then, electrons are emitted from the floating gate according to the tunnel phenomenon, and the threshold voltage of the memory cell becomes low. That is, data is written using the phenomenon of electron tunneling from the floating gate to the source diffusion layer side.
[0025]
In this embodiment, since the amount of tunneling of electrons from the drain terminal side can be suppressed, in the nonvolatile memory cell, the fluctuation in the amount of charge in the floating gate is suppressed even in general for 10 years of continuous data reading. Must be done. However, at the time of reading, a voltage is applied to the data line, and a change in the voltage is read by a sense amplifier or the like. Therefore, a weak electric field is applied between the drain terminal and the floating gate electrode of the memory cell connected to the data line, and the floating gate is gradually increased. The electrons inside are emitted to the drain terminal (disturb phenomenon on the drain terminal side).
[0026]
In order to suppress the fluctuation of the threshold voltage due to this, conventionally, the voltage of the drain terminal has been limited to about 1V. By adding the MOS transistors 1 and 2 as shown in this embodiment to the circuit, electrons can be tunneled from the source terminal side, so that the concentration of the diffusion layer on the drain side can be reduced. This makes it possible to suppress the amount of electrons emitted from the floating gate to the drain terminal during reading. As a result, the limitation on the drain terminal voltage is relaxed to about 3 V, and the design of the sense amplifier can be facilitated.
[0027]
A fourth embodiment of the present invention will be described with reference to FIG. The memory cell used in FIG. 6 has the cross-sectional view shown in FIG. A rewriting method similar to that of the third embodiment is employed. As a result, the influence of the drain disturb phenomenon is reduced, and the drain terminals of the two memory cells M11 and M12 on the same word line W1 can be connected to the common data line D1. Here, MOS transistors 1 and 2 are provided for the two source lines S1 and S2.
[0028]
At the time of writing, the MOS transistor 1 is turned on when writing data to M11, and the MOS transistor 2 is turned on when writing data to M12. Further, in order to prevent a malfunction at the time of reading, the control line on the source side is separated into two SS1 and SS2.
[0029]
In this embodiment, in addition to the effects shown in the third embodiment, the number of data lines can be reduced, and the effective memory cell area can be reduced.
[0030]
A fifth embodiment of the present invention will be described with reference to FIG. In the present embodiment, each of the source-side control lines SS and SG is one in the fourth embodiment. Therefore, the word lines of the memory cells connected to the source lines S1 and S2 are separated from each other. Also in this embodiment, in addition to the effects shown in the third embodiment, the number of data lines can be reduced, and the effective memory cell area can be reduced.
[0031]
【The invention's effect】
According to the present invention, in a nonvolatile semiconductor memory device in which a threshold voltage of a memory cell is changed by using a tunnel emission phenomenon of electrons between a floating gate electrode and a drain or a source diffusion layer, a memory cell is selected at the time of electron tunnel emission. Variations in the threshold voltage of the memory cell due to the generation of hot electrons when charging the drain line or the source line via the memory cell on the non-word line can be suppressed, and the data retention characteristics of the memory cell can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of a memory cell according to a first embodiment of the present invention.
FIG. 2 is a timing chart of each signal line in the first embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a configuration of a memory cell according to a second embodiment of the present invention.
FIG. 4 is a timing chart of each signal line in a second embodiment of the present invention.
FIG. 5 is a sectional view of a flash memory cell according to a third embodiment of the present invention.
FIG. 6 is an explanatory diagram showing a configuration of a memory cell according to a fourth embodiment of the present invention.
FIG. 7 is an explanatory diagram showing a configuration of a memory cell according to a fifth embodiment of the present invention.
[Explanation of symbols]
Reference numerals 1, 2,... MOS transistors, 3.... Peripheral circuits such as sense amplifiers, 4..

Claims (3)

A memory array in which nonvolatile semiconductor memory cells capable of electrically writing and erasing data to a floating gate are arranged in a matrix, wherein a plurality of the nonvolatile semiconductor memory cells are connected between a data line and a source line; Each data line is connected to a source line via a first MOS transistor connected in parallel to the nonvolatile semiconductor memory cell, and each source line is connected to a common source line via a second MOS transistor; In the operation of extracting electrons from the floating gate of the nonvolatile semiconductor memory cell, the second MOS transistor is turned off in advance to electrically separate a source line from a common source line, and to use the first MOS transistor. And electrically connecting the voltage of the data line and the source line. 2. The operation according to claim 1, wherein in the operation of extracting electrons from the nonvolatile semiconductor floating gate of the nonvolatile semiconductor memory cell, after the operation of extracting electrons is completed, the voltage of a word line connected to the gate of the nonvolatile semiconductor memory cell is reduced. A non-volatile semiconductor circuit that electrically disconnects the data line from the source line by turning off the first MOS transistor after setting the voltage to 0V; 2. The operation according to claim 1, wherein in the operation of extracting electrons from the floating gate of the nonvolatile semiconductor memory cell, a voltage of a data line and a source line are electrically connected in advance using the first MOS transistor. After the voltage of the word line connected to the gate of the nonvolatile semiconductor memory cell is set to a predetermined voltage necessary for erasing, and after the operation of extracting electrons is completed, the voltage of the word line is set to 0 V, A non-volatile semiconductor circuit that electrically separates a data line from a source line by turning off the MOS transistor.

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