JPH02133960A - Writable nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory device from which a data can be read out and to which the data can be written by a method wherein a voltage is applied to a gate of a memory cell transistor from a single power supply. CONSTITUTION:During a readout operation, a ground voltage of 0V is used as a voltage to be applied to a gate of a memory cell transistor 4 from which a data is to be read out. Accordingly, in the same way as during a write operation, a power supply used to apply the voltage to the gate of the memory transistor 4 from which the data is to be read out is not required. In addition, even when memory information is erased, the ground voltage of 0V may be used as individual gate voltages for memory transistors 3 to 6. Accordingly; a power supply required when the memory information is erased is only a power supply used to apply a voltage to a drain line 1. Accordingly, during both the write operation and the readout operation, the power supply used to apply the voltage to the gate of the memory transistor required in addition to the power supply used to apply the voltage to the drain line may be only one power supply used to apply the voltage to a gate of a nonselective memory transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a writable nonvolatile semiconductor memory device having a memory cell array whose basic unit is a cascade of MOS transistors.

[Prior art] As a conventional writable nonvolatile semiconductor memory device, MOS
Devices using transistors as memory cells are known. Recently, as one of the configurations of a memory cell array of such a semiconductor memory device, the document “IEDM 87-2
5.6". This uses multiple enhancement-type MOS transistors connected in cascade instead of a single MOS transistor as the basic unit of the memory cell array configuration. The principle of writing into a conventional memory cell using an enhancement type MOS transistor was as follows.

Generally, writing to a MOS transistor is performed by injecting electrons into its floating gate. One method for this electron injection is to cause a channel current to flow through the MOS transistor in an avalanche state.

FIG. 5 is a graph showing the relationship between the gate voltage and threshold voltage of a single enhancement type MOS transistor when its drain voltage is 9V. In the figure, the horizontal axis is the gate voltage vG, and the vertical axis is the threshold voltage Vth.

Referring to the figure, when the drain voltage is a constant value of 9V, MO
S) The transistor threshold voltage Vth is the gate voltage vG
It suddenly increases when the voltage is between 8v and 14V. This means that the PN junction of the MOS transistor has a gate voltage vG
This means that the voltage is in an avalanche state between 8V and 14V.

Therefore, the gate voltage vG of the MOS transistor is 8V.
The most efficient writing state occurs at ~14V. Conversely, when the gate voltage vG is less than 8V or greater than 14V, the writing level is extremely low or no writing is performed. Generally, such MOS
Writing to a MOS transistor, which is a memory cell, is performed by utilizing the characteristics of the transistor. Note that when writing is performed under the conditions of a drain voltage of 9V and a gate voltage of 9.5V, the threshold voltage of the written MOS transistor becomes approximately 4.5V.

Figure 4(a) shows the enhancement type MOS described earlier.
2 is a diagram illustrating an example of a memory cell array composed of transistors, and also a diagram illustrating voltages applied to the gates of each memory cell transistor when writing to the memory cell transistor 19. FIG. As mentioned earlier,
The optimal gate voltage for putting the MOS transistor in the write state was 8V to 14V when the drain voltage was 9V.

Therefore, when the drain voltage is set to 9V, the gate voltage of the memory cell transistor 19 for writing must be within this range. In addition, the voltage at each gate of memory cell transistors 16 to 18 that do not perform writing is 8V to 8V.
Must be outside the 14V range. Furthermore, since a channel current must flow through the memory cell transistor for writing, an appropriate voltage must be applied between the drain and source. Therefore, as shown in the figure,
Only the gate voltage of the memory cell transistor 19 for writing is set to 9.5V, and 9V is applied to the drain line 1. Furthermore, the source line 2 is provided with a ground potential OV. However, in order to write to the memory cell transistor 19, it is necessary to transmit the voltage 9V of the drain line 1 to the drain of the memory cell transistor 19 to be written, so the memory cell transistors 16 to 18 that are not to be written are turned on. There is a need to.

However, at this time, considering that some of the memory cell transistors 16 to 18 that are not to be programmed have already been programmed and have a threshold voltage of 4.5V, the gate voltage should be set to 4.5V or higher. must be done. Furthermore, memory cell transistors 16 to 18 that do not perform writing
The gate voltage of should be outside the range of 8v to 14V, as mentioned earlier. Taking these things into consideration, 21V is applied to the gates of each of the memory cell transistors 16 to 18 that are not to be written.

Next, reading from the MOS transistor will be explained. The written MOS transistor has electrons accumulated in its floating gate, and its threshold value has increased to about 4.5V. Therefore, the drain
If a low voltage is applied between the source, the gate voltage will be 4.5V.
If the gate voltage is higher than 4.5V, the drain current is in the ON state and flows, but if the gate voltage is smaller than 4.5V, the gate voltage is in the OFF state and no drain current flows. Conversely, the threshold voltage of a MOS transistor to which writing has not been performed remains at its initial value. Therefore, in a MOS transistor to which writing has not been performed, a drain current flows even if the gate voltage is smaller than 4.5 V as long as the gate voltage is larger than the initial threshold voltage. Reading is performed by utilizing the difference in characteristics between a MOS transistor to which writing has been performed and a MOS transistor to which writing has not been performed.

Similar to FIG. 4(a), FIG. 4(,b) is a diagram showing an example of a memory cell array composed of the enhancement type MOS transistors mentioned above, and also shows a case where reading is performed from the memory cell transistor 17. FIG. 3 is a diagram showing voltages applied to each memory cell transistor in FIG. As shown in the figure, the memory cell transistor 17 to be read is
By setting the gate voltage to 4■, it can be determined whether or not writing is being performed. That is, if writing is being performed, it is in the OFF state, and if writing is not being performed, it is in the ON state. Furthermore, memory cell transistor 1
7 is in the ON state, 1V is applied to the drain line 1, and the source line 2 is grounded.
It is set as v. However, in order to apply the respective voltages of drain line 1 and source line 2 to the drain and source of memory cell transistor 17 to be read, it is necessary to
8. and 19 must all be in the ON state. Therefore, memory cells 15, 18 . Memory cell transistors 16, 18 . and 19, the gate voltages are all 7V.

The following is a write-inhibited time when writing is not desired.

FIG. 4(c), like FIGS. 4(a) and 4(b), is a diagram showing an example of a memory cell array composed of the enhancement type MOS transistors mentioned above, and also shows each memory cell array when write is prohibited. FIG. 3 is a diagram showing voltages applied to memory cell transistors.

However, the gate voltage of each memory cell transistor is the one in the case where the memory cell transistor 19 is temporarily selected as the memory cell transistor to be written. Referring to the figure, both drain line 1 and source line 2 are provided with ground potential Ov. Therefore, even if all memory cell transistors 16 to 19 are in the ON state, no channel current flows through any of the four memory cell transistors and no writing is performed.

Note that ultraviolet irradiation or the like is generally used as a method for erasing information stored in a MOS transistor.

[Problems to be Solved by the Invention] Writing and reading are performed as described above in a conventional writable nonvolatile semiconductor memory device using a memory cell array configured using cascade-connected enhancement type MOS transistors as a basic unit. It was carried out in

Therefore, different voltages must be applied to the gates of selected memory cell transistors and the gates of unselected memory cell transistors both during writing and reading. Furthermore, since both of these voltages are not Ov, two voltage sources other than ground are required.

That is, in addition to a power supply for applying a voltage to the drain line, two power supplies for applying a gate voltage to the memory cell transistor are required both during writing and during continuous data writing.

Therefore, it was very inconvenient to use as a storage device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a nonvolatile semiconductor memory device that can perform reading and writing by applying a voltage to the gates of memory cell transistors using a single power supply.

[Means for Solving the Problems] In order to achieve the above objects, in a writable nonvolatile semiconductor memory device according to the present invention, a memory cell array thereof is configured as follows.

All memory cell transistors constituting the memory cell array have a floating gate, a tunnel oxide film in part or all of the lower part of the floating gate, and a drain diffusion region in at least a part of the tunnel oxide film. A MOS) transistor which has a depletion type characteristic in an initial state where no charge is accumulated in the floating gate, and which can have an enhancement type characteristic in a written state where a charge is accumulated in the floating gate. . MO as above
S) A memory cell array was constructed by connecting transistors in cascade and using them as a basic unit.

[Effect]

Since all MOS transistors constituting the memory cell array have a tunnel oxide film, electron injection into the floating gate of the memory cell transistor during writing can be performed by the tunnel effect. When electrons are injected into the floating gate by the tunnel effect, the efficiency hardly depends on the channel current of the memory cell transistor. Therefore, there is no need to apply a high voltage between the drain and source as in the conventional case, and both the drain and source voltages may be at the ground potential Ov.

Furthermore, the characteristics of the memory cell transistor to which writing has been performed can be changed from the depletion type before writing to the enhancement type. Therefore, if the characteristics of the memory cell transistor are set to the enhancement type after writing, the following reading method becomes possible.

That is, whether or not writing has been performed in the memory cell transistor to be read, that is, the stored information of the memory cell transistor can be determined from its characteristics (enhancement type or depletion type). That is, when a low voltage is applied between the drain and the source, if writing is not performed, the characteristics are of the depression type, so that the gate voltage becomes ON at Ov, and the drain current flows. On the other hand, if writing is being performed, its characteristics are enhancement type, so it is turned off at gate voltage OV.
state, and no drain current flows.

Therefore, in order to read the stored information of the memory cell transistor, it is sufficient to set the gate voltage of the memory cell transistor to be read to Ov.

As described above, in the nonvolatile semiconductor memory device according to the present invention, the ground potential Ov, which has conventionally been a voltage source applied only to the source line, can be used as a voltage source during writing and reading. Therefore, the number of voltage sources conventionally required to supply a voltage other than the ground potential Ov to the gate of the memory cell transistor during writing and reading can be reduced. This allows writing and reading with a single power supply.

[Example] FIG. 3(a) is a plan view showing an example of a case where a memory cell transistor used in this example is patterned on a semiconductor substrate. Referring to the figure, 15 is a semiconductor substrate, 12
11 is a source diffusion layer, 11 is a drain diffusion layer, 13a is a floating gate, and 13b is a control gate. Further, 14a is a tunnel oxide film.

Further, FIG. 3(b) is a diagram schematically showing a cross section of a memory cell transistor patterned as shown in FIG. 3(a) in the direction of straight line AA'. Referring to the figure, semiconductor substrate 1
5, a source diffusion layer 12 and a drain diffusion layer 11 are formed. Further, a floating gate 13a and a control gate 13b are formed on the semiconductor substrate 15 between the source diffusion layer 12 and the drain diffusion layer 11.

At this time, the oxide film under the floating gate 13a is a tunnel oxide film 14a, which is 14% larger than a normal gate oxide film.
It is thin, about 00A or less.

Further, FIG. 3(c) is a cross-sectional view taken along straight line BB' of the memory cell transistor patterned as shown in FIG. 3(a). Referring to the figure, a normal oxide film 14b having a floating gate 13a therein is formed on a semiconductor substrate 15.
is formed. Furthermore, a control gate 13b is formed in the upper layer. Note that electron injection from the drain diffusion layer 11 to the floating gate 13a due to the tunnel effect is caused by the injection of electrons into the floating gate 13a from the drain diffusion layer 11 and the source diffusion layer 12.
The voltage applied to the control gate 13b is set to Ov, and a high voltage of 10V to 15V is applied to the control gate 13b.

FIG. 2 is a graph showing the relationship between the gate voltage and drain current of the memory cell transistor used in this example.

In the figure, the horizontal axis is the gate voltage VG, and the vertical axis is the drain current I0.

The memory cell transistor used in this embodiment exhibits a depletion type characteristic in an initial state before writing is performed as shown in FIG. 2(a). Note that the threshold voltage in this case is assumed to be -2V in the following description. When writing is performed, charge is accumulated in the floating gate, and the threshold voltage increases, and its characteristics exhibit an enhancement type as shown in FIG. 2(b). Note that the threshold voltage in this case is assumed to be 2V in the following description.

In this example, the structure is as described above, and
Memory cell transistors having the above characteristics are connected in cascade to form a memory cell array.

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 1(a) is a diagram showing the configuration of the memory cell array and the voltages applied to the memory cell transistors 3 to 6 when writing to the memory cell transistor 4. Referring to the figure, the gate voltage of memory cell transistor 4 to which writing is performed is 18V, and the voltages of memory cell transistors 3, 5 and 6 which are not to be written are all 5/5/1.
■.

Therefore, memory cell transistors 3 to 6 are all turned on regardless of whether writing has already been performed or not. Furthermore, drain line 1 and source line 2
are both grounded, giving Ov. Therefore, the potentials of the drain line 1 and the source line 2 are transmitted to the drains and sources of the memory cell transistors 3 to 6, and all become Ov. However, since a high voltage of 18 V is applied to the gate of the memory cell transistor 4 for writing, a tunnel effect occurs. Therefore, electrons are injected into the floating gate of memory cell transistor 4 and writing is performed. This means that its characteristics have changed from a depression type to an enhancement type.

Note that the write-inhibited state may be handled as follows.

FIG. 1(b) shows the voltages applied to the memory cell transistors 3 to 6 when no writing is performed, as shown in FIG. 1(a).
It is a figure shown similarly to. The figure shows a case where memory cell transistor 4 is selected as the memory cell transistor to be written. Therefore, the voltage applied to each gate of memory cell transistors 3 to 6 is the same as when writing to memory cell transistor 4. However, a voltage of 18 V is applied to the drain line 1, and the source line 2 is electrically disconnected from the ground and placed in a floating state. Therefore, even if all of the memory cell transistors 3 to 6 are in the ON state, writing to the memory cell transistor 4 due to the tunnel effect does not occur.
No channel current flows through any memory cell transistor.

As mentioned above, during writing, the gate of the memory cell transistor 4 to which writing is to be performed and the memory cell transistors 3, 5, . As in the conventional case, two power supplies are required for applying voltages to the respective gates of 6 and 6. However, the ground potential Ov is used as the voltage applied to the drain line 1, unlike the conventional case. Therefore, 18V can be applied to the gate of the memory cell transistor 4 by using the power source for applying the voltage to the drain line 1 as the power source for applying the voltage to the gate of the memory cell transistor 4 to which writing is desired.

Moreover, by doing this, there is no problem even when writing is prohibited. In other words, when writing is prohibited, the voltage of the drain line 1 only needs to be set to 18V, so the voltage can be applied to both the gate of the memory cell transistor 4 and the drain line 1 from the power supply for applying voltage to the drain line 1. .

Next, the case of reading will be explained.

FIG. 1(C) is a diagram showing the voltages applied to the memory cell transistors 3 to 6 when reading is performed from the memory cell transistor 4, similar to FIGS. 1(a) and 1(b). Referring to the figure, the gate voltage of memory cell 4 to be read is the ground potential OV, and the gate voltage of memory cell transistors 3.5 and 6 to be read is all 5V.
shall be.

Therefore, memory cell transistor 3 that does not perform reading
．． 5. and 6 are all in the ON state regardless of whether writing is being performed or not. Furthermore, 1V is applied to the drain line 1, and the ground potential Ov is applied to the source line 2. As a result, IV is applied to the drain of the memory cell transistor 4 to be read, and Ov is applied between the sources. On the other hand, since the gate voltage of the memory cell transistor 4 is OV, if the memory cell transistor 4 is a depression type, it is in an ON state and a drain current flows. However, if it is an enhancement type, it is in an OFF state and no drain current flows. That is, if writing is not performed to the memory cell transistor 4, the characteristics of the memory cell transistor 4 remain in the depletion type, so that a drain current flows. However, if writing is performed, the characteristics of the memory cell transistor are of the enhancement type, and no drain current flows. Therefore, the stored information of the memory cell transistor 4 to be read can be read depending on the presence or absence of the drain current.

As described above, during continuous reading, the ground potential Ov is used as the voltage applied to the gate of the memory cell transistor 4 to be read. Therefore, as in the case of writing, a power source for applying a voltage to the gate of the memory cell transistor 4 to be read is not required. Note that an appropriate circuit is provided between the power supply for voltage application to the drain line 1 and the drain line 1, and the high voltage 18V from the power supply for voltage application to the drain line 1 is set to 1V. can be applied to

Furthermore, a case will be described in which information stored in a memory cell transistor is erased.

FIG. 1(d) shows the voltages applied to the memory cell transistors 3 to 6 when erasing information stored in all of the memory cell transistors 3 to 6.
, and (c). Referring to the figure, ground potential Ov is applied to all gates of memory cell transistors 3 to 6, and 18V is applied to drain line 1. Further, the source line 2 is electrically disconnected from the ground and placed in a floating state. by this,
Memory cell transistor 3 closest to drain line l
From there, the stored information is sequentially erased from the memory cell transistors farthest from the drain line 1. This is based on the following principle.

In other words, since the gate voltage is Ov, when writing is performed on the memory cell transistor 3 and charges are accumulated in the floating gate, a tunnel effect occurs due to the drain voltage of 18V, and the charges are tunneled, contrary to the case of writing. released into the layers. The characteristics of the memory cell transistor 3 which has discharged charges from the floating gate return from the enhancement type to the initial state of the depletion type.

On the other hand, since Ov is applied to the gate of the memory cell transistor 3, the memory cell transistor 3 is turned on and the voltage 18V on the drain line 1 is transmitted to the drain of the next memory cell transistor 4. Regarding memory cell transistors in which no charge is accumulated,
Since it has depletion type characteristics, it is in an ON state if the gate voltage is OV. Therefore, the drain voltage of 18V is transmitted to the next memory cell transistor. Therefore, similarly to memory cell transistor 3, storage information is erased for memory cell transistor 4 as well. Thereafter, the stored information of memory cell transistors 5 and 6 is similarly erased, and the stored information of all memory cell transistors 3-6 is erased.

As described above, even when erasing stored information, the ground potential Ov may be used as the gate voltage of each of the memory cell transistors 3 to 6. Therefore, the only power source required when erasing stored information is the power source for applying voltage to the drain line 1.

Furthermore, erasure of stored information is also possible by irradiation with ultraviolet rays.

[Effects of the Invention] As described above, the memory cell array of the nonvolatile semiconductor memory device according to the present invention has a tunnel oxide film, has depletion type characteristics as an initial characteristic before writing, and further has: At the end of writing, since the memory cell transistor is composed of a cascade connection of memory cell transistors having enhancement type characteristics, the following effects can be brought about.

During both writing and reading, the voltages applied to the memory cell transistors are at most two voltages in addition to the ground voltage Ov. Therefore, the power source for applying voltage to the drain line during writing and reading can be commonly used as the power source for applying voltage to the gate of the selected memory cell transistor for writing or reading. Therefore, in addition to the power supply for applying voltage to the drain line during writing and reading, the power supply for applying voltage to the gate of the memory cell transistor that is required is the power supply 1 for applying voltage to the gate of the unselected memory cell transistor. It turns out that it is enough. In other words, in addition to the conventional power supply for applying voltage to the drain line, two
Write and read operations that require a power source can now be performed with a single power source.

[Brief explanation of the drawing]

FIG. 1 shows the structure of a memory cell array of a non-volatile semiconductor memory device which is an embodiment of the present invention, as well as write/write-protection and
Diagram showing voltage applied to memory cells in read/erase state,
FIG. 2 is a diagram showing the characteristics of the memory cell transistor used in the present invention, FIG. Figure 4 shows an example of the structure of a memory cell array of a conventional non-volatile semiconductor memory device, as well as a
FIG. 5 is a diagram showing the voltage applied to the memory cell transistor in a read/write inhibited state, and FIG. 5 is a diagram showing the characteristics of the memory cell transistor used in the conventional nonvolatile semiconductor memory device shown in FIG. . In the figure, 1 is a drain line, 2 is a source line,
3 to 6 are memory cell transistors each having a tunnel oxide film; 11 is a drain diffusion layer; 12 is a source diffusion layer; 13a is a floating gate; 13b is a control gate; 14a is a tunnel oxide film; 14b is an oxide film; Semiconductor substrates 16 to 19 are memory cell transistors each having no tunnel oxide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A nonvolatile memory device including at least two or more memory cells connected in series, wherein the memory cell includes a depression type MOS transistor, and the depression type MOS transistor is connected to a semiconductor substrate. , a source diffusion region formed in the semiconductor substrate, a drain diffusion region formed in the semiconductor substrate, a floating gate formed above the semiconductor substrate, and at least above the drain diffusion region and below the floating gate. a tunnel oxide film formed on at least a portion of the MOS transistor, thereby accumulating charge in the floating gate due to a tunnel effect during writing, thereby changing the depletion type MOS transistor into an enhancement type MOS transistor. Possible non-volatile semiconductor memory device.