JPS61184337U - - Google Patents

Info

Publication number
JPS61184337U
JPS61184337U JP5764986U JP5764986U JPS61184337U JP S61184337 U JPS61184337 U JP S61184337U JP 5764986 U JP5764986 U JP 5764986U JP 5764986 U JP5764986 U JP 5764986U JP S61184337 U JPS61184337 U JP S61184337U
Authority
JP
Japan
Prior art keywords
voltage
operational amplifier
resistor
analog
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5764986U
Other languages
Japanese (ja)
Other versions
JPS6320191Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986057649U priority Critical patent/JPS6320191Y2/ja
Publication of JPS61184337U publication Critical patent/JPS61184337U/ja
Application granted granted Critical
Publication of JPS6320191Y2 publication Critical patent/JPS6320191Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のA/D変換回路の例を示す回路
図、第2図は本考案によるA/D変換回路の実施
例を示す回路図である。図において、2は演算増
幅器、4,5は抵抗、7〜9はトランジスタ、1
0は積分用コンデンサ、11は定電流源、12は
コンパレータ、21はポテンシヨメータ、22は
ボルテージホロアである。
FIG. 1 is a circuit diagram showing an example of a conventional A/D conversion circuit, and FIG. 2 is a circuit diagram showing an embodiment of an A/D conversion circuit according to the present invention. In the figure, 2 is an operational amplifier, 4 and 5 are resistors, 7 to 9 are transistors, and 1
0 is an integrating capacitor, 11 is a constant current source, 12 is a comparator, 21 is a potentiometer, and 22 is a voltage follower.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アナログ入力信号を増幅する演算増幅器と、定
電流によつて積分されるコンデンサと、該コンデ
ンサの蓄積電圧と前記演算増幅器の出力電圧とを
比較するコンパレータとによつて構成される一重
積分型アナログ―デイジタル変換回路において、
前記演算増幅器の反転入力端子と出力端子との間
に第1の抵抗を接続し、更に該反転入力端子に第
2の抵抗を接続し、該第2の抵抗の他端に、定電
圧を可変分圧するポテンシヨメータと該ポテンシ
ヨンメータにより変えられた電圧をうけるボルテ
ージホロアとからなるレベル調整回路を接続して
前記演算増幅器にバイアス電圧を与え、前記アナ
ログ入力信号の加えられる電圧の最大値の大きさ
に対応して、前記ボルテージホロアの入力に加え
られる定電圧の値を調整するようにしたことを特
徴とするアナログ―デイジタル変換回路。
A single-integration type analog device consisting of an operational amplifier that amplifies an analog input signal, a capacitor that integrates a constant current, and a comparator that compares the voltage stored in the capacitor with the output voltage of the operational amplifier. In the digital conversion circuit,
A first resistor is connected between the inverting input terminal and the output terminal of the operational amplifier, a second resistor is further connected to the inverting input terminal, and a constant voltage is variable at the other end of the second resistor. A level adjustment circuit consisting of a voltage dividing potentiometer and a voltage follower receiving the voltage changed by the potentiometer is connected to apply a bias voltage to the operational amplifier, and the maximum value of the voltage applied to the analog input signal is An analog-to-digital conversion circuit characterized in that the value of the constant voltage applied to the input of the voltage follower is adjusted in accordance with the magnitude of the voltage follower.
JP1986057649U 1986-04-18 1986-04-18 Expired JPS6320191Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986057649U JPS6320191Y2 (en) 1986-04-18 1986-04-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986057649U JPS6320191Y2 (en) 1986-04-18 1986-04-18

Publications (2)

Publication Number Publication Date
JPS61184337U true JPS61184337U (en) 1986-11-17
JPS6320191Y2 JPS6320191Y2 (en) 1988-06-06

Family

ID=30582373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986057649U Expired JPS6320191Y2 (en) 1986-04-18 1986-04-18

Country Status (1)

Country Link
JP (1) JPS6320191Y2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139759A (en) * 1975-05-28 1976-12-02 Canon Inc Comparison circuit
JPS5215654A (en) * 1975-07-28 1977-02-05 Nippon Electric Co Wire rope and its manufacture
JPS5298524A (en) * 1976-02-13 1977-08-18 Yashica Co Ltd Digital shutter circuit
JPS52156541A (en) * 1976-06-23 1977-12-27 Hitachi Ltd A-d converter
JPS5322473A (en) * 1976-10-29 1978-03-01 Seiko Epson Corp Electronic watch
JPS5322478A (en) * 1976-08-13 1978-03-01 Hitachi Ltd Indicator

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139759A (en) * 1975-05-28 1976-12-02 Canon Inc Comparison circuit
JPS5215654A (en) * 1975-07-28 1977-02-05 Nippon Electric Co Wire rope and its manufacture
JPS5298524A (en) * 1976-02-13 1977-08-18 Yashica Co Ltd Digital shutter circuit
JPS52156541A (en) * 1976-06-23 1977-12-27 Hitachi Ltd A-d converter
JPS5322478A (en) * 1976-08-13 1978-03-01 Hitachi Ltd Indicator
JPS5322473A (en) * 1976-10-29 1978-03-01 Seiko Epson Corp Electronic watch

Also Published As

Publication number Publication date
JPS6320191Y2 (en) 1988-06-06

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