JPS61183986A - Manufacture of semiconductor light emitting device - Google Patents

Manufacture of semiconductor light emitting device

Info

Publication number
JPS61183986A
JPS61183986A JP60022927A JP2292785A JPS61183986A JP S61183986 A JPS61183986 A JP S61183986A JP 60022927 A JP60022927 A JP 60022927A JP 2292785 A JP2292785 A JP 2292785A JP S61183986 A JPS61183986 A JP S61183986A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
mirror
layer
polished
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60022927A
Other languages
Japanese (ja)
Other versions
JPH0574956B2 (en
Inventor
Hiroko Nagasaka
長坂 博子
Naoto Mogi
茂木 直人
Naohiro Shimada
島田 直弘
Tadashi Komatsubara
小松原 正
Masaru Nakamura
優 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60022927A priority Critical patent/JPS61183986A/en
Publication of JPS61183986A publication Critical patent/JPS61183986A/en
Publication of JPH0574956B2 publication Critical patent/JPH0574956B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0207Substrates having a special shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18305Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] with emission through the substrate, i.e. bottom emission
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18361Structure of the reflectors, e.g. hybrid mirrors
    • H01S5/1838Reflector bonded by wafer fusion or by an intermediate compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054Methods of obtaining the confinement
    • H01S5/2059Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion

Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To obtain the title device of high output and high reliability which is easily produced, by a method wherein the first semiconductor substrate with a hetero junction structure and the second semiconductor substrate with a structure acting as current stricture or mode control are directly joined to each other. CONSTITUTION:A clad layer 12, an undoped active layer 13, and a clad layer 14 are successively grown above an N-GaAs substrate 11, thus forming a double hetero junction structure (first structure). Next, the surface of the clad layer 14 is polished into mirror. On the other hand, a P-SiC substrate 15 is provided with a metal mask in stripe form, and a high-resistant layer 16 is formed by front implantation, thus forming the second structure. The surface of the sub strate 15 is polished into mirror. The mirror-polished surfaces of the substrates 11, 15 are made opposed, brought into close contact, and adhered by heat treat ment. Next, the substrate 11 is removed, and the exposed surface of the clad layer 12 is polished into mirror; then, an N-SiC substrate (third semiconductor) 18 is adhered. A semiconductor laser chip is prepared by cutting this element for each stripe.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体レーザや発光ダイオード等の半導体発
光装置の製造方法に係わり、特に基板の接着を利用した
半導体発光装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor light emitting device such as a semiconductor laser or a light emitting diode, and particularly to a method of manufacturing a semiconductor light emitting device using bonding of substrates.

〔発明の技術的背景とその問題点) 半導体レーザにおいては、発振状態での活性層からの発
熱は、素子の電流−光出力特性を飽和させたり、また定
出力動作の場合には発熱による効率の低下が動作電流を
引下げ、それが更に熱を増加させる。このような正帰還
がかかつて、ついには発撮しなくなるような劣化を引起
こす。これらの点から特に高出力レーザや長期の信頼性
を要求される通信用レーザ等において、活性層の発熱を
いかに速くヒートシンクに導くかは重要な問題である。
[Technical background of the invention and its problems] In semiconductor lasers, heat generated from the active layer in the oscillation state saturates the current-optical output characteristics of the device, and in the case of constant output operation, the efficiency due to heat generation decreases. The reduction in the operating current reduces the operating current, which further increases heat. This kind of positive feedback eventually causes deterioration to the point where it stops firing. From these points of view, how quickly the heat generated in the active layer can be guided to the heat sink is an important issue, especially in high-power lasers and communication lasers that require long-term reliability.

従来の構造のレーザでは、活性層とヒートシンクとの間
に、少なくともクラッド層及びコンタクト層と云う熱伝
導性の悪い半導体材料が存在する。
In a laser having a conventional structure, semiconductor materials having poor thermal conductivity, called at least a cladding layer and a contact layer, are present between the active layer and the heat sink.

さらに、融着金属によっては、ジャンクショクを上にし
てマウントしなければならないので、厚い基板が介在し
ており、熱の発散は良くないものであった。
Furthermore, depending on the fusion metal, it is necessary to mount it with the junction facing upward, which requires a thick substrate, which results in poor heat dissipation.

また、半導体レーザは、その材料や用途に応じて様々な
構造を有するが、一般には活性層及びクラッド層を含む
ヘテロ接合構造部と、電流狭窄効果やモード制御効果を
有する構造部とが半導体基板表面に垂直方向に結合した
形で構成されているものが多い。例えば、第5図(a)
に示す如くm−EC0(モディファイド、エンペップイ
ド。
Semiconductor lasers have various structures depending on their materials and applications, but in general, a heterojunction structure including an active layer and a cladding layer, and a structure having a current confinement effect or mode control effect are formed on a semiconductor substrate. Many are composed of bonds perpendicular to the surface. For example, Fig. 5(a)
As shown in m-EC0 (Modified, Enpepoid.

コンファイニングレイツー。イン、オプチカルガイド)
構造と称される作り付は導波型レーザ(第16回国隔置
体素子コンファレンス、予稿集p153〜1)156.
1984年)では、半導体基板51上にダブルへテロ接
合構造部をなす活性層53及びクラッド層52.54と
、電流狭窄効果及び実効屈折率差によるモード制御効果
を有する電流阻止層54及び高屈折率層55とが、基板
51の表面に垂直方向に結合した構造を有する。第5図
(b)はC3P(チャネルド、サブストレート、プレー
ナー)レーザと称されるもので(IEEE、ジャーナル
、オア2クウオンタム、エレクトロニクス。
Confining Ray Two. optical guide)
The built-in structure, which is called the structure, is a waveguide laser (16th National Space Element Conference, Proceedings p153-1) 156.
(1984), an active layer 53 and cladding layers 52 and 54 forming a double heterojunction structure are formed on a semiconductor substrate 51, a current blocking layer 54 having a current confinement effect and a mode control effect due to an effective refractive index difference, and a high refractive index layer. The substrate 51 has a structure in which the index layer 55 is vertically bonded to the surface of the substrate 51. Figure 5(b) shows what is called a C3P (channeled, substrate, planar) laser (IEEE, Journal, Or2Quantum, Electronics).

1978年、QE−14巻、 p89 ) 、このレー
ザはモード制御効果を有する半導体基板51と、ヘテロ
接合構造部52.〜,54とが、基板表面に対して、第
5図(a)とは逆の順序で結合した作り付は導波型レー
ザである。また、第5図(C)はN08(ネイティブ、
オキサイド、ストライプ)レーザと称されるもので(1
00C81予稿集MB−1)、これはへテロ接合構造部
52.〜,54と、電流狭窄部58.61とが、順次結
合した利得導波型レーザである。
(1978, QE-14, p.89), this laser consists of a semiconductor substrate 51 having a mode control effect and a heterojunction structure 52. . . , 54 are coupled to the substrate surface in the reverse order to that shown in FIG. In addition, Fig. 5 (C) shows N08 (native,
It is called a laser (oxide, stripe) (1
00C81 Proceedings MB-1), this is a heterojunction structure part 52. . . , 54 and current confinement portions 58 and 61 are sequentially coupled to form a gain waveguide laser.

このように半導体基板表面に垂直方向にヘテロ接合構造
部と電流狭窄若しくはモード制御部とが縦方向結合した
レーザは、第6図(a)〜(C)に示す如く製造される
。GaAMAs系レーザを例にすると、まず第6図(a
)に示す如くN−GaAS基板51上にN−QaAff
iAS第1クラッド層52.GaAS活性層53゜P−
GaAnAS第2クラッドH54及びN−GaAS電流
阻止層55を成長形成したのち、同図(b)に示す如く
電流阻止層55をストライプ状にエツチングし、次いで
同図(C)に示す如く実効屈折率差を設けるためのP−
GaAgAS高屈折率層56.P−GaAりAs第3ク
ラッド層57及びP−GaAsコンタクト層58を成長
形成する。
A laser in which the heterojunction structure section and the current confinement or mode control section are vertically coupled in a direction perpendicular to the surface of the semiconductor substrate in this manner is manufactured as shown in FIGS. 6(a) to 6(C). Taking a GaAMAs laser as an example, first of all, Fig. 6 (a)
), N-QaAff is placed on the N-GaAS substrate 51.
iAS first cladding layer 52. GaAS active layer 53°P-
After growing the GaAnAS second cladding H54 and the N-GaAS current blocking layer 55, the current blocking layer 55 is etched into stripes as shown in FIG. P- to make a difference
GaAgAS high refractive index layer 56. A P-GaAs third cladding layer 57 and a P-GaAs contact layer 58 are grown.

m−EC0レーザに第6図に示す方法を用いる場合に、
いくつかの問題を生じる。第1に、高屈折率層56.ク
ラッド層57及びコンタクト層58の成長は、ストライ
プ部分ではGaAaAS上の成長となるため、LPE法
によっては形成不可能であり、MOCVD法やM B’
 E法を用いなければならない。第2に、気相成長法を
用いる場合にも溝部の成長は結晶欠陥を生じ易く、レー
ザの性能や信頼性の低下を引起こす。第3に、ダブルへ
テロ接合自体がエツチングプロセスや成長プロセスを経
るために、エツチング液に晒されたり、成長過程に高温
に晒され、構造やドーピングレベルの変化や結晶欠陥の
導入を生じ易い。
When using the method shown in FIG. 6 for the m-EC0 laser,
This causes some problems. First, the high refractive index layer 56. Since the cladding layer 57 and the contact layer 58 are grown on GaAaAS in the stripe portion, they cannot be formed by the LPE method, and cannot be formed by the MOCVD method or M B'
The E method must be used. Second, even when using the vapor phase growth method, the growth of the groove tends to cause crystal defects, which causes a decrease in laser performance and reliability. Third, since the double heterojunction itself undergoes an etching process and a growth process, it is exposed to etching solutions and exposed to high temperatures during the growth process, which tends to cause changes in structure and doping level and the introduction of crystal defects.

また、第5図(b)に示すC8Pレーザは、基板にチャ
ネルを形成したのちにダブルへテロ接合を形成して作ら
れるが、この場合にも問題点が生じる。例えば、溝上に
ヘテロ接合を成長させるため、成長条件によっては活性
層の品質の低下を引起こす。特に、気相成長法を用いる
場合には、成長層に溝形状が反映されるので活性層が折
れ曲り、信頼性の低下を引起こし易い。
Further, the C8P laser shown in FIG. 5(b) is manufactured by forming a channel in the substrate and then forming a double heterojunction, but problems arise in this case as well. For example, since a heterojunction is grown on the groove, the quality of the active layer may deteriorate depending on the growth conditions. In particular, when vapor phase growth is used, the groove shape is reflected in the grown layer, which tends to bend the active layer and cause a decrease in reliability.

以上のような諸問題の他にも、一般的に縦方向結合型構
造の場合は、いずれも結晶成長法によってその構造を形
成していくため、各層の材料や組成は下地材料と格子整
合がとれ、結晶成長可能なものである必要があり、また
結晶の面方位等は基板の面方位、下地の加工形状及び結
晶成長条件等により決定されると云う制約がある。これ
らの制約は、デバイスの構造や性能の可能性を大幅に制
限するものである。
In addition to the problems mentioned above, in the case of vertically bonded structures, the structure is generally formed using a crystal growth method, so the material and composition of each layer has to be lattice-matched with the underlying material. It must be able to be removed and crystal grown, and there are restrictions in that the plane orientation of the crystal is determined by the plane orientation of the substrate, the processed shape of the base, the crystal growth conditions, etc. These constraints severely limit the possibilities of device construction and performance.

一方、通信用ダイオードにおいては、ファイバとの結合
を考えた時、広がり角及びスポットサイズを小さくする
ことと、高輝度化が必要である。
On the other hand, in communication diodes, when coupling with a fiber is considered, it is necessary to reduce the spread angle and spot size, and to increase the brightness.

スポットサイズは電流の広がりによって支配されている
ので、活性層と狭窄層とが十分近いことが必要で、且つ
コンタクト層等の吸収を避けるためには、2回のエピタ
キシャル成長による狭窄層の埋込みをする必要がある。
Since the spot size is controlled by the spread of the current, it is necessary that the active layer and the constriction layer be sufficiently close to each other, and in order to avoid absorption by the contact layer, etc., the constriction layer is buried by epitaxial growth twice. There is a need.

このため、工程が複雑であり量産性に問題がある。Therefore, the process is complicated and there is a problem in mass production.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情を考慮してなされたもので、その目
的とするところは、製造が容易で高出力・高信頼性の半
導体発光装置を製造することができ、且つ結晶成長によ
る材質や面方位の制約を大幅に緩和できる半導体発光装
置の製造方法を提供することにある。
The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to be able to manufacture a semiconductor light emitting device that is easy to manufacture, has high output, and has high reliability, and that also has a material and a surface that can be improved by crystal growth. It is an object of the present invention to provide a method for manufacturing a semiconductor light emitting device that can significantly alleviate restrictions on orientation.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、ヘテロ接合構造部が形成された第1の
半導体基板と、電流狭窄或いはモード制御として作用す
る構造部が形成された第2の半導体基板とを、直接接合
させて半導体発光装置を製造することにある。
The gist of the present invention is to directly bond a first semiconductor substrate on which a heterojunction structure is formed and a second semiconductor substrate on which a structure functioning as current confinement or mode control is formed, thereby producing a semiconductor light emitting device. The purpose is to manufacture.

即ち本発明は、半導体発光装置の製造方法において、第
1の半導体基板の表面に活性層及びクラッド層を積層し
たヘテロ接合からなる第1の構造部を形成したのち、該
構造部の表面を鏡面研磨し、さらに第2の半導体基板の
表面に上記第1の構造部に対して電流狭窄効果或いはモ
ード制御効果の少なくとも一方を及ぼす第2の構造部を
形成したのち、該構造部を鏡面研磨し、次いで清浄な雰
囲気中で前記第1及び第2の構造部の鏡面研磨された表
面同志を対向させて密着し、この状態で200 [”0
1以上の温度で熱処理して前記各基板を接着するように
した方法である。
That is, the present invention provides a method for manufacturing a semiconductor light emitting device, in which a first structure section consisting of a heterojunction in which an active layer and a cladding layer are stacked is formed on the surface of a first semiconductor substrate, and then the surface of the structure section is mirror-finished. After polishing and further forming a second structure on the surface of the second semiconductor substrate that exerts at least one of a current confinement effect and a mode control effect with respect to the first structure, the structure is mirror-polished. Then, in a clean atmosphere, the mirror-polished surfaces of the first and second structural parts were brought into close contact with each other facing each other, and in this state, 200 ["0
In this method, each of the substrates is bonded by heat treatment at one or more temperatures.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ヘテロ接合からなる第1の構造部と電
流狭窄若しくはモード制御部として作用する第2の構造
部とを別々に製造できるので、第1の構造部の上に気相
成長により第2の構造を形成する従来方法に比して、第
2の構造部の構造やその形成方法が第1の構造やその材
質に影響を受けたり、逆に第2の構造部を形成するため
にヘテロ接合構造部がエツチング液に晒されたり高温に
よる構造やドーピングの変化や結晶欠陥が導入されると
言った諸問題は全て解決される。また、相互の構造を配
慮したプロセスを行う必要がないので、プロセスの手順
や条件が簡便になり、素子の歩留りの向上や量産性の向
上に有効である。さらに、相互の構造や材質及び結晶成
長法の制限を考慮する必要がない。例えば、電流狭窄効
果若しくはモード制御効果の生じる第2の構造を必ずし
も結晶成長によって製造する必要ない。このことは、従
来の半導体レーザに対する制約を大幅に緩和するもので
あり、より完全に電流狭窄効果や、さらに複雑なモード
制御効果を実現することができる。
According to the present invention, the first structure consisting of a heterojunction and the second structure functioning as a current confinement or mode control section can be manufactured separately, so that the first structure can be formed by vapor phase growth on the first structure. Compared to the conventional method of forming the second structure, the structure of the second structure and its formation method are influenced by the first structure and its material, or conversely, the second structure is formed. Problems such as exposure of the heterojunction structure to etching solutions, changes in structure and doping due to high temperatures, and introduction of crystal defects are all solved. Furthermore, since there is no need to perform processes that take mutual structures into consideration, process procedures and conditions are simplified, which is effective in improving device yield and mass productivity. Furthermore, there is no need to consider restrictions on mutual structures, materials, and crystal growth methods. For example, the second structure in which the current confinement effect or mode control effect occurs does not necessarily need to be manufactured by crystal growth. This greatly alleviates the constraints on conventional semiconductor lasers, and allows more complete current confinement effects and more complex mode control effects to be realized.

また、接着は面方位に依存しないため、他の特性は変え
ずに縦方向に面方位の異なる構造が結合したレーザと言
う新しい半導体レーザが実現される。
Furthermore, since adhesion does not depend on the surface orientation, a new semiconductor laser, which is a laser in which structures with different surface orientations are combined in the vertical direction, can be realized without changing other characteristics.

また、上記理由から、第2の半導体基板として熱伝導率
の高い半導体材料、例えばSiC,0゜3i等を用いる
ことができ、これによりヘテロ接合構造部の熱を速やか
に放熱することができる。
Furthermore, for the above reasons, a semiconductor material with high thermal conductivity, such as SiC, 0.degree.

このため、発光出力の大出力化をはかることもできる。Therefore, it is possible to increase the light emission output.

〔発明の実施例〕[Embodiments of the invention]

まず、実施例を説明する前に、本発明の基本原理につい
て説明する。
First, before explaining embodiments, the basic principle of the present invention will be explained.

従来、ガラス板の平滑な面を極めて正常に保ち、このよ
うな2枚のガラス板を直接密着させると、その間の摩擦
係数が増大して接合状態が得られることが知られている
。そして、これに逆らって上記ガラス板の面同志を滑ら
すと、その接合面のむしり取りによるクラックが発生す
ることも知られている。これに対して従来、半導体結晶
体同志の上記ガラスの如き接合法が知られていないこと
は、半導体結晶体の接合すべき面の平滑性とその清浄性
を厳密に保つことが難しかったことが最大の原因であっ
たと言える。
Conventionally, it has been known that when two such glass plates are directly brought into close contact with each other by keeping the smooth surfaces of the glass plates extremely normal, the coefficient of friction between them increases and a bonded state is obtained. It is also known that if the surfaces of the glass plates slide against each other, cracks will occur due to the peeling off of the bonded surfaces. On the other hand, the reason why there is no known bonding method for semiconductor crystals like the one described above for glass is that it is difficult to strictly maintain the smoothness and cleanliness of the surfaces of semiconductor crystals to be bonded. It can be said that this was the biggest cause.

そこで本発明者等は、次のような処理を施すことにより
、ガラス同志の接合のように半導体結晶体同志の接合も
可能なことを見出した。即ち、2つの半導体結晶体の接
合すべき面を表面粗さ5o○[人]以下に平滑化し、5
分間水洗した。
The inventors of the present invention have therefore discovered that it is possible to bond semiconductor crystal bodies together, similar to the bonding of glasses together, by performing the following treatment. That is, the surfaces of two semiconductor crystal bodies to be joined are smoothed to a surface roughness of 5 o○ [person] or less, and
Washed with water for a minute.

平滑化の方法は、鏡面研磨或いは鏡面研磨した表面上に
その平坦さを損わない方法、例えばMOCVD法或いは
MBE法によってエピタキシャル成長層を形成して行う
。得られた半導体の面は水に良く濡れ、自然酸化物の層
が形成されていることが推定された。その後、メタノー
ル置換。
The smoothing method is performed by forming an epitaxial growth layer on the mirror-polished surface by a method that does not impair the flatness of the surface, such as MOCVD or MBE. The surface of the obtained semiconductor was well wetted with water, and it was assumed that a layer of natural oxide was formed. Then replace with methanol.

フレオン乾燥を行い、このようにして得られた半導体結
晶体を、ゴミ浮遊量20[個/7FL3]の実質的にゴ
ミのないクリーンルーム中で上記接合面を相互に直接密
着させて200 [℃]以上の温度で熱処理したところ
、両者は極めて強固に接合した。この接合体の接着強度
は、熱処理温度200[℃]以上で特に著しく上昇する
Freon drying was carried out, and the semiconductor crystal thus obtained was brought into direct contact with the bonding surfaces in a substantially dust-free clean room with a dust floating amount of 20 [pieces/7FL3] at 200 [°C]. When heat treated at the above temperature, both were bonded extremely firmly. The adhesive strength of this bonded body increases particularly when the heat treatment temperature is 200[° C.] or higher.

以上のことから、研磨した清浄な半導体の面は水洗だけ
で表面が親水性となり、清浄な環境下で且つ200 [
”01以上の温度下で接合すれば強固に接着体を得るこ
とができる。
From the above, the surface of a polished clean semiconductor becomes hydrophilic simply by washing with water, and even in a clean environment and at a temperature of 200 [
A strong bond can be obtained by bonding at a temperature of 0.01 or higher.

一方、200 [℃]程度の加熱温度では、半導体構成
原子ついてはもとより、最も拡散し易い1価イオンでも
、半導体結晶中における拡散速度は通常無視できる程度
に小さいことは周知である。
On the other hand, it is well known that at a heating temperature of about 200 [° C.], the diffusion rate in the semiconductor crystal is usually negligible, not only for semiconductor constituent atoms but also for monovalent ions, which are the most easily diffused.

また、この200 [℃]付近の温度では、酸化膜の表
面に吸着された水分子が殆ど脱離し、化学吸着により形
成された一〇H基の脱水結合が起こり始めることも知ら
れている。これらのことを考え合わせれば、前記半導体
結晶体相互の結合は、金属同志の接合として知られてい
る相互拡散によるものではなく、半導体結晶体の表面酸
化膜の水和層間の相互作用や、−OH基の脱水重合によ
って半導体−〇−半導体なる強固な接合構造を成してい
るものと考えられる。
It is also known that at a temperature around 200 [° C.], most of the water molecules adsorbed on the surface of the oxide film are desorbed, and dehydration bonding of 10H groups formed by chemical adsorption begins to occur. Taking these things into consideration, the bonding between the semiconductor crystals is not due to interdiffusion, which is known as metal-to-metal bonding, but is due to interaction between hydrated layers of the surface oxide film of the semiconductor crystals, or - It is thought that a strong bonding structure of semiconductor-〇-semiconductor is formed by dehydration polymerization of OH groups.

このような事実は、半導体結晶体の表面を親水性にし、
その密着接合後に200 [℃]以上の加熱処理を施せ
ば、高い接着強度が得られることを意味している。
This fact makes the surface of the semiconductor crystal hydrophilic,
This means that high adhesive strength can be obtained if heat treatment is performed at 200[° C.] or higher after the close bonding.

以下、本発明の詳細を図示の実施例によって説明する。Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図(a)〜(d)は本発明の第1の実施例に係わる
GaAlAs系半導体レーザの製造工程を示す断面図で
ある。
FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of a GaAlAs semiconductor laser according to a first embodiment of the present invention.

まず、第1図(a)に示す如<N−GaAs基板(第1
の半導体基板)11上に厚さ1.51μTrL]のN 
 G ao−s5A Qo、4y A Sクラッド層1
2<n=1x10  cm”)、厚さ0308[、cz
mlのアンドープQao、o  AρO,IAS活性層
13及び厚さ1.5[μm]の P  Gao、55 Aρo、4sAsクラッド層14
(n=1x10 cm゛3)をMOCVD法により順次
成長形成する。ここで、上記活性層13及びクラッド層
12.14からダブルへテロ接合構造部(第1の構造部
)が形成されることになる。次いで、P−GaAffi
ASクラッド層14の表面を層面4さ500[人]以下
に鏡面研磨し、脱脂しておく。
First, as shown in FIG. 1(a),
N with a thickness of 1.51μTrL] on the semiconductor substrate) 11
G ao-s5A Qo, 4y A S cladding layer 1
2<n=1x10 cm”), thickness 0308[, cz
ml undoped Qao, o AρO, IAS active layer 13 and 1.5 [μm] thick P Gao, 55 Aρo, 4s As cladding layer 14
(n=1×10 cm3) are sequentially grown and formed by MOCVD method. Here, a double heterojunction structure (first structure) is formed from the active layer 13 and the cladding layer 12.14. Then P-GaAffi
The surface of the AS cladding layer 14 is mirror-polished to a thickness of 500 mm or less and degreased.

一方、第1図(b)に示す如く高熱伝導率の材料である
P−8t C基板(第2の半導体基板)15にメタルマ
スク(図示せず)を幅3[μTrL]。
On the other hand, as shown in FIG. 1(b), a metal mask (not shown) is placed on a P-8t C substrate (second semiconductor substrate) 15, which is a material with high thermal conductivity, with a width of 3 [μTrL].

周期300 [μm]で<110>方向にストライプ状
に付けておき、プロトン打込みを行い高抵抗層16を形
成する。そして、基板15の表面を表面粗さ500[人
]以下に鏡面研磨した後、脱脂しておく。なお、上記P
−8i C基板15及び高抵抗層16から電流狭窄部と
して作用する第2の構造部が形成されることになる。ま
た、P−8i C基板15の裏面には予めP側金属電極
17を形成しておく。
The high resistance layer 16 is formed by forming stripes in the <110> direction with a period of 300 [μm] and performing proton implantation. Then, the surface of the substrate 15 is mirror-polished to a surface roughness of 500 [mm] or less, and then degreased. In addition, the above P
A second structural portion that acts as a current confinement portion is formed from the −8i C substrate 15 and the high-resistance layer 16. Further, on the back surface of the P-8i C substrate 15, a P-side metal electrode 17 is formed in advance.

次いで、前記N−GaAS基板11の表面層であるP−
GaAffiASクラッド層14の表面及層面48 i
 C基板15の表面を清浄な水で数分間水洗する。続い
て、これをスピンナーで脱水処理する。次いで、クラス
1以下の清浄な雰囲気中で、第1図(C)に示す如く基
板11.15の鏡面研磨した表面側を対向させ、P−G
aAffiAsクラッド層14とP−8i C基板15
とを密着させる。
Next, the surface layer of the N-GaAS substrate 11 is P-
Surface and layer surface 48 i of GaAffiAS cladding layer 14
Wash the surface of the C substrate 15 with clean water for several minutes. Next, this is dehydrated using a spinner. Next, in a clean atmosphere of class 1 or below, the mirror-polished surfaces of the substrates 11 and 15 are placed facing each other as shown in FIG.
aAffiAs cladding layer 14 and P-8i C substrate 15
and bring them into close contact.

この状態で、200[°C]以上の温度で熱処理し、基
板11.15を接着する。
In this state, heat treatment is performed at a temperature of 200[° C.] or higher to bond the substrates 11.15.

次いで、第1図(CI>に示す如く前記N−Ga’As
基板11をPAエッチャントでN−GaAnAsクラッ
ド層12が露出するまでエツチングし、このエツチング
面を鏡面研磨した後、脱水・水洗を施す。そして、更に
もう1枚のN−8iC基板〈第3の半導体基板)18も
同様に前処理して、これをN−GaAgASクラッド層
12の研磨した表面と密着させ、先の手順と同様にして
接着する。なお、N−8iC基板18の裏面には予めN
側電極19としてAuGe/Auを始めに付けておく。
Next, as shown in FIG. 1 (CI), the N-Ga'As
The substrate 11 is etched with a PA etchant until the N-GaAnAs cladding layer 12 is exposed, and the etched surface is mirror polished and then dehydrated and washed with water. Then, another N-8iC substrate (third semiconductor substrate) 18 is pretreated in the same way, and it is brought into close contact with the polished surface of the N-GaAgAS cladding layer 12, and the same procedure as before is carried out. Glue. Note that the back surface of the N-8iC substrate 18 is coated with N in advance.
AuGe/Au is first applied as the side electrode 19.

同様に、前記P−8i基板15の裏面には、P側電極1
7として T r PtAuを始めに付けておく。
Similarly, a P-side electrode 1 is provided on the back surface of the P-8i substrate 15.
7, T r PtAu is attached first.

次いで、上記第1図(d)に示す試料を前記ストライプ
と垂直にヘキ開面を出すよう(ヘキ開し、ストライプ方
向の長さ、即ち共振器長は250[μm]とした。さら
に、これを各ストライブ毎に切り分けて、第2図に示す
如く1つの半導体レーザチップを作製した。なお、この
チップはN側電極19を下にして、Cuベース上にAU
Snを融着金属としてマウントされる。
Next, the sample shown in FIG. 1(d) above was opened so that a cleavage plane was exposed perpendicular to the stripe, and the length in the stripe direction, that is, the resonator length was 250 [μm]. was cut into strips for each strip, and one semiconductor laser chip was fabricated as shown in Fig. 2.This chip was made with the AU on the Cu base with the N-side electrode 19 facing down.
It is mounted using Sn as a fusion metal.

かくして製造された半導体レーザは、従来のNOSレー
ザと比較すると、NOSレーザが発撮しきい圃が50[
mA]、CWでの光出力が120 [mW] <らいで
飽和してくるのに対し、発振しきい値が46rmA]、
CWでの光出力の飽和は170 [mW]以上と大幅な
改善が見られた。さらに、放熱特性の向上のために50
[℃]。
Compared to conventional NOS lasers, the semiconductor laser thus manufactured has a firing threshold of 50 [
mA], CW optical output saturates at 120 [mW] < lasing threshold is 46 rmA],
The optical output saturation under CW was 170 [mW] or more, which was a significant improvement. In addition, 50%
[℃].

5 [mW]の定出力動作試験においても、動作電流が
平均10[mA]はどNOSレーザより低く、劣化も殆
ど見られていない。
Even in a constant output operation test of 5 [mW], the average operating current was 10 [mA], lower than any other NOS laser, and almost no deterioration was observed.

また、電流狭窄構造部をヘテロ接合構造部上にエピタキ
シャル成長により形成する従来方法に比して、ヘテロ接
合構造部がエツチング液に晒されたり、高温による構造
やドーピングの変化や結晶欠陥が導入されると言った等
の不都合もない。さらに、相互の構造を配慮したプロセ
スを行う必要もないので、プロセスの手順や条件が簡便
となる。
In addition, compared to the conventional method in which a current confinement structure is formed by epitaxial growth on a heterojunction structure, the heterojunction structure is exposed to an etching solution, and the structure and doping change due to high temperature and crystal defects are introduced. There are no such inconveniences. Furthermore, since there is no need to perform a process that takes mutual structures into consideration, the process procedure and conditions become simpler.

このため、製造歩留り及び最産性の向上をはかり得、さ
らに信頼性の向上をはかり得る。
Therefore, manufacturing yield and productivity can be improved, and reliability can also be improved.

第3図は第2の実施例に係わるバラス型発光ダイオード
(LED)の概略構造を示す断面図である。製造工程は
、基本的には第1図(a)〜(d)と同様である。バラ
ス型LEDの場合、電流狭窄層を形成する際のマスクの
形状がストライブではなく、直径50[μm1の円形で
ある。但し、プロトン打込み後の断面は、第1図(b)
と同様となる。ヘテロ接合部と接着され、第1図(C)
のような断面で表わされる形となった後、N−GaAS
基板11にフォトレジストを塗り、電流が注入されて発
光する部分の基板の上を直径150[μm]の部分を残
してフォトレジストを取り除き、N−電慟金属(AuG
e/Au)を蒸着し、レジストを剥離してリフトオフを
行う。次いで、この金属電極をマスクとしてPAエッチ
ャントでN−GaAλASクラッド層12に至る深さま
でエツチングする。その後、ダイシングで各チップに切
出すことにより、第3図に示す如きLEDが完成するこ
とになる。
FIG. 3 is a sectional view showing a schematic structure of a ballast type light emitting diode (LED) according to the second embodiment. The manufacturing process is basically the same as that shown in FIGS. 1(a) to (d). In the case of a rosette type LED, the shape of the mask when forming the current confinement layer is not a stripe but a circle with a diameter of 50 [μm1]. However, the cross section after proton implantation is shown in Figure 1(b).
It is the same as. Figure 1 (C)
After forming a cross section like this, N-GaAS
A photoresist is applied to the substrate 11, and the photoresist is removed leaving a 150 [μm] diameter portion on the substrate where a current is injected and emits light.
e/Au) is deposited, the resist is peeled off, and lift-off is performed. Next, using this metal electrode as a mask, etching is performed using a PA etchant to a depth that reaches the N-GaAλAS cladding layer 12. Thereafter, by cutting each chip by dicing, an LED as shown in FIG. 3 is completed.

なお、LEDの場合、ダブルへテロ接合構造のパラメー
タ(特に厚さ)が前記半導体レーザとは異なっている。
Note that in the case of an LED, the parameters (particularly the thickness) of the double heterojunction structure are different from those of the semiconductor laser.

即ち、クラッド層12.14の厚さは2.5 [μm]
 、活性層13の厚さは1.○[μm]とした。
That is, the thickness of the cladding layer 12.14 is 2.5 [μm]
, the thickness of the active layer 13 is 1. ○ [μm].

第4図(a)〜(f)は第3の実施例に係わるGaAf
fiAS系半導体レーザの製造工程を示す断面図である
。なお、この図では1チツプに相当する部分のみを示し
ている。
FIGS. 4(a) to 4(f) show GaAf according to the third embodiment.
FIG. 3 is a cross-sectional view showing the manufacturing process of a fiAS-based semiconductor laser. Note that this figure only shows a portion corresponding to one chip.

まず、第4図(a)に示す如く面方位<100>のN−
GaAS基板41(Siドープ 1X10  cm”)上に厚さ1.5[μm]のN−G
 a n、as A Qo、ss A Sクラッド層4
2(Seドープ1 X 1017cm” ) 、厚さ0
.08 [μ711L]のアンドープG ao、ot 
A Qo、os A S活性層43及び厚さ1.5[μ
771]のP −G ao、、、 A ffi、、、、
 A Sクラッド層44(Znドープ7 X 101!
1cm” )を順次成長形成する。ここで、上記活性層
43及びクラッド層42.44からダブルへテロ接合構
造(第1の構造部)が形成されることになる。
First, as shown in Fig. 4(a), N-
N-G with a thickness of 1.5 μm on a GaAS substrate 41 (Si doped 1×10 cm”)
a n, as A Qo, ss A S cladding layer 4
2 (Se doped 1 x 1017cm”), thickness 0
.. 08 [μ711L] undoped G ao,ot
A Qo, os A S active layer 43 and thickness 1.5 [μ
771] P-Gao,,, Affi,,,,
A S cladding layer 44 (Zn doped 7 x 101!
1 cm") are sequentially grown. Here, a double heterojunction structure (first structure portion) is formed from the active layer 43 and the cladding layers 42 and 44.

一方、第4図(b)に示す如く面方位(100)のP−
GaAs基板45上に厚さ0.05 rμm]のP−G
ao、s  Ano、、As高屈折率R46を成長形成
する。次いで、第4図(C)に示す如く高屈折率層46
上にストライプ状にエツチングマスク(図示せず)を形
成し、これにより幅3[μTrt]程度、深さ1[μT
rL]のメサストライプを形成する。続いて、第4図(
d)に示す如くエツチングによって除去した部分にN−
GaAs電流素子層47(Seドープ5X10  cI
l−’)を成長形成する。ここで、高屈折率層46及び
電流素子層47から、電流狭窄及びモード制御部として
作用する第2の構造部が形成されることになる。
On the other hand, as shown in Fig. 4(b), P-
PG with a thickness of 0.05 rμm on the GaAs substrate 45
ao, s Ano, , As high refractive index R46 is grown. Next, as shown in FIG. 4(C), a high refractive index layer 46 is formed.
An etching mask (not shown) is formed in the form of a stripe on the etching mask.
rL] to form a mesa stripe. Next, Figure 4 (
As shown in d), N- is applied to the part removed by etching.
GaAs current element layer 47 (Se doped 5X10 cI
l-') is grown and formed. Here, the high refractive index layer 46 and the current element layer 47 form a second structure that acts as a current confinement and mode control section.

次いで、前記第4図(a)に示す状態の試料及び同図(
d)に示す状態の試料の各表面を表面粗さ500[大]
以下に鏡面研磨する。このとき、P−GaAs基板45
の研磨に際し、研磨表面にはP−GaAgAS高屈折率
層46及びN−GaAs電流素子層47が露出している
ものとする。
Next, the sample in the state shown in FIG. 4(a) and the same figure (
Each surface of the sample in the state shown in d) has a surface roughness of 500 [large]
Mirror polish the following. At this time, the P-GaAs substrate 45
During polishing, it is assumed that the P-GaAgAS high refractive index layer 46 and the N-GaAs current element layer 47 are exposed on the polished surface.

次いで、上記各研磨面を清浄な水で水洗し、至温でスピ
ンナー処理のような脱水処理を施す。これらの処理を施
した各鏡面研磨面を、例えば1クラス以下の清浄な大気
雰囲気中に設置し、その鏡面研磨面に異物が実質的に介
在しない状態で、第4図(e)に示す如く相互に密着し
て接合する。
Next, each polished surface is washed with clean water and subjected to dehydration treatment such as spinner treatment at the lowest temperature. Each mirror-polished surface subjected to these treatments is placed in a clean atmosphere of, for example, 1 class or less, and the mirror-polished surface is exposed to substantially no foreign matter as shown in FIG. 4(e). be closely attached to each other.

ぞの後、上記接合したウェハを200 [℃]以上S加
熱処理することにより、接合強度を増大する。
After that, the bonded wafers are heat-treated at 200 [° C.] or higher to increase the bonding strength.

次イテ、P−GaAs基板45及び N−GaAs基板41をそれぞれ数[μm] 、数10
[μm]の厚さまで研磨し、その両面に第4図(f)に
示す如くオーミック電極48.49を形成する。
Next, the P-GaAs substrate 45 and the N-GaAs substrate 41 are separated by a number [μm] and a number 10, respectively.
It is polished to a thickness of [μm], and ohmic electrodes 48 and 49 are formed on both surfaces as shown in FIG. 4(f).

かくして製造された半導体レーザは、ダブルへテロ接合
構造からなる第1の構造部と、電流狭窄及びモード制御
部として作用する第2の構造部とが、別々に製造される
ことになる。従って、先に説明した第1の実施例と同様
な効果が得られる。
In the semiconductor laser manufactured in this way, the first structure section consisting of a double heterojunction structure and the second structure section functioning as a current confinement and mode control section are manufactured separately. Therefore, effects similar to those of the first embodiment described above can be obtained.

また、前記第5図(a)の構造では高屈折率層56がP
型クラッド層54及び電流素子層55の表面全体を覆っ
ており、ストライブ溝両側部分で高屈折率層56がぜり
あがっているので、この部分の実効屈折率差が溝中央よ
り大きくなり、モードが偏ってしまう問題があるが、本
実施例の構造では上記の問題は生じない。
Further, in the structure shown in FIG. 5(a), the high refractive index layer 56 is P
Since the high refractive index layer 56 covers the entire surface of the mold cladding layer 54 and the current element layer 55 and rises at both side portions of the stripe groove, the effective refractive index difference in this portion is larger than that in the center of the groove. Although there is a problem that the mode is biased, the above problem does not occur in the structure of this embodiment.

なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記第1の実施例において、成長の初め
のGaAs基板11をN型基板としておき、第1図(C
)の状態でN−GaAs基板11を全てはエツチングせ
ずに残しておき、この基板11の下面にN (1!l電
極19として、A、uGe/Auを付けてオーミックコ
ンタクトを取るようにしてもよい。また、この実施例に
おいて、PNを逆とした場合には、前記基板15がN−
8i C基板となる。この場合、ストライブ状の3i3
N4等のマスクを付けた後Zn拡散を行い、前記高抵抗
層16をP型とすることでNPNの形で電流狭窄を行う
ことができる。さらに、ヒートシンクの材料はSiCに
限るものではなく、C1Si、GaP、InP、GaA
s等を用いてもよい。
Note that the present invention is not limited to the embodiments described above. For example, in the first embodiment, the GaAs substrate 11 at the beginning of growth is an N-type substrate, and as shown in FIG.
), the N-GaAs substrate 11 is left without etching, and an ohmic contact is made by attaching A, uGe/Au as an electrode 19 to the bottom surface of this substrate 11. In addition, in this embodiment, when the PN is reversed, the substrate 15 is N-
This will be an 8i C board. In this case, striped 3i3
After applying a mask such as N4, Zn is diffused and the high resistance layer 16 is made of P type, so that current confinement can be performed in the form of NPN. Furthermore, the material of the heat sink is not limited to SiC, but also C1Si, GaP, InP, GaA
s etc. may also be used.

また、前記電流素子層及び高屈折率層は、それぞれ電流
素子効果のある材質及び活性層に対して実効屈折率が高
く電流が注入できる材質等であればよく、GaASヤG
aAQAsである必要はない。例えば、電流素子層には
アンドープZn5eを用いてもよいし、またGaAs系
の代りにGaASP基根上に成長したGa1nPを用い
てもよい。Ga1nPとGaAりASとは一組成を除い
て格子が整合がとれないが、本発明の接着技術を用いれ
ば問題ない。また、結晶成長法はMOCVD法に限るも
のではなく、MBE法やLPE法を用いることも可能で
ある。ざらに、第1及び第2の構造部の構造、材質及び
導電型等は、仕様に応じて適宜変更可能である。その他
、本発明の要旨を逸脱しない範囲で、種々変形して実施
することができる。
Further, the current element layer and the high refractive index layer may be made of a material that has a current element effect and a material that has a high effective refractive index and can inject current into the active layer, such as GaAS or G.
It does not have to be aAQAs. For example, undoped Zn5e may be used for the current element layer, or Ga1nP grown on a GaASP base may be used instead of GaAs. Although Ga1nP and GaAl AS cannot have lattice matching except for one composition, there is no problem if the bonding technique of the present invention is used. Further, the crystal growth method is not limited to the MOCVD method, and it is also possible to use the MBE method or the LPE method. In general, the structure, material, conductivity type, etc. of the first and second structural parts can be changed as appropriate according to specifications. In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は本発明の第1の実施例に係わる
半導体レーザの製造工程を示す断面図、第2図は上記工
程により製造された半導体レーザの概略構造を示す断面
図、第3図は第2の実施例に係わるバラス型LEDの概
略構造を示す断面図、第4図(a)〜(f)は第3の実
施例に係わる半導体レーザの製造工程を示す断面図、第
5図(a)〜(C)はそれぞれ従来の半導体レーザの概
略構造を示す断面図、第6図(a)〜(C)は従来の半
導体レーザの製造工程を示す断面図である。 11 、41−N−GaAS基板(第1の半導体基板)
 、12.42−N−GaA/lAsクラッド層、13
.43・・・アンドープGaAj2AS活性層、14.
44−P−GaA QAsクラッド層、15・・・P−
8iC基板(第2の半導体基板)、16・・・高抵抗層
、17.48・・・P側電極、18・・・N−8iC基
板(第3の半導体基板)、19.49−N側電極、45
−P −G a A s基板(第2の半導体基板) 、
46−P−GaAffiAs高屈折率層、47・・・N
−GaAS電流素子層。 出願人代理人 弁理士 鈴江武彦 第1図 第2図 第3図 第4図 第4図 第5図
1(a) to (d) are cross-sectional views showing the manufacturing process of a semiconductor laser according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the schematic structure of the semiconductor laser manufactured by the above steps. , FIG. 3 is a cross-sectional view showing a schematic structure of a ballast type LED according to the second embodiment, and FIGS. 4(a) to (f) are cross-sectional views showing the manufacturing process of a semiconductor laser according to the third example. , FIGS. 5(a) to 5(C) are sectional views showing the schematic structure of a conventional semiconductor laser, and FIGS. 6(a) to 6(C) are sectional views showing the manufacturing process of the conventional semiconductor laser. 11, 41-N-GaAS substrate (first semiconductor substrate)
, 12.42-N-GaA/lAs cladding layer, 13
.. 43...Undoped GaAj2AS active layer, 14.
44-P-GaA QAs cladding layer, 15...P-
8iC substrate (second semiconductor substrate), 16... High resistance layer, 17.48... P side electrode, 18... N-8iC substrate (third semiconductor substrate), 19.49-N side electrode, 45
-P-GaAs substrate (second semiconductor substrate),
46-P-GaAffiAs high refractive index layer, 47...N
-GaAS current element layer. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 4 Figure 5

Claims (4)

【特許請求の範囲】[Claims] (1)第1の半導体基板の表面に活性層及びクラッド層
を積層したヘテロ接合からなる第1の構造部を形成した
のち、該構造部の表面を鏡面研磨する工程と、第2の半
導体基板の表面に上記第1の構造部に対して電流狭窄効
果或いはモード制御効果の少なくとも一方を及ぼす第2
の構造部を形成したのち、該構造部を鏡面研磨する工程
と、次いで清浄な雰囲気中で前記第1及び第2の構造部
の鏡面研磨された表面同志を対向させて密着し、この状
態で200[℃]以上の温度で熱処理して前記各基板を
接着する工程とを含むことを特徴とする半導体発光装置
の製造方法。
(1) After forming a first structural part consisting of a heterojunction in which an active layer and a cladding layer are laminated on the surface of a first semiconductor substrate, mirror polishing the surface of the structural part; A second structure that exerts at least one of a current confinement effect and a mode control effect on the first structure on the surface of the structure.
After forming the structural part, the structural part is mirror-polished, and then the mirror-polished surfaces of the first and second structural parts are brought into close contact with each other facing each other in a clean atmosphere, and in this state, A method for manufacturing a semiconductor light emitting device, comprising the step of bonding each of the substrates by heat treatment at a temperature of 200[° C.] or higher.
(2)前記鏡面研磨する工程は、表面粗さ500[Å]
以下に研磨することである特許請求の範囲第1項記載の
半導体発光装置の製造方法。
(2) The mirror polishing step has a surface roughness of 500 [Å]
2. A method for manufacturing a semiconductor light emitting device according to claim 1, which comprises polishing.
(3)前記清浄な雰囲気とは、ゴミ浮遊量が20[個/
m^3]以下の雰囲気であることを特徴とする特許請求
の範囲第1項記載の半導体発光装置の製造方法。
(3) The above-mentioned clean atmosphere means that the amount of floating debris is 20 [pieces/
The method for manufacturing a semiconductor light emitting device according to claim 1, characterized in that the atmosphere is less than or equal to m^3].
(4)前記第1の半導体基板の裏面側を前記第1の構造
部に達するまで或いは該構造部の近傍までエッチングし
、このエッチング面に上記第1の半導体基板と同一導電
型を有し、且つ上記第1の半導体基板より熱伝導性の良
好な第3の半導体基板を接着することを特徴とする特許
請求の範囲第1項記載の半導体発光装置の製造方法。
(4) etching the back side of the first semiconductor substrate until it reaches the first structural portion or near the structural portion, and having this etched surface have the same conductivity type as the first semiconductor substrate; 2. The method of manufacturing a semiconductor light emitting device according to claim 1, further comprising bonding a third semiconductor substrate having better thermal conductivity than the first semiconductor substrate.
JP60022927A 1985-02-08 1985-02-08 Manufacture of semiconductor light emitting device Granted JPS61183986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60022927A JPS61183986A (en) 1985-02-08 1985-02-08 Manufacture of semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60022927A JPS61183986A (en) 1985-02-08 1985-02-08 Manufacture of semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPS61183986A true JPS61183986A (en) 1986-08-16
JPH0574956B2 JPH0574956B2 (en) 1993-10-19

Family

ID=12096261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60022927A Granted JPS61183986A (en) 1985-02-08 1985-02-08 Manufacture of semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS61183986A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137677A (en) * 1987-11-25 1989-05-30 Ricoh Co Ltd Edge-face type light emitting diode array element
US5608750A (en) * 1993-07-29 1997-03-04 Hitachi, Ltd. Semiconductor laser device and a method for the manufacture thereof
WO1998000895A1 (en) * 1996-06-28 1998-01-08 Honeywell Inc. Current confinement for a vertical cavity surface emitting laser
WO1998048492A1 (en) * 1997-04-23 1998-10-29 Honeywell Inc. Electronic devices formed from pre-patterned structures that are bonded
JP2000277804A (en) * 1995-06-15 2000-10-06 Nichia Chem Ind Ltd Nitride semiconductor device and manufacture thereof, and light emitting element
US7105857B2 (en) 2002-07-08 2006-09-12 Nichia Corporation Nitride semiconductor device comprising bonded substrate and fabrication method of the same
JP2006319374A (en) * 1993-03-19 2006-11-24 Philips Lumileds Lightng Co Llc Reflecting boundary plane between led layer, and wafer jointed to it
JP2007189242A (en) * 2000-08-08 2007-07-26 Osram Opto Semiconductors Gmbh Opto-electronics semiconductor chip and its manufacturing method
US7301175B2 (en) 2001-10-12 2007-11-27 Nichia Corporation Light emitting apparatus and method of manufacturing the same
US7547921B2 (en) 2000-08-08 2009-06-16 Osram Opto Semiconductors Gmbh Semiconductor chip for optoelectronics
JP2010087360A (en) * 2008-10-01 2010-04-15 Kyoto Institute Of Technology Production process of semiconductor substrate, and semiconductor substrate
JP2011003934A (en) * 1999-06-09 2011-01-06 Toshiba Corp Laminate, and light-emitting element
JP2011507262A (en) * 2007-12-14 2011-03-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Light emitting device having a bonded interface
JPWO2013038964A1 (en) * 2011-09-13 2015-03-26 電気化学工業株式会社 Clad material for LED light-emitting element holding substrate and manufacturing method thereof

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137677A (en) * 1987-11-25 1989-05-30 Ricoh Co Ltd Edge-face type light emitting diode array element
JP2006319374A (en) * 1993-03-19 2006-11-24 Philips Lumileds Lightng Co Llc Reflecting boundary plane between led layer, and wafer jointed to it
US5608750A (en) * 1993-07-29 1997-03-04 Hitachi, Ltd. Semiconductor laser device and a method for the manufacture thereof
JP2000277804A (en) * 1995-06-15 2000-10-06 Nichia Chem Ind Ltd Nitride semiconductor device and manufacture thereof, and light emitting element
WO1998000895A1 (en) * 1996-06-28 1998-01-08 Honeywell Inc. Current confinement for a vertical cavity surface emitting laser
EP1176680A1 (en) * 1996-06-28 2002-01-30 Honeywell Inc. Current confinement for vertical cavity surface emitting laser
WO1998048492A1 (en) * 1997-04-23 1998-10-29 Honeywell Inc. Electronic devices formed from pre-patterned structures that are bonded
JP2011003934A (en) * 1999-06-09 2011-01-06 Toshiba Corp Laminate, and light-emitting element
JP2007189242A (en) * 2000-08-08 2007-07-26 Osram Opto Semiconductors Gmbh Opto-electronics semiconductor chip and its manufacturing method
US7547921B2 (en) 2000-08-08 2009-06-16 Osram Opto Semiconductors Gmbh Semiconductor chip for optoelectronics
US7301175B2 (en) 2001-10-12 2007-11-27 Nichia Corporation Light emitting apparatus and method of manufacturing the same
US7390684B2 (en) 2001-10-12 2008-06-24 Nichia Corporation Light emitting apparatus and method of manufacturing the same
US7378334B2 (en) 2002-07-08 2008-05-27 Nichia Corporation Nitride semiconductor device comprising bonded substrate and fabrication method of the same
US7105857B2 (en) 2002-07-08 2006-09-12 Nichia Corporation Nitride semiconductor device comprising bonded substrate and fabrication method of the same
US8030665B2 (en) 2002-07-08 2011-10-04 Nichia Corporation Nitride semiconductor device comprising bonded substrate and fabrication method of the same
JP2011507262A (en) * 2007-12-14 2011-03-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Light emitting device having a bonded interface
US9905730B2 (en) 2007-12-14 2018-02-27 Lumileds Llc Light emitting device with bonded interface
JP2010087360A (en) * 2008-10-01 2010-04-15 Kyoto Institute Of Technology Production process of semiconductor substrate, and semiconductor substrate
JPWO2013038964A1 (en) * 2011-09-13 2015-03-26 電気化学工業株式会社 Clad material for LED light-emitting element holding substrate and manufacturing method thereof

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