WO1998048492A1

WO1998048492A1 - Electronic devices formed from pre-patterned structures that are bonded

Info

Publication number: WO1998048492A1
Application number: PCT/US1998/007351
Authority: WO
Inventors: Robert A. Morgan; Richard A. Skogman
Original assignee: Honeywell Inc.
Priority date: 1997-04-23
Filing date: 1998-04-15
Publication date: 1998-10-29

Abstract

An electronic device that is formed by bonding two or more structures together, wherein at least one of the structures includes a pre-patterned layer. By providing a patterned layer in one or more of the structures before the bonding process, the feature size of the pattern can be tightly controlled using standard processing techniques. This may reduce the physical size, and increase the performance, functionality, and reliability of many electronic devices.

Description

ELECTRONIC DEVICES FORMED FROM PRE-PATTERNED STRUCTURES THAT ARE BONDED BACKGROUND OF THE INVENTION

This invention relates to the field of electronic devices, and more particularly relates to electronic devices formed from pre-patterned structures that are bonded together.

Most electronic devices are formed on a single substrate. By using a single substrate, a number of electronic devices can be completely formed on a single wafer. This technique is suitable for many electronic devices, particularly those formed from a number of similar materials. Similar materials are materials that are similar in kind or nature. This includes homogeneous or heterogeneous lattice-matched semiconductor crystals or amorphous semiconductors and polymers. Similar materials can typically be epitaxially formed, such as for homogeneous or heterogeneous lattice-matched semiconductor materials, or formed using other conventional processing techniques. In some instances, it may be desirable to incorporate dissimilar materials into an electronic device. Dissimilar materials typically cannot be easily formed on the same substrate. For semiconductor materials, this is often because the crystalline structure of the materials are lattice mismatched, which limits the ability of the materials to be grown or otherwise epitaxially formed using conventional processing techniques. Likewise, selected polymers may be considered dissimilar from glass and/or semiconductor materials.

One technique for incorporating dissimilar materials into a device is to form a part of a device on a first substrate and another part of the device on another substrate. The two parts of the device can then be bonded together to form a completed device. Fusion bonding is a typical bonding process, and requires heating and applying pressure to the elements, as is known in the art (see for example, Z. L. Liau and D. E. Mull, "Wafer fusion: a novel technique for optoelectronic device fabrication and monolithic integration," Appl. Phys. Lett. Vol. 56, pp. 737-739 (1990); Stefan Bengtsson, "Semiconductor wafer bonding; a review of interfacial properties and applications," J. of electronic Materials, Vol. 21, pp. 841-862 (1992); and Y. H. Lo, R. Bhat, D. M. Hwang,

C. Chua and C.-H. Lin, "Semiconductor laser on Si substrates using the technology of bonding by atomic rearrangement," Appl. Phys. Lett., Vol. 62, pp. 1038-1040 (1993)). Fusion bonding typically does not melt the materials to form a bond, but rather produces an atomic or electronic rearrangement of the material interface. This atomic rearrangement often exploits the diffusion of atoms from one material to the other. Electronic bonding may utilize covalent or vander Waals forces. Fusion bonding may thus maintain the crystalline structure of both materials, which is useful in semiconductor applications.

One illustrative electronic device that uses fusion bonding is described in Margalit et al., entitled "Lateral Oxidized Long Wavelength CW Vertical-Cavity Lasers", Appl. Phsy. Lett., Vol. 69, pp. 471-473 (1996). In Margalit et al., a Vertical Cavity Surface Emitting Laser (NCSEL) is disclosed that includes a GaAs/AlAs n-type

Distributed Bragg Reflector (DBR) mirror, an InGaAsP quantum-well region, and an AlGaAs/GaAs p-type DBR mirror. It is known that this InGaAsP material is lattice mismatched or dissimilar with the GaAs/AlAs material used in the n-type and p-type DBR mirrors. Margalit et al. discloses forming the InGaAsP quantum-well region separately, and fusion bonding the InGaAsP quantum- well active region with the n-type and p-type DBR mirrors.

Unlike Margalit et al., the active region of conventional GaAs VCSEL devices includes a GaAs bulk or quantum- well material. The GaAs quantum- well active region is similar and lattice-matched relative the GaAs/AlAs DBR mirror regions, and thus can typically be epitaxially formed with the mirror regions. VCSELs that use GaAs quantum-wells may emit a wavelength near 0.85um.

For communication applications, it is often desirable to produce a longer wavelength of, for example, 1.3 or 1.55 μm. One method of producing this longer wavelength is to provide an InGaAsP quantum-well active region as described in Margalit et al.

Regardless of the type of active region provided, it is often desirable to provide a gain-guiding region within the VCSEL. The gain guiding region directs the flow of operating current through a defined portion of the active region. This may define the gain area, and thus increase the efficiency of the VCSEL. The gain guiding region can also have optical guiding properties for guiding the laser light resulting in increased efficiency and providing mode control. The operating current of the VCSEL is often proportional to the size of the gain guided region. Thus, it can be beneficial to have a smaller gain guided region. In addition, the size of the gain guided region can determine, at least in part, the minimum physical size and the operating modes of the VCSEL.

For conventional all-epitaxial grown VCSEL devices, the gain guiding region can be formed by implanting high energy ions through the top mirror surrounding the active region. The implantation step is controlled so that a circular core of the VCSEL is not implanted. The un-implanted core defines the gain guided region. Because the thickness of a typical top mirror is about 3 μm, straggle and other processing factors can limit the minimum lateral size of the gain guided region, often to not less than about 10 μm. This translates into a typical operating current in the milliamp range.

The Margalit et al. reference provides a method for forming a gain-guiding region with a reduced annular inner diameter. As indicated above, Margalit et al. suggest fusion bonding an active region between an n-type DBR mirror and a p-type DBR mirror. After the fusion bonding process is completed, Margalit et al. teach to selectively etch the top mirror down to the active region so that a pillar structure is formed. This is performed using a chlorine reactive ion etch with a SiO₂ mask. The diameter of the circular pillar structure ranges from 10 to 30 μm.

The bottom layer of the top mirror is formed from a high aluminum content material such as AlAs. Margalit et al. suggest heating the resulting device in water vapor utilizing a Nitrogen flow, so that this AlAs layer oxidizes laterally from the edges of the pillar structure toward the center of the device. By timing the oxidation reaction, Margalit et al. suggest that a desired aperture size can be obtained.

It has been recognized that the VCSEL disclosed by Margalit et al. may suffer from a number of limitations. First, the completed VCSEL is non-planar. This may limit the ease of batch fabrication, integrability, manufacturability, and possibly the reliability of the device. Second, it is believed that the aperture size provided by the lateral oxidation process may be difficult to control, particularly since it depends on a timed chemical reaction.

SUMMARY OF THE INVENTION

The present invention overcomes many of the disadvantages of the prior art by providing an electronic device that is formed by bonding two or more structures, where at least one of the structures has a pre-patterned layer therein. By providing a patterned layer in one or more of the structures before the bonding process, the feature size of the pattern can be tightly controlled using standard fabrication techniques. Predominantly surface processing may be used. This may increase the performance, and reduce the physical size of many electronic devices while maintaining planarity. For a VCSEL device, this may translate into a reduced diameter gain guided region and lower operating currents. It may also provide for waveguiding to reduce diffraction losses with smaller VCSEL devices, or for anti-guiding which may suppress multi-mode emission. In addition to the above, and because two or more separate structures are bonded together to form the final device, dissimilar materials can be incorporated into a device. The incorporation of dissimilar materials may add device and processing flexibility, and increase device functionality.

Finally, the present invention may provide a relatively planar device. This may increase the ease of batch fabrication and integration, and may increase the reliability of the device.

While it is recognized that the advantages of the present invention may be realized in many types of electronic devices, the application of the present invention to a VCSEL device, as described herein, is believed to be illustrative. Other applications of the present invention include, but are not limited to, improved Resonant Cavity Photo

Detectors (RCPD), LEDs, photodetectors, GaAs/Silicon integration, optical-electronics integration, etc.

Specifically with respect to VCSEL devices, it is envisioned that the present invention may improve performance and expand VCSEL utilization into advanced data/tele-communication applications. Planar state-of-the-art pre-patterned similar and dissimilar parts that are bonded together may improve the capability to produce novel, integrated optoelectronics devices. Some illustrative applications for VCSELs constructed in accordance with the present invention include ultra-efficient, ultra-dense optical-electronic processors. These include both free-space and wave-guided optically interconnected smart pixel multi-chip modules for use within and between processing boards. The capability to produce low threshold arrays using pre-patterned fusion bonding with enhanced performance may enable two-dimensional VCSEL-array based flat panel and projection displays. Three-dimensional volumetric displays based on multiple element high efficiency VCSEL arrays are also envisioned. Finally, and because of the ability to synthesize multiple-wavelength material, applications involving wavelength division multiplexing and/or multi-color displays are envisioned.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects of the present invention and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof and wherein:

Figure 1 is a schematic diagram of a planar, current-guided, GaAs/AlGaAs top surface emitting vertical cavity laser in accordance with the prior art;

Figure 2 is a schematic diagram of a first illustrative VCSEL in accordance with present invention having an etched pattern in the bottom mirror;

Figure 3 is a schematic diagram of a second illustrative VCSEL of the present invention having an implanted pattern near the active region;

Figure 4 is a schematic diagram of a third illustrative VCSEL of the present invention having a patterned oxide layer surrounding the active region; Figure 5 is a schematic diagram of a fourth illustrative VCSEL of the present invention having an etched pattern in the first part of the top mirror of the bottom structure;

Figure 6 is a table showing a detailed construction for the bottom structure of Figure 5; Figure 7 is a table showing a detailed construction for the top structure of

Figure 5;

Figure 8 is a schematic diagram of a fifth illustrative VCSEL of the present invention formed from dissimilar material and having an etched pattern formed near the active region; and Figure 9 is a schematic diagram of a sixth illustrative VCSEL of the present invention formed from dissimilar materials and having an implanted pattern near the active region. DET AILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a schematic illustration of a planar, current-guided, GaAs/AlGaAs top surface emitting vertical cavity laser 10 in accordance with the prior art. Formed on an n-doped gallium arsenide (GaAs) substrate 14 is an n-contact 12. Substrate 14 is doped with impurities of a first type (i.e., n type). An n-type mirror stack 16 is formed on substrate 14. Formed on stack 16 is a spacer 18. Spacer 18 has a bottom confinement layer 20 and a top confinement layer 24 surrounding active region 22. A p-type mirror stack 26 is formed on top confinement layer 24. A p-metal layer 28 is formed on stack 26. The emission region may have a passivation layer 30.

The gain guiding isolation region 29 restricts the area of the current flow 27 through the active region. Region 29 may be formed by deep H+ ion implantation. The diameter "g" may be set by the desired resistance of the p-type mirror stack 26, particularly through the isolation region 29. Further, the diameter "g" may be set to provide the desired active area, and thus the gain aperture of the VCSEL 10. Thus, isolation region 29 performs the gain guiding function. The diameter "g" is typically limited by fabrication limitations, such as straggle during the implantation step, as described above.

The diameter "w" of the exit aperture 34 may be smaller than the diameter "g" of the isolation region 29. This may reduce the contact resistance and improve the fabrication tolerance. Because most of the energy for higher order modes is concentrated away from the center of the lasing cavity, this may also help reduce the number of modes the laser produces at a given drive current.

Spacer 18 may contain a bulk or quantum- well active region disposed between mirror stacks 16 and 26. Quantum-well active region 22 may have alternating layers of aluminum gallium arsenide (AlGaAs) barrier layers and GaAs quantum-well layers. Stacks 16 and 26 are distributed Bragg reflector (DBR) stacks, and may include periodic layers of doped AlGaAs and aluminum arsenide (AlAs). The AlGaAs of stack 16 is doped with the same type of impurity as substrate 14 (e.g., n type), and the AlGaAs of stack 26 is doped with the other kind of impurity (e.g., p type).

Contact layers 12 and 28 are ohmic contacts that allow appropriate electrical biasing of laser diode 10. When laser diode 10 is forward biased with a sufficient positive voltage on contact 28 with respect to contact 12, active region 22 emits light 31 which passes through stack 26.

Figure 2 is a schematic diagram of a first illustrative VCSEL in accordance with present invention. The left side of Figure 2 shows the pre-patterned VCSEL before the bonding step, and the right side shows the VCSEL after the bonding and post processing steps.

In the illustrative embodiment, a bottom mirror 50 is epitaxially formed on a first substrate 52. A top mirror 54 and an active region 56 are epitaxially formed on a second substrate 58. An annular shaped trough 60 is etched into the top surface 62 of the bottom mirror 50, where the center of the annular shape corresponds to the gain guided region 66. The etching step may use standard photolithography techniques, and may provide a gain guided region 66 of less than 5um in diameter. As indicated herein, it is contemplated that the gain-guiding region can be defined using any number of processing techniques, including etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

The substrate 58 containing the top mirror 54 and active region 56 may be flipped over as shown, and bonded to the top surface 62 of the bottom mirror 50. The resulting device has the conventional top mirror/active region/bottom mirror configuration, but has a buried void 64 defined by the annular shaped trough 60 that was etched into the bottom mirror 50. The buried void 64 defines the gain guided region 66 of the VCSEL, and may also promote optical waveguiding. The second substrate 58 may be etched or otherwise removed from the top mirror 54, if desired. Preferably, this is accomplished by lapping and polishing the second substrate 58, followed by a selective wet chemical etch. To complete the device, post processing steps may be performed, including adding appropriate top and bottom contacts 72 and 70, respectively.

This structure has a number of advantages over the prior art. First, the gain guided region 66 is defined using established photolithography techniques, which are known to be manufacturable and provide tight tolerances. Thus, the size of the gain guided region 66 may be made smaller and with more accuracy than in the prior art. A smaller gain guided region 66 may decrease the operating current of the VCSEL device, and may provide more mode control. Another advantage of the present invention is that the resulting VCSEL device is planar, as shown. This may increase the ease of batch fabrication, and possibly the reliability of the device. Furthermore, planarity favors integrability.

If any adjacent devices are present, such as in a one or two dimensional array or integrated circuits, it may be desirable to provide isolation between devices. This can be accomplished in any number of ways, including providing a deep H+ ion implant 76 through the top mirror portion, as shown. This may be performed before or after bonding.

It is envision that the present invention may improve performance and expand VCSEL utilization into advanced data/telecommunication apparatus. Planar bonding of state-of-the-art pre-patterned similar and dissimilar materials may also improve the capability to produce novel, integrated optoelectronics technology. Some illustrative applications for VCSELs constructed in accordance with the present invention include ultra-efficient, ultra-dense optical-electronic processors. These include both free-space and wave-guided optically interconnected smart pixel multi-chip modules within and between boards. The capability to produce low threshold arrays using pre-patterned fusion bonding with enhanced performance may enable two-dimensional VCSEL-array based flat panel and projection displays. Three-dimensional volumetric displays based on multiple element high efficiency VCSEL arrays are also envisioned. Finally, and because of the ability to synthesize multiple-wavelength material, applications involving wavelength division multiplexing and or multi-color displays are envisioned.

Figure 3 is a schematic diagram of a second illustrative VCSEL of the present invention. Again, the left side of Figure 3 shows the VCSEL before the bonding step, and the right side shows the VCSEL after the bonding and post processing steps. The embodiment shown in Figure 3 is similar to that shown in Figure 2 except that an ion implantation is used rather than the etching step. Accordingly, ions may be implanted near the active region 92 before the top mirror/active region structure is bonded to the bottom mirror 96. The implant may define an annular shape, with the center of the annular shape defining the gain guided region 102. Of course, the shape of the gain guided region is not limited to an annular shape. Likewise, the ion implantation may be performed in the bottom mirror 96.

An advantage of this embodiment over conventional VCSEL devices may be that lower energy ions may be used to define the gain guided region 102. In conventional VCSEL devices, the top mirror may be about 3μm thick. Thus, a high energy particle beam is typically required to implant ions through the top mirror and into the active region. With such deep implants, scatter and straggle become significant limitations on the minimum dimensions that can be achieved.

In the illustrative embodiment, the ion implant predominantly effects the surface and does not need to penetrate nearly as far into the material. Thus, ion scattering and straggle are not as significant, allowing more control over the minimum dimensions of the resulting gain guiding implant. Figure 4 is a schematic diagram of a third illustrative VCSEL of the present invention. The embodiment shown in Figure 4 is similar to that shown in Figure 3 except that a patterned oxide layer is provided. That is, rather than implanting the active region 110 with ions as described above, the top surface of the active region 110 is provided with a patterned oxide layer 112. The patterned oxide layer 112 may have an un-oxidized aperture 114 that defines the gain guided region of the VCSEL device. The patterned oxide layer 112 may be formed using a number of known processing techniques. Preferably, the oxide layer 112 may be chemically fabricated while protecting the active region 110.

Figure 5 is a schematic diagram of a fourth illustrative VCSEL of the present invention. In this embodiment, a bottom mirror 120, an active region 122 and a bottom portion 124 of the top mirror 136 are formed on a first substrate 126. The bottom portion 124 of the top mirror 136 may protect the active region during subsequent processing. The top portion 128 of the top mirror 136 is formed on a second substrate 130. An annular shaped trough 132 is etched into the bottom portion 124 of the top mirror 136, where the center of the annular shaped trough 132 corresponds to the desired gain guided region 134. The top portion 128 of the top mirror 136 may be flipped over and bonded to the bottom portion 124 of the top mirror 136, as shown. The resulting device has the conventional top mirror/active region/bottom mirror configuration, but includes a buried void 140 in the top mirror 136. The buried void defines the gain guided region 134 of the VCSEL device, and may promote optical waveguiding. Figure 6 is a table showing a detailed construction for the bottom structure of Figure 5. As indicated with reference to Figure 5, the bottom structure includes the first substrate 126, the bottom mirror 120, the active region 122 and the bottom portion 124 of the top mirror 136. In step 1, a 0.29um thick GaAs epitaxial buffer layer is grown on the GaAs substrate 126 (not shown in Figure 6). The GaAs buffer layer provides a buffer between the GaAs substrate 126 and the remainder of the VCSEL. As is known, typical GaAs substrates (e.g. wafers) have some crystalline imperfections therein. The epitaxially grown GaAs layer provides a uniform crystalline base in which the remainder of the VCSEL device may be formed. Step 2 provides a transition layer, wherein the material is linearly graded from

GaAs to AlAs. In step 3, one half of an AlAs low refractive index DBR layer is grown. Steps 4-8 form the bottom mirror 120. As shown in the "LOOPS" column, steps 4-8 are repeated thirty-one times. Step 4 provides the second half of the AlAs DBR layer. Step 5 provides a linearly graded layer, wherein the material is linearly graded from AlAs to Al_{0 16}Gao ₈₄As. Step 6 provides a 400A thick Al_{0 16}Gao ₈₄As high refractive index DBR layer. Step 7 provides a linear graded layer, wherein the material is linearly graded from Al_{0 16}Ga₀₈₄As to AlAs. Finally, step 8 provides a first half of an AlAs DBR layer. Step 9 forms the second half of the AlAs DBR layer. Step 10 begins confinement region by forming a linearly graded layer, wherein the material is linearly graded from AlAs to Al₀₆₀Gao ₄₀ As .

Step 11 provides a carrier confinement layer formed from Al₀₆₀Gao₄₀As. Step 12 forms a linearly graded transition layer, wherein the material is linearly graded from Al₀ eoGao ₄₀As to Al₀₂₅Gao ₇₅As.

Steps 13-19 form the multiple quantum- well active region 122. Step 13 provides a 100A thick Al₀₂₅Gao ₇₅As barrier layer. Step 14 provides a 70 A thick GaAs quantum- well layer. Step 15 provides a 100A thick Al₀₂₅Gao₇₅As barrier layer. Step 16 provides a 70A thick GaAs quantum- well layer. Step 17 provides a 100 A thick Al₀₂₅Gao ₇₅ As barrier layer. Step 18 provides a 70A thick GaAs quantum- well layer, and step 19 provides a 100A thick A-c^Ga^As barrier layer. Step 20 forms a linearly graded transition layer, wherein the material is linearly graded from Al₀₂₅Gao ₇₅As to Al₀₆₀Gao ₄₀As. Step 21 provides a carrier confinement layer formed from Al₀₆₀Gao₄₀As. Step 22 provides a transition layer, wherein the material is linearly graded from Al₀₆₀Gao₄₀As to AlAs. Step 23 provides a first half of an AlAs DBR layer.

Steps 24-28 form the bottom portion 124 of the top mirror 136. As shown in the "LOOPS" column, steps 24-28 are repeated two times. Step 24 provides the second half of the AlAs layer. Step 25 provides a linearly graded layer, wherein the material is linearly graded from AlAs to Al_{0 16}Gao ₈₄As. Step 26 provides a 400A thick Al_{0 16}Gao ₈₄As layer. Step 27 provides a linearly graded layer, wherein the material is linearly graded from Al_{0 16}Gao ₈₄As to AlAs. Step 28 provides a first half of an AlAs DBR layer. Step 29 forms the second half of the AlAs DBR layer. Step 30 completes the bottom portion of the top mirror by forming a linearly graded layer, wherein the material is linearly graded from AlAs to Al_{0 16}Ga„ ₈₄As.

Finally, step 31 provides a 250A thick GaAs layer. This layer serves both as one-half of a low refractive index DBR, and a bonding surface to be patterned. GaAs is chosen to minimize unwanted oxidation and to increase etch selectivity if desired. The thickness of the GaAs is about 50A thicker than the ideal thickness to accommodate any reduction caused during surface preparation and processing.

Figure 7 is a table showing a detailed construction for the top structure of Figure 5. As indicated with reference to Figure 5, the top structure includes the second substrate 130 and the top portion 128 of the top mirror 136. In step 1 , a 2900A thick GaAs epitaxially layer is grown on the GaAs substrate

130 (not shown in Figure 7). The GaAs layer provides a buffer between the GaAs substrate 130 and the remainder of the VCSEL.

Step 2 indicates that the growth is stopped or paused while the As ambient displaces the P ambient for the subsequent grown of step 3. Step 3 provides a GalnP etch stop layer. Other materials such as AlAs may also serve as an etch stop layer. Step

4 indicates that the growth is again stopped or paused in order to displace the P ambient with As ambient for the subsequent growth of step 5. Step 5 provides a GaAs Cap layer, and step 6 indicates that the growth is stopped or paused prior to the growth indicated in step 7. The GalnP etch stop layer allows the second substrate 130 to be etched away after the bottom structure and the top structure are bonded together. Step 7 provides a Al_{0 16}Ga„ ₈₄As DBR layer. Step 8 provides a transition layer, wherein the material is linearly graded from Al₀ ι₆Gao ₈₄As to AlAs. Steps 9-24 form the top portion 128 of the top mirror 136. Steps 9 and 10 provide an AlAs DBR layer. Step 11 provides a linearly graded layer, wherein the material is linearly graded from AlAs to Al₀ ^Ga,, ₈₄As. Step 12 provides a 400A thick Al₀ ,₆Gao₈₄As layer. Step 13 provides a linearly graded layer, wherein the material is linearly graded from Al_{0 16}Gao ₈₄As to AlAs Step 14 provides a first half of an AlAs

DBR layer.

As shown in the "LOOPS" column, steps 15-19 are repeated sixteen times. Step 15 provides the second half of the AlAs DBR layer. Step 16 provides a linearly graded layer, wherein the material is linearly graded from AlAs to Al_{0 16}Gao ₈₄As. Step 17 provides a 400A thick Al_{0 16}Gao ₈₄As layer. Step 18 provides a linearly graded layer, wherein the material is linearly graded from Al_{0 16}Gao ₈₄As to AlAs Steps 19 provides a first half of an AlAs DBR layer.

As shown in the "LOOPS" column, steps 20-24 are repeated two times. Step 20 provides the second half of the AlAs DBR layer. Step 21 provides a linearly graded layer, wherein the material is linearly graded from AlAs to Al_{0 16}Gao ₈₄As. Step 22 provides a 400A thick Al_{0 16}Gao ₈₄As layer. Step 23 provides a linearly graded layer, wherein the material is linearly graded from Al_{0 16}Gao ₈₄As to AlAs Steps 24 provides a first half of an AlAs DBR layer. Step 25 provides the second half of the AlAs DBR layer. Step 26 provides a linearly graded layer, wherein the material is linearly graded from AlAs to Al_{0 16}Ga(, ₈₄As. Finally, step 27 provides one half of an GaAs DBR layer.

After the bottom structure and top structure are completed, as described above with reference to Figures 6 and 7, respectively, a pattern may be formed in either the top mirror as shown in Figure 5 or in the bottom portion 124 of the top mirror 136. Preferably, the pattern is formed using photo-lithography in conjunction with a chemical etching process. For example, when a pattern is formed in the bottom portion 124 of the top mirror 136, a chemical etching process may be used to chemically remove portions of the GaAs layer formed in step 31 of Figure 6. At least the removed portions of the GaAs layer form the current confinement, or gain guiding region, of the VCSEL structure. Likewise, when a pattern is formed in the top portion 128 of the top mirror 136, the chemical etching process is used to chemically remove portions of the GaAs layer formed in step 27 of Figure 7.

After the desired pattern is formed, the top structure and the bottom structure are bonded together, as shown in Figure 5. Preferably, the bottom structure is formed on a bottom wafer and the top structure is formed on a top wafer. The top wafer may have a reduced size relative to the bottom wafer so that the top wafer can be aligned with the bottom wafer by viewing features on the top surface of the bottom wafer. However, alignment via through-epi viewing may also be performed.

The bottom structure is placed in a fusion bonding apparatus with the epitaxial growth surface facing up. The top structure (Figure 7) is placed on top of the bottom structure with the epitaxial growth surface facing down. Preferably, silicon spacer wafers (not shown) are placed above and below the pair of GaAs wafers, and a piece of graphite foil is placed above the top spacer wafer to provide an even distribution of the bonding pressure. The lid is closed on the fusion bonder and the chamber is evacuated. The temperature is raised to about 600° Celsius and a bonding pressure of approximately 200 Newtons is applied for about 1 hour.

While fusion bonding is the preferred bonding process, it is contemplated that an intermediate material may be used to bond the top structure to the bottom structure. In this embodiment, the intermediate material may be placed between the bottom and top structures. The top structure and the bottom structure may then be placed together, and the intermediate material may form a bond therebetween. Examples of intermediate materials include adhesives, polymers, other semi-conductor materials, etc. After completing the bonding process, the second substrate 130 may be selectively removed. The bonded structure is then preferably coated with plasma deposited SiO₂ to protect the edges of the wafers from the chemical etch step. The wafer pair is mechanically lapped to within about .005 inches of the InGaP etch stop layer provided in step 3 of Figure 7. The remaining .005 inch (5 mil) of GaAs is chemically removed with a 1 :8:1 solution of H2O:H2SO4:H2O2, which will stop etching at the InGaP etch stop layer.

After the second substrate 130 has been removed with the 1 :8:1 solution, the InGaP etch stop is selectively removed using HC1. It is recognized that alternate etch stop layers may be used (e.g. AlAs), and that other processes and chemicals may be used to remove the second substrate 130 from the top mirror.

After the second substrate 130 is removed, final VCSEL processing may be performed. Photo-lithographic alignment is made with the features visible on top of the periphery of the bottom wafer, or through the top wafer or bottom wafer. As indicated above, the top wafer may have a reduced size relative to the bottom wafer so that features on the top surface of the bottom wafer are visible. Post bonding processing may include, but is not limited to, front and backside metalization and patterning, passivation, and implantation or etching for isolation.

Figure 8 is a schematic diagram of a fifth illustrative VCSEL of the present invention. As indicated above, the active region for conventional GaAs VCSEL devices may include a GaAs quantum-well structure. The GaAs quantum-well structure is lattice-matched relative the GaAs/ AlAs mirror regions of the conventional VCSEL device, and thus can be epitaxially formed with the corresponding mirror regions.

VCSELs that use GaAs quantum-wells may emit at a wavelength near 0.85um.

For communication applications, it is often desirable to produce a longer wavelength of, for example, 1.3 or 1.55 μm. One method of producing this longer wavelength is to provide an InGaAsP quantum-well active region. In the illustrative embodiment of Figure 8, the active region 154 is formed from InGaAsP, and the bottom mirror 150 and the top mirror 152 are formed from GaAs DBRs. It is noted that the InGaAsP active region 154 is lattice mismatched relative to the GaAs DBR mirror regions.

In accordance with the illustrative embodiment, the bottom mirror 150 may be formed on a first substrate 156, the top mirror 152 may be formed on a second substrate

158, and the active region 154 may be formed on a third substrate 160, as shown. GaAs is the preferred substrate material for the bottom mirror 150 and the top mirror 152 because of the relative technological maturity of the AlGaAs system. Also, the AlGaAs material system exhibits better optical and thermal properties than that of InP-based materials.

To form the gain guided region, an annular shaped trough 162 is etched into the top surface 164 of the active region 154. The center of the annular shaped trough corresponds to the desired gain guided region 166. It is contemplated that the etching step may use standard photolithographic techniques, and thus may be manufacturable and tightly controlled. The remaining portions of the active region 154 that do not correspond to the gain guided region 166 may be implanted with ions, as shown by the dotted hatch 174. The ion implant may render the corresponding portions of the active region non-conductive, and thus inactive.

The third substrate 160, including the active region 154, may be flipped over and bonded to the top surface 170 of the bottom mirror 150, as shown. Thereafter, the third substrate 160 may be etched or otherwise removed from the active region 154. Then, the substrate containing the top mirror 152 may be flipped over and bonded to the active region 154, such that the top mirror 152 engages the active region 154. The second substrate 158 containing the top mirror 152 may then be etched or otherwise removed from the top mirror 152, if desired.

The resulting device has the conventional top mirror/active region/bottom mirror configuration, but has a buried void 172 defined by the annular shaped trough 162 that is etched into the active region 154. The buried void defines the gain guided region 166.

Figure 9 is a schematic diagram of a sixth illustrative VCSEL of the present invention. This embodiment is similar to the embodiment shown in Figure 8 except that the active region 180 is selectively implanted, rather than etched. Preferably, all of the active region 180 is implanted with ions except for the desired gain guided region 182. The ion implant renders the implanted portion of the active region non-conductive, and thus inactive.

Having thus described the preferred embodiments of the' present invention, those of skill in the art will readily appreciate that the teachings found herein may be applied to yet other embodiments within the scope of the claims hereto attached.

Claims

WHAT IS CLAIMED IS:

1. An electronic device, comprising: a first part, said first part including a patterned layer; and a second part bonded to said first part.

2. An electronic device according to claim 1 wherein the first part is epitaxially grown on a substrate.

3. An electronic device according to claim 2 wherein the second part is epitaxially grown on a substrate.

4. An electronic device according to claim 1 wherein said first part is formed from a first material, and said second part is formed from a second material, said first material and said second material being similar relative to one another.

5. An electronic device according to claim 1 wherein said first part is formed from a first material, and said second part is formed from a second material, said first material and said second material being dissimilar relative to one another.

6. An electronic device according to claim 1 wherein said second part is fusion bonded to said first part.

7. An electronic device according to claim 1 wherein said bond is formed by applying an intermediate material between said second part and said first part.

8. A VCSEL device, comprising: a first part formed on a first substrate, wherein said first part includes a patterned layer; a second part formed on a second substrate; and bonding means for bonding said second part to said first part.

9. A VCSEL device according to claim 8 wherein said first part includes a bottom mirror, an active region, and a number of top mirror layers.

10. A VCSEL device according to claim 9 wherein the second part includes a number of top mirror layers.

11. A VCSEL device according to claim 9 wherein at least part of one of the number of top mirror layers of the first part includes the pattern.

12. A VCSEL device according to claim 11 wherein the at least part of one of the number of top mirror layers of the first part are patterned using a process selected from the group consisting of etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

13. A VCSEL device according to claim 8 wherein the first part includes a bottom mirror and an active region, wherein at least a portion of the active region has the pattern formed therein.

14. A VCSEL device according to claim 13 wherein the second part includes a number of top mirror layers.

15. A VCSEL device according to claim 13 wherein at least a portion of the active region is patterned using a process selected from the group consisting of etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

16. A VCSEL device according to claim 8 wherein the first part includes a bottom mirror, wherein at least a portion of the bottom mirror has the pattern formed therein.

17. A VCSEL device according to claim 16 wherein the second part includes an active region and a top mirror.

18. A VCSEL device according to claim 16 wherein at least a portion of the bottom mirror is patterned using a process selected from the group consisting of etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

19. A VCSEL device, comprising: 5 a first part formed on a first substrate; a second part formed on a second substrate; a third part formed on a third substrate; wherein at least one of the first, second and third parts include a patterned layer; and o bonding means for bonding the first, second and third parts together.

20. A VCSEL device according to claim 19, wherein said first part is formed at least in part from a first material, said second part is formed at least in part from a second material, and said third part is formed at least in part from a third material, 5 wherein said first, second and third materials are similar relative to one another.

21. A VCSEL device according to claim 19, wherein said first part is formed at least in part from a first material, said second part is formed at least in part from a second material, and said third part is formed at least in part from a third material, 0 wherein at least one of said first, second and third materials are dissimilar relative to one of the other materials.

22. A VCSEL device according to claim 19 wherein the first part includes a bottom mirror formed on the first substrate. 5

23. A VCSEL device according to claim 22 wherein the second part includes an active region formed on the second substrate.

24. A VCSEL device according to claim 23 wherein the third part includes a 0 top mirror formed on the third substrate.

25. A VCSEL device according to claim 24 wherein the second substrate is removed from the active region of the second part before bonding the first, second and third parts together.

26. A VCSEL device according to claim 25 wherein the third substrate is removed from the top mirror of the third part before bonding the first, second and third parts together.

27. A VCSEL device according to claim 25 wherein the third substrate is removed from the top mirror of the third part after the first, second and third parts are bonded together.

28. A method for producing an electronic device, wherein the electronic device includes a first part and a second part, the method comprising the steps of: providing a patterned layer in the first part of the electronic device; and bonding the second part of the electronic device to the first part.

29. A method according to claim 28 wherein the second part is fusion bonded to the first part.

30. An electronic device according to claim 28 wherein the bonding step includes providing an intermediate material between said second part and said first part.

31. A method for producing a VCSEL device, comprising the steps of: processing a first part of the VCSEL device on a first substrate; processing a second part of the VCSEL device on a second substrate; providing a patterned layer in the first part of the VCSEL device; and bonding the second part of the VCSEL device to the first part of the VCSEL device.

32. A method according to claim 31 wherein the first part of the VCSEL device includes a bottom mirror, an active region, and a number of top mirror layers.

33. A method according to claim 32 wherein the second part of the VCSEL device includes a number of top mirror layers.

34. A method according to claim 32 wherein at least part of one of the number of top mirror layers of the first part include the pattern.

35. A method according to claim 34 wherein the at least part of one of the number of top mirror layers of the first part are patterned using a process selected from the group consisting of etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

36. A method according to claim 31 wherein the first part of the VCSEL device includes a bottom mirror and an active region, wherein at least a portion of the active region includes the pattern.

37. A method according to claim 36 wherein the second part of the VCSEL device includes a number of top mirror layers.

38. A method according to claim 36 wherein at least a portion of the active region is patterned using a process selected from the group consisting of etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

39. A method according to claim 31 wherein the first part of the VCSEL device includes a bottom mirror, wherein at least a portion of the bottom mirror includes the pattern.

40. A method according to claim 39 wherein the second part of the VCSEL device includes an active region and a top mirror.

41. A method according to claim 39 wherein at least a portion of the bottom mirror is patterned using a process selected from the group consisting of etching, depositing, diffusing, implanting, growing, oxidizing, and intermixing.

42. A method for producing a VCSEL device, comprising the steps of: processing a first part of the VCSEL device on a first substrate; processing a second part of the VCSEL device on a second substrate; processing a third part of the VCSEL device on a third substrate; providing a patterned layer in at least one of the first, second and third parts of the VCSEL device; and bonding the first, second and third parts of the VCSEL device together.

43. A method according to claim 42 wherein the first part of the VCSEL device includes a bottom mirror formed on the first substrate.

44. A method according to claim 43 wherein the second part of the VCSEL device includes an active region formed on the second substrate.

45. A method according to claim 44 wherein the third part of the VCSEL device includes a top mirror formed on the third substrate.

46. A method according to claim 45 wherein said bonding step includes the steps of: bonding the first part and the second part to form an intermediate part; bonding the third part to the intermediate part.

47. A method according to claim 46 further comprising the step of removing the second substrate from the active region of the second part before bonding the third part to the intermediate part.

48. A method according to claim 47 further comprising the step of removing the third substrate from the top mirror of the third part.

49. An array of electronic devices that are simultaneously formed, comprising: a first part having a number of sub-patterns formed therein that are repeated to form an overall pattern, each of the sub-patterns corresponding to at least one of the electronics devices; and a second part bonded to said first part.

50. A number of electronic devices according to claim 49 further comprising isolation means for electrically isolating selected ones of the number of electronic devices from the others.