JPS6118248A - Eye pattern measuring device - Google Patents

Abstract

PURPOSE:To attain a quantitative measurement at a high speed and with high accuracy by fetching an analog eye pattern signal to calculate the distribution of an identification level. CONSTITUTION:The analog eye pattern signal generated in an I-ch output of a demodulator 1 is fed to an A/D converter 6, a clock generated in a CLK output is fed to the converter 6 and an A/D conversion data at an eye pattern aperture point is outputted. A timing pulse is outputted from an AND gate 11 after a predetermined time and an output is fetched to a processing unit 9 from the A/D converter 6, the fetched data is calculated for histogram at the processing unit 9. A soft copy is outputted from a display device 12 and a hard copy is outputted from a printer 13 as required from the obtained histogram, which is stored in a floppy disc device 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an eye pattern measuring device capable of quantitatively measuring eye pattern information used for evaluating characteristics of transmission paths and modulators in digital transmission.

In a digital transmission system in which data is digitized and transmitted in multi-value format, an eye pattern occurs in the transmitted signal, regardless of whether it is wired or wireless.

This eye pattern is used to evaluate the state of the transmission path and the characteristics of the modulator/demodulator, but since the conventional technique is qualitative, the final result is the bit error ratio (Bit error ratio).
Error Ratio (BER)) is used for quantitative measurement. However, this BER measurement can only be performed at the input and output sections of a digital transmission system device, and cannot be performed before the data identification device in a device that includes a modem.

[Conventional technology]

Therefore, characteristic evaluation of such locations, such as multivalued QA
M modulation method ((Iuadrature 'Amplit
The above-mentioned qualitative measurement using the eye pattern is used to adjust the modulator/demodulator in the ude modulation communication system.

This measurement is performed by visually observing an eye pattern image displayed on an oscilloscope.

[Problem that the invention seeks to solve]

In measurements using such image information, the subjectivity of the measurer is easily reflected in the measurement data, and the reliability of the measurement data is B.
It cannot help but be lower than the ER value.

[Means for solving problems]

The present invention provides an eye pattern measuring device capable of quantitatively evaluating characteristics using an eye pattern, and the means thereof includes a differential amplifier that receives an analog eye pattern signal and a reference potential from an analog eye pattern signal output device. an analog converter for converting the output signal into a digital value in response to the output signal of the differential amplifier and the clock signal from the clock signal generating means; - A digital converter, a processing device that performs predetermined arithmetic processing, and digital data supply means that supplies the digital value to the processing device. □ [Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a first embodiment of the invention. In this figure, 1 is a demodulator in the 64QAM modulation system, and its ■ channel (I-ch) output, Q channel (Q-ch) output, and clock output (CLK output) are connected to the discriminator 2, while its The I-ch ratio output and CLK output are connected to the device of the present invention. That is, it is connected to one input of the I'-Ch small output variable gain differential amplifier 3, and the CLK output is connected to the buffer 4.

An offset potential supply circuit 5 serving as reference potential supply means is connected to the other input of the amplifier 3.

The output of amplifier 3 is converted to an analog-to-digital converter (hereinafter referred to as
It is abbreviated as A/D converter. )6. The output of the buffer 4 is connected to the clock input of the converter 6 via a phase shifter 7.

The output of the A/D converter 6 is connected to a processing unit (hereinafter referred to as CPU) 9 via a peripheral interface adapter (hereinafter referred to as PiA) 8. p
The iA8 clock input includes an input that receives the output of the phase shifter 7 via a buffer 10, and a CPU clock (CPU-C
The output of an AND gate 1) having an input for receiving LK) from the CPU 9 is connected to the CPU 9, which includes a digital playback device 12, a printer 13,
A floppy disk device 14 is connected.

Next, the operation of the apparatus of the present invention configured as described above will be explained.

An I-ch ratio output analog eye pattern signal (see (2-1) in Figure 2) of the demodulator 1 is generated, and this signal is amplified by the amplifier 3 so that it falls within the input range of the A/D converter 6. After that, it is supplied to the A/D converter 6.

At the same time, the clock generated at the CLK output of the demodulator 1 is supplied as an A/D clock to the clock input of the A/D converter 6 via the buffer 4 and the phase shifter 7 ((2- (See 2). By supplying this clock, A/D converted data of the eye pattern aperture point (sampling point) is output from the A/D converter 6 (see (2-3) in FIG. 2).

After a predetermined time has elapsed, AND GATE 1
) appears at one input (see point a in the figure).
(2-4) in Figure 2) and the other input of the AND gate 1) (see point b in the figure).
(See ('2-5) in the figure) and the AND gate ll
A timing pulse as shown in (2-6) in FIG. 2 is outputted from the CPU 9, and the digital value outputted from the A/D converter 6 is taken into the CPU 9 via the PiA8.

Such uptake occurs every time the timing conditions for AND gate 1) are met.

The data thus captured is obtained by the CPU 9 calculating a histogram as shown in FIG. 3, that is, the distribution of discrimination levels at the MO points of the eye pattern. Note that (3-2) in FIG. 3 is a partially enlarged view of (3-1) in FIG.

The histogram obtained as described above quantitatively represents the eye pattern, and if necessary, a soft copy thereof can be outputted from the display device 12, a hard copy thereof can be outputted from the printer 13, and a floppy disk device 14 can also be outputted. It is also possible to store the data in a file and have the above-mentioned output produced at a later time.

Also, since the standard deviation of the above distribution is calculated, B after identification
It is also possible to obtain ER, etc.

FIG. 4 shows a second embodiment of the present invention, and this embodiment differs from the first embodiment in that the reference potential of the differential amplifier 30 is changed as follows.

That is, in the first embodiment, the entire input eye pattern signal is the input range of the A/D converter 6, as shown in (5-1) in FIG. In this embodiment, as shown in (5-2) in FIG. 5, a portion of the input eye pattern signal, for example, each half of the adjacent eye portions, is
This is the input range of the D converter 6.

For this purpose, the second embodiment is characterized in that the digital value already taken into the CPU 9 is supplied to the amplifier 3 as a reference potential via the PiA 15 and the digital-to-analog converter 16.

By taking such measures, for example, in the 64QAM modulation system, the levels of 0 to 7 can be changed to (00)1) to (F
F) 141! The resolution per level would have decreased due to the output, but now the input range can be changed to (00), 6-way to (F F ) + 6 Liao, and output It is possible to obtain the distribution of identification levels with high accuracy.

FIG. 6 shows a third embodiment of the present invention, and this embodiment replaces the first and second embodiments in which data is imported into the CPU each time the timing conditions for data entry into the CPU are met. In order to reduce the CPU load spent on this import and achieve speed-up, the CPU reads the acquisition number data in response to a predetermined number of acquisitions being carried out by the acquisition buffer means. This is an improvement.

For this purpose, this acquisition buffer means has a RAM 30, and when the system is put into the mode of acquiring data from the A/D converter (same as in the first and second embodiments) 6 upon power-on, the seventh In the initialization step S1 of the main program shown in the figure, the initialization flag INIFLG is set on by program control, and the stitch 310 of FIG. 8 showing the details of the eye monitor step S2. RA by S15,316,517,818
After clearing M30, the RA is cleared from A/D converter 6.
Complete preparations for importing data into M30.

A signal for setting the above mode is also sent from the PtA 31 to the timing generator 33 via the line 32, and from this generator 33 to the latch 34, RAM 30. Control signals necessary for this purpose are supplied to the crane ladder 35 and the launch 36. The data supplied from the A/D converter 6 to the RAM 30 via the latch 34 which is launch-controlled by the output of the frequency division counter 37 is used as an address of the RAM 30, and the contents accessed by that address are read from the RAM 30 each time. It is output and incremented by 1 in the slider 35, and the incremented value is loaded into the latch 36 and then written back to the inter-address.

In this way, when data is fetched and the number of fetches reaches a predetermined value, the arrival is detected by the overflow detector 38, and a signal indicating this is sent to the enable terminals E and PiA3 of the buffer 39.
1, is supplied to the enable terminal E of the latch 40 and the timing generator 33. Then, the read request signal IRQ is transferred from the PtA31 to the CPU (7th
Step 5ll in the figure). Note that INIFLG has been cleared in step 318 in the program processing that precedes this.

The system is then switched to a mode in which all data in the RAM 30 is read into the CPU. The signal is sent from the CPU that confirmed the IRQ to the PtA 31 and then to the timing generator 33 via the PtA 31. The CPU also supplies an address for addressing the PtA 31 and the launch 40 to the address decoder 41, and also sends the address to the data bus 42 to the RAM 30. Addressed by the output from the address decoder 41, sequentially carrying all the addresses of
The address of the RAM 30 on the data bus 42 is sent to the notch 40, and the RAM 30 is enabled for reading (step 512 in FIG. 7).

Then, in response to the fact that the IRQ flag is on (Y in step S13 in FIG. 7), all data in the RAM 30 is sequentially read out using the address of the RAM 30 set in the launcher 40 (step 514 in FIG. 7). ),
These data are sequentially fetched into the CPU via the PtA31. At this time, the RAM 30 is electrically disconnected from the crane ladder 35 and the launch 36 due to the function of the buffer 39 that responds to overflow detection. Then, the RAM 30 is enabled for RAM write (step 315 in FIG. 7) and all addresses in the RAM 30 are cleared (step 516 in FIG. 7). At this time, since TNIFLG has been cleared as described above, the CPU bypasses step S17 in FIG.
A reset signal is generated on line 43 via iA 31 to reset overflow detector 38 (step 19 in FIG. 7).

Thus, the IR that was being supplied from PtA31 to the CPU
Q disappears, and the system is switched to a mode for taking in data from the A/D converter 6, and data is taken in as described above. Then, in response to the A/D converter output value, that is, the number of writes to the address of the RAM 30, that is, the number of realizations at any discrimination level at the sampling point of the eye pattern reaches a predetermined value, The data is loaded from the RAM 30 to the CPU as described above.

After such acquisition has been completed at the appropriate sampling point and the desired processing has been performed on the data, the main program of the system, assuming it has a display routine S3, is connected to the CPU. The processing results will be displayed on the screen of the display device.

In summary, according to the third embodiment, the CPU controls the A/D converter output value until the number of occurrences of the A/D converter output value as described above reaches a predetermined value. Since there is no need to send data to the import process, the load on the CPU is reduced accordingly, and data can be imported at high speed.

〔Effect of the invention〕

As explained above, according to the present invention, in addition to being able to quantitatively measure the distribution of discrimination levels at the sampling points of the eye pattern, In addition, effects such as (1) faster measurement can be achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a diagram showing the distribution of discrimination levels; FIG. 4 is a diagram showing the second embodiment of the present invention;
FIG. 5 is a diagram for explaining the difference between the embodiment in FIG. 4 and the embodiment in FIG. 1, and FIG. 6 is a diagram showing a third embodiment of the present invention.
7 and 8 are flowcharts for explaining the embodiment of FIG. 6. In the figure, 1 is a demodulator, 3 is a differential amplifier, 4 is a buffer, and 5
6 is an A/D converter, 7 is a phase shifter,
8, 15.31 is a peripheral interface adapter, 9 is a CPU, 10 is a buffer, 1) is an AND gate,
16 is a digital-to-analog converter, 30 is a RAM, 3
3 is a timing generator, 34, 36, and 40 are launches, 35 is a full addresser, 38 is an overflow detector, 39 is a buffer, and 41 is an address decoder. Figure 1

Claims (3)

[Claims] (1) A differential amplifier that receives an analog eye pattern signal and a reference potential from an analog eye pattern signal output device, means for generating a clock signal that coincides with the analog eye pattern signal opening point, and an output signal of the differential amplifier and an analog-to-digital converter that converts the output signal into a digital value in response to a clock signal of the clock signal generating means; a processing device that performs predetermined arithmetic processing; and digital data that supplies the digital value to the processing device. 1. An eye pattern measuring device comprising: supply means. (2) The eye pattern measuring device according to claim 1, wherein the reference potential is configured to be changed to a value according to the result of the processing device. (3) The digital data supply means is the analog
means for cumulatively holding the number of occurrences of the same output digital value from a digital converter; means for detecting that the number of occurrences has reached a predetermined value; and means for storing the cumulative number in response to the output of the detection means. 2. The eye pattern measuring device according to claim 1, further comprising an interface section for transferring the number of occurrences of the eye pattern to the processing device.