JPH0648442Y2 - LSI tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an LSI tester for inspecting the quality of an LSI having a one-chip television (hereinafter, 1cTV) function.

[Conventional technology]

An LSI with a 1cTV function introduces a video signal and outputs a luminance signal and a color signal for each scanning line based on the information contained in this signal. FIG. 4 shows the configuration of a conventional device for inspecting the quality of an LSI having such a function. In the figure,
The VSG (video signal generator) outputs a test video signal, and applies, for example, a so-called composite signal to a 1 cTV LSI (that is, DUT: Device Under Test) 2 to be inspected. The VSG also outputs an event signal synchronized with the horizontal scanning start position of the test video signal. The output signal of the DUT2 and the event signal are added to the VSM (video signal measuring instrument).

FIG. 6 shows a typical waveform example of the test video signal. In the figure, part (a) is a subcarrier and has 3.58 MHz.
Is a high frequency signal. Then, this high-frequency subcarrier signal is superimposed on the stepped wave. In the video signal shown in FIG. 6, the amplitude Y represents "brightness", and the subcarrier signal superimposed on each staircase wave represents "color".

The "color" information is embedded in the amplitude value and phase of the subcarrier signal in each step wave.

To check the quality of the DUT, use D for the test video signal.
Measure how faithfully the UT outputs RGB signals (color signals) or luminance signals. For example, as a test video signal, a signal having only color information as shown in FIG.
It is assumed that the RGB output of the DUT is as shown in Fig. 7 (2) when added to (the constant staircase wave in Fig. 6). The VSM in Figure 4 is the RGB
The signal level is sampled and measured at the cycle of the built-in clock signal, and the measurement data indicated by the circle in FIG. 7B is stored in the built-in memory. And the data of each circle and the 7th
The phases of the test video signal shown in FIG. 1A are compared. In this comparison operation, the falling edge of the event signal (see FIG. 7 (3)) generated in synchronization with the start position P1 of the horizontal scanning line in FIG. Compare the test video signal with the circled RGB data stored in the memory. The RGB data in FIG. 7 (2) is drawn with an ideal waveform with a delay amount of 0. However, since there is a delay time in DUT2, the actual RGB data is as shown in FIG. 7 (4) (delay time Δt). . Therefore, when the edge of the event signal is used as a trigger and the RGB signal is taken into the memory, d1 "empty data" (data that is not regular RGB data) shown in FIG. 7 (4) are stored in the memory. The actual "color information" is shown in (a) and (b) in Fig. 7 (1), but in the LSI tester it covers the entire area from the start P1 to P2 shown in Fig. 7 (1). DUT2
The RGB output of is measured as data.

As a result, the address of the actual RGB data stored in the memory is shifted by d1 with respect to the RGB data having no delay amount shown in FIG. 7 (2). Therefore, when comparing the test video signal and the RGB data, it is troublesome because it is necessary to control so as to read the data at the position deviated by the address d1.

In practice, a more troublesome problem will occur, which will be explained.

When inspecting the characteristics of a 1cTV LSI, for example, as shown in FIG. 7 (2), an accurate determination cannot be made only by the data of one scanning line due to noise contained in the measured value. Therefore, for example, the data of FIG. 7 (2) is continuously taken into the memory for 10 scanning lines, and this is averaged for determination.

There is also a desire to judge the data characteristics of Fig. 7 (2) over the entire CRT screen. In such cases, CR
A huge memory capacity is required to store the data of FIG. 7 (2) in the memory for the scanning lines over the entire screen of T. Therefore, for example, as shown in FIG. 5 (2), the CRT screen is divided into, for example, four equal parts, and 10 scanning lines are formed in each part.
RGB data is stored in memory. These 10 scanning lines are shown in block B from the top of the CRT screen as shown in Fig. 5 (2).
When 1 to B4 are set, data is stored in order from the top for each address of the memory as shown in FIG. 5 (1), so that the data of each block is stored in the memory as shown in FIG. 5 (1).

Here, the data of the block B1 is as shown in FIG.
Since d1 “empty data” due to the delay time of DUT2 is stored, the RGB data in block B1 is stored at address d1.
It is stored in the shifted position. In addition, it is the RGB data for the first scan line that causes the "empty data". For the RGB data in the subsequent scan lines, the RGB signal that is continuously output from the DUT. Since "is introduced,""emptydata" does not exist, and as a result, it becomes as shown in Fig. 5 (1).

Next, for the data of block B2, the series of operations in block B1 is temporarily stopped, and the data of FIG. 7 (4) is newly triggered by an event signal, so that d1 "empty data" is first recorded as in block B1. Store. Therefore, each RGB data of the block B2 has an address shifted by (2 × d1) from the start address AD 00 of the memory.

Similarly, block B3 is (3 x d1) and block B4 is (4
× d1) address shift. And for each block
When the RGB data is inspected, it is troublesome because it is necessary to correct only this address shift for each block and read the RGB data from the memory address.

[Problems to be solved by the device]

As described above, in the conventional LSI tester, "null data" exists in the data captured in the memory due to the signal delay time in the DUT2. Since this "empty data" shifts the address of the regular RGB data stored in the memory, the shift amount must be corrected to read the RGB data, which requires a troublesome control.
Moreover, "empty data" is stored in a valuable memory area, which is not efficient.

An object of the present invention is to provide an LSI tester that does not store the "empty data" described above.

[Means for Solving the Problems]

In order to solve the above problems, the present invention is an LSI having a single-chip television function (hereinafter, simply referred to as DUT).
The video signal generator that outputs the clock signal and the event signal that is generated in synchronization with the start position of the horizontal scanning line of the video signal at the same time when the video signal is added to An AD converter that takes in a cycle and converts it into a digital signal, a memory that stores the digital signal of the AD converter at the timing of the write signal added from the address write pulse generator described later, and a signal delay in the DUT Set value according to time Δt (N1)
To the counter described later, and count the clock signal triggered by the event signal generation, and output the signal (S10) when the number of pulses of this clock signal reaches the set value (N1) from the controller. A means comprising a counter and an address / write pulse generator for applying a write signal and an address signal to a memory at the cycle of a clock signal triggered by the generation of a counter output signal is taken.

[Action]

A set value corresponding to the delay time Δt of the DUT is set in the counter by the controller. Then, the counter counts down from the set value (N1) every time the clock signal is added, triggered by the generation of the event signal, and the content is "0".
When it becomes, a signal is output. That is, the counter outputs a signal after the delay time Δt of the DUT after the event signal is generated. Then, using the output signal of the counter as a trigger,
Since I am trying to capture the output data of the DUT one after another,
No "empty data" is stored in memory. Therefore, the conventional address correction using "empty data" is not necessary.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an example of the essential configuration of an LSI tester according to the present invention, and FIGS. 2 and 3 are time charts of the signals of the respective parts of FIG.

In FIG. 1, reference numeral 1 is a VSG (video signal generator), and as described in FIG. 4, a test video signal S1 as shown in FIG. The signal S3 is applied to the AD converter 13, counter 17, and address / write pulse generator 20 described later. Further, an event signal S2 (see FIG. 2 (2)) generated in synchronization with the start positions P1, P2, ... Of the horizontal scanning lines of the video signal is output to the flip-flop 16 and the counter 17 described later.

2 is a DUT, an LSI having the function of a one-chip television
Is. The DUT 2 introduces the test video signal S1 and outputs an RGB signal, a luminance signal, etc. corresponding to the test video signal S1. In the present specification, an example in which the RGB signal is output will be described.

Reference numeral 10 is a VSM (video signal measuring instrument) which is a main part of the present invention, and is constituted by the following elements.

Reference numeral 11 is a filter, which has a function of removing an unnecessary frequency component included in the RGB signal output from the DUT2.

Reference numeral 12 is a sample-and-hold circuit, which functions to sample the output (S5) of the filter 11 which changes moment by moment, and to enable the AD converter at the next stage (hereinafter referred to as ADC) to capture the signal. To have.

Reference numeral 13 denotes an ADC which takes in the signal S6 from the sample and hold circuit 12 at the cycle of the clock signal and converts it into a digital signal. That is, the output of the ADC 13 is a digitized output signal of the DUT.

Reference numeral 15 is a memory, which stores the signal of the ADC 13 at the timing of a write signal (WRITEPULSE) applied from an address write pulse generator described later. The address to be stored is given by the address write pulse generator 20.

Reference numeral 16 is a D type flip-flop (hereinafter referred to as DFF), which introduces the event signal S2 into the clock terminal and outputs a counter enable signal S9 (see FIG. 3 (2)) for controlling the operation of the counter. While the signal S9 is "LOW", the counter is disabled and does not count. In addition, when it becomes “HIGH”, the counter is set to the clock S
Count 3. DFF16 becomes "HIGH" at the falling edge of the event signal S2, and when a signal S10 described later is output from the counter, after a certain delay time, the signal S15 is applied to the reset terminal and becomes "LOW".

Reference numeral 17 denotes a counter, which is triggered by the generation of the event signal S2, and transmits the setting signal S1 from the controller via the register 18.
2 is loaded, and when the signal S9 from the DFF16 becomes "HIGH", every time the clock signal S3 is added, the loaded value (eg, N1) is down-counted, and when the content becomes "0", the signal S10 is added. Is output to the trigger circuit 19 and the delay element 22. Counter 17 waits for DU after event signal S2 is generated.
The signal S10 is output after the delay time Δt of T2.

Reference numeral 19 is a trigger circuit, which introduces the signal S10 from the counter 17 and outputs the signal S11 shown in FIG. This signal S
Reference numeral 11 has a function of stopping the operation of the address write pulse generator 20 of the next stage when it is "LOW", and operating the address write pulse generator 20 when it is "HIGH". The trigger circuit 19 has a built-in counter function, and when, for example, 10 signals S10 are input, its output S11 is set to "LOW".

20 is an address write pulse generator, a trigger circuit
When the signal S11 from 19 is "HIGH", the write pulse S14 and the address signal S13 are added to the memory 15 at the application timing of the clock signal S3.

Reference numeral 21 is a controller, and a read signal (READ
Signal) and read the contents of the memory 15. Also, a set value (N1) corresponding to the signal delay time Δt in the DUT 2 is set in the counter 17 via the register 18.
This set value (N1) can be easily calculated as follows.

The signal delay time Δt in the DUT 2 can be known by a time measuring device (known technique) not shown. Also, the cycle tc of the clock signal S3 can be known in advance. Set value
N1 can be calculated by the equation (1).

N1 = Δt / tc (1) The operation of the device shown in FIG.
Description will be given with reference to the drawings. A test video signal S1 as shown in FIG. 2 (1) is added from VSG1 to DUT2. At the same time, an event signal S2 as shown in FIG. 2B is output for each start position P1, P2, ... Of each horizontal scanning line of the video signal S1.

DUT2 is Δ from the start position P1 of this test video signal S1
After a delay of t, for example, the RGB signal S4 as shown in FIG. The RGB signal S4 added to this filter 11 passes through the sample hold circuit 12 and
It is added to DC13 and converted to digital signal S7 at the timing of clock S3.

However, since the write pulse S14 is not added to the memory 15 at this time, the memory 15 does not store the digital signal S7 from the ADC 13.

Hereinafter, description will be given mainly with reference to FIG. FIG. 3 is a time chart explaining the operation of fetching data into the memory 15 with a delay time Δt of the DUT 2 after the event signal S2 is generated.

When the event signal S2 is generated (see (1) in FIG. 2), the counter 17 synchronizes with this falling edge and registers 18
Load the set value (N1) from the controller 21 that was set to. This set value (N1) is a value corresponding to the signal delay time Δt in the DUT 2 as described in the equation (1). Also, the Q terminal of DFF16 becomes "HIGH" due to the generation of the event signal S2 (see (2) in FIG. 3). The counter 17 is enabled by the signal S9 becoming "HIGH" and counts down every time the clock signal S3 is input from the set value N1. Therefore, when the clock signal N1 is input, its content is "0". When the contents become "0" (see FIG. 3 (3)), the counter 17 outputs the signal S10 (see FIG. 3 (4)).

This signal S10 is delayed by DFF16 through the delay element 22.
Since it is added to the reset terminal of (see (3) in Fig. 3)
The output S9 of DFF16 becomes "LOW" (see Fig. 3 (2)).
Therefore, the counter 17 is disabled, and the counter 17 does not count even if the clock signal S3 is input.

On the other hand, the trigger circuit 19 which has introduced the signal S10 has its output S11.
Is set to “HIGH” and is added to the address write pulse generator 20.

Since the address / write pulse generator 20 applies the write pulse signal S14 and the address signal S13 to the memory 15 in synchronization with the clock signal S3 when the signal S11 from the trigger circuit 19 becomes "HIGH", the memory 15 outputs the signal from the ADC13. Start importing S7 (see Fig. 3 (7)).

Thus, the memory 15 starts the operation of fetching the signal S7 from the ADC 13 immediately after the counter 17 counts N1 clock signals S3 as shown in FIG. That is, since the RGB signal is taken into the memory 15 after the delay time Δt of the DUT 2 from the generation of the event signal S2, there is no fear of storing "null data" shown in Fig. 5 (1).

Therefore, the problems that the conventional example has can be solved. That is, when reading the RGB data stored in the memory 15, it is not necessary to correct the address and read it.

As described above, the RGB data of P1 and P2 in FIG. Here, if the set value of the counter built in the trigger circuit 19 is, for example, "10" (this built-in counter can be set by, for example, the controller 21), the RGB data for 10 scanning lines will be continuous. And take in the memory 15. That is, the event signal S2 is transmitted to the counter 17 at the start position P2 of the next scanning line.
In addition to the DFF16, the counter 17 performs the operation described in FIG.
Is repeated until the delay time Δt from the occurrence of this event signal S2.
After that, the signal S10 is again output to the trigger circuit 19 (see FIG. 2 (4)). In this way, when the built-in counter of the trigger circuit 19 counts, for example, 10 signals S10, its output S11 is set to "LOW", and the output of the address write pulse generator 20 is stopped.

After that, the controller 21 adds the READ signal S8 to the memory 15 and further adds the read address signal S17 to the memory 15 to read the contents, and conducts the quality inspection of the DUT 2.

[Effect of the present invention]

As described above, according to the present invention, "empty data" due to the delay time of DUT2 is not stored in the memory. Therefore, when the RGB data stored in the memory for inspection is read out, desired data can be read out without correcting the address shift due to “empty data”.

Moreover, since "empty data" is not stored, the memory can be efficiently used.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a main part configuration of an LSI tester according to the present invention, FIGS. 2 and 3 are time charts of signals of respective parts in FIG. 1, FIG. 4 is a diagram showing a conventional example, and FIG. ~ Fig. 7 is a diagram for explaining the problems of the conventional example. 1 ... VSG, 2 ... DUT, 10 ... VSM, 13 ... ADC, 15 ... memory, 17
... Counter, 19 ... Trigger circuit, 20 ... Address write pulse generator, 21 ... Controller.

Claims (1)

[Scope of utility model registration request] 1. An LSI having a one-chip television function
A video signal generator that outputs a clock signal and an event signal that is generated in synchronization with the start position of the horizontal scanning line of the video signal at the same time that a video signal is added to (hereinafter simply referred to as DUT) An AD converter that takes in a signal at a cycle of a clock signal and converts it into a digital signal, and a memory that stores the digital signal of the AD converter at the timing of a write signal added from an address write pulse generator described later, Setting value according to the signal delay time Δt in the DUT (N1)
To the counter described later, and count the clock signal triggered by the event signal generation, and output the signal (S10) when the number of pulses of this clock signal reaches the set value (N1) from the controller. An LSI tester equipped with a counter and an address / write pulse generator that adds a write signal and an address signal to a memory at the cycle of a clock signal triggered by generation of a counter output signal.