JPS61182258A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an SCR by a method wherein a P base layer and an N emitter layer are superposed onto one surface of an N<->-Si substrate, a P emitter layer is formed onto one surface of another N<->-Si substrate,and mirror-finished N<-> layers are joined mutually in a clean atmosphere, and joined firmly at 200 deg.C or higher. CONSTITUTION:A P-type base (PB) 12 is shaped onto one surface of an N<->-Si substrate 11 through a thermal diffusion, and an N-type emitter (NE) 13 is superposed. A P-type emitter (PE) 15 is formed onto one surface of another N<->-type Si substrate 14 through the thermal diffusion. Surfaces to be bonded in the N<->-type substrates 11, 14 are mirror-polished and processed to surface roughness of 500Angstrom or less. Degreasing is conducted and a contaminated film is removed and washed by water and dried centrifigally. Mirror surfaces are bonded mutually under the state in which there is no foreign matter substantially, and treated at 1,000-1,200 deg.C and joined. According to the constitution, the PB layer and the PE layer are shaped separately and a SCR 16 can be formed, and the anode side and the cathode side can be designed independently, thus shortening production time. When a NB layer having low lifetime is interposed between NB layers in both substrates through the irradiation of radiation or a quenching method and joined, the lifetime of carriers can be controlled partially.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a diode, a transistor, a thyristor, a GT
Regarding the manufacturing method of semiconductor devices such as Q.

[Technical background of the invention and its problems]

Manufacturing semiconductor devices includes multiple diffusion steps.

For example, a thyristor is made by thermally diffusing P-type impurities from both sides of a high-resistance N-type semiconductor substrate to form Pmm paste Pn and PM.
The emitter layer Pw is formed, and the above P type base l1jPB is formed.
The N-type emitter is thus fabricated by selectively thermally diffusing n-type impurities to form an N-type emitter. Also, P
When making a thyristor in which the impurity profiles of the type base layer Pn and the P type emitter layer PK are different, the P type base layer is formed by thermal diffusion 5 from one side, and then the P type emitter layer is formed by thermal diffusion from the opposite side. Since multiple thermal diffusion processes are involved in this way, the impurity profile previously formed by thermal diffusion changes in the subsequent thermal diffusion process, making it difficult to improve the design accuracy of the impurity profile. When changing the temperature of the P-type emitter ring formation process for 1 hour, the temperature of the previous thermal diffusion process, for example, the P-type base layer formation process.

I needed to change the time. Furthermore, since heat diffusion is performed many times, it takes time to manufacture the device.

In addition, in order to shorten the switching time, after forming the PNPN structure, minority carrier lifetime control ME such as doping with heavy metal elements and radiation irradiation is performed, but in this case, the lifetime of only the center of the N-type base layer is reduced due to some noise. However, since the overall lifetime is reduced at the same time, there is a problem in that the forward voltage drop increases significantly.

[Purpose of the invention]

It is an object of the present invention to provide a method for manufacturing a semiconductor device that eliminates the drawbacks of the conventional methods described above, can independently form impurity profiles on the anode side and cathode side, and shortens the manufacturing time. The purpose of this invention is to provide a partial control method.

[Summary of the invention]

The present invention utilizes a method of directly bonding two semiconductor substrates to obtain one semiconductor substrate.

First, a P-type base layer and an N-type emitter layer are formed on one side of a first high-resistance N-type semiconductor substrate by a method such as thermal diffusion, and separately, a P-type base layer and an N-type emitter layer are formed on one side of a second high-resistance N-type semiconductor substrate. A mold emitter layer is formed by a method such as thermal diffusion. Next, the first semiconductor substrate and @2 semiconductor substrate are bonded in a clean atmosphere with their N-type high resistance surfaces facing each other, and heat treated at a temperature of 200°C or higher to complete the bonding. Make it strong. In this way P
A thyristor with an NPN structure is manufactured.

[Effects of the Invention] According to the present invention, the anode side profile and the cathode side profile can be formed independently, and are not mutually affected by profile changes due to thermal diffusion. Furthermore, since work can proceed in parallel, manufacturing time can be shortened. Furthermore, by performing carrier lifetime control before bonding, the lifetime can be partially reduced.

[Embodiments of the invention]

The present invention will be explained in more detail below with reference to Examples.

In FIG. 1(a), P-type impurities are thermally diffused from one side of a high-resistance N-type silicon substrate 11 to form a P-type base layer (PR) 12, and then N-type impurities are thermally diffused on the same surface. , shows a state in which an N-type emitter (NB) 13 is formed. $
FIG. 1(b) shows a state in which a P-type impurity is thermally diffused from one side of a high-resistance N-type silicon substrate 14 to form a P-type emitter v1 layer (PE) 15.

These substrates are thoroughly cleaned and bonded in a clean atmosphere in close contact as shown in FIG. 1(C).

The process of forming an element wafer using the direct bonding method is as follows. First, the surfaces of two semiconductor substrates to be bonded are mirror-polished to a surface roughness of 500A or less.

Depending on the surface condition of the semiconductor substrate, pretreatments such as degreasing and stain film removal are performed. In the case of a "S" substrate, this pretreatment is, for example, a process such as s H2O2 + Hm "4 → aqua regia boil → HF. After this, the substrate is washed with clean water for several minutes, and dehydrated by drying with a spinner at room temperature. This dehydration process is to remove excessive moisture adsorbed on the polished surface of the ferrule, and it is important to avoid heating and drying at temperatures above 100°C, which will evaporate most of the adsorbed moisture. .

The polished surfaces of the post-substrates are bonded to each other in a clean atmosphere of class 1 or below with substantially no foreign matter intervening, and 2
Heat treatment at 00°C or higher. In the case of a Si substrate, the preferable heat treatment temperature is 1000°C to 1200°C. Thus, according to this embodiment, the thyristor 16 can be manufactured by forming the PB and PE separately, and the γ node side and the cathode side are independent. E can be designed. Moreover, manufacturing time can also be shortened.

[Other embodiments of the invention]

Next, the case of controlling carrier lifetime using a diode as an example will be explained. Conventional methods for shortening the switching time of semiconductor devices such as diodes, transistors, and thyristors include methods to diffuse electrical metals such as gold and platinum to form lifetime killers for minority carriers, and methods to reduce the switching time of semiconductor devices such as electron beams and gamma rays. A method has been used in which lattice defects generated in semiconductor crystals by irradiation are used as minority carrier lifetime killers.

In either method, if the switching time is shortened, the forward voltage drop (hereinafter referred to as VF) increases, the screw force consumed by the semiconductor element increases, and the temperature of the element increases, which reduces the forward current withstand capability. There was a problem.

IBEE Transactions on
Electron Devices.

VOL, ED-30, L7, July 1983 p.
, 782-p., 790 TEMPLE and I (OLR
OYD paper Opt1mizlngCarrier L
ifetime Profile for Impro
ved Trade-off Between Tu
rn-off Time and Forward D
According to rop, when excess carriers are extracted from both ends during switching, the reduction of excess carriers near the center of the N base is delayed. (Figure 3 (a)) Therefore, if a low lifetime region is provided at the center of the N base, the carrier density in the low lifetime region will quickly become smaller than the carrier density in the adjacent region, resulting in a carrier density gradient. Quickly extract a career from the normal lifetime domain. (Figure 3(b)) Case without low lifetime region and the case where the lifetime near the center of N base is 11
If a region of 50 is provided, a calculation using a computer shows that when switching from VF = 1.5V, the time toff required for the reverse current density to decrease from the peak to 1 mA/cm'' is set as a low lifetime region. The current density in the on state can be increased by 25%.However, in the conventional lifetime control method, the lifetime of only a part of the N base region can be increased by 25%. It cannot be lowered.

According to the present invention, a low lifetime region can be provided within the N base.

Figure 2 (a) shows a state in which a P emitter 118 is formed on a high-resistance N-type silicon substrate 17. Figure 2 (b)
1 indicates a state in which a high-resistance N-type silicon substrate 19 is made to have a low lifetime by a method such as quenching or radiation irradiation.

FIG. 2(C) shows an N emitter layer 2 on an N type silicon substrate 20.
1 is formed. A diode 22 is made by bonding silicon substrates of 17° and 19.20°. (Figure 2(d)
) The bonding may be performed for three sheets at the same time or twice for two sheets at a time. In order to reduce the thickness of the low lifetime region 23, the silicon substrate 17 and the low lifetime silicon substrate 19 may be bonded once, and then the low lifetime silicon substrate side may be lapped and bonded to the silicon substrate 20.

In this way, a low lifetime region can be provided anywhere within the N base. Similarly, optimum lifetime profiles can be achieved with transistors, thyristors, GTQs, etc. When creating a low lifetime region by irradiation, it is necessary to consider the annealing effect caused by heat treatment during bonding. The annealing effect at 400°C in the case of electron beam irradiation is quoted from JP-A-54-53857,
It is shown in Figure 4.

N(o): Recombination center concentration N(t) after radiation irradiation
Recombination center concentration τ after near annealing. : Lifetime value before radiation irradiation τ(0): Lifetime value D after radiation irradiation D τ(t); Lifetime value after annealing.

In addition, in FIG. 1, a thyristor structure is realized. However, as shown in FIG.
ii#51, a two-layer structure silicon substrate consisting of a high resistance base layer 52 of the opposite conductivity type, a high resistance base layer 53 of the second conductivity type, and a collector layer 54 of the fourteenth conductivity type. - The transistor structure may be realized by bonding silicon substrates of the structure by the above method. In addition, as shown in FIG.
A diode structure may be realized by similarly bonding a silicon substrate consisting of a base layer 63 of a conductivity type and an emitter layer 64 of a second conductivity type.

Furthermore, in addition to carrier lifetime control as shown in Figure 2,
This, one or both of the bases 1ijll and 14 in FIG.
In FIG. 5, the lifetime of one or both of the base layers 52 and 53, and in FIG. This can be achieved by radiation irradiation or rapid cooling.

Furthermore, although a base substrate with a short lifetime is interposed in FIG. 2, this can also be applied to FIGS. 5 and 6 by similarly inserting a base substrate with a short lifetime between the bases. Furthermore, Fig. 2.

In the examples shown in FIGS. 5 and 6, the base substrates may be inserted between, for example, two bases, and one of the base substrates may be used as a substrate with a short lifetime.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the manufacturing process of a thyristor according to an embodiment of the present invention, and FIG. Figure 3 shows the case where the lifetime is uniform (a
) and when there is a low lifetime region in the center of the N base (b
), FIG. 4 is a diagram showing the annealing effect of an electron beam, and FIGS. 5 and 6 are diagrams of other examples. In the figure, 11.14...N-type silicon substrate, 12...P-type base layer, 13...N-type emitter layer, 15...PM emitter layer, 16...thyristor, 17.20...・N
m silicon substrate, 19...Low lifetime N-type silicon substrate, 21...N-type emitter noise, 22...Diode, 23...Low lifetime. Noriyuki Chika (one idiot), who is the attorney-at-large attorney, is in charge of the report, Figure 3, and Figure 4.

Claims (9)

[Claims] (1) A three-layer structure consisting of a first emitter layer of one conductivity type, a first base layer of opposite conductivity type, and a second base layer of one conductivity type with high resistance is formed, and the second base layer side with high resistance is formed. The mirror-polished surface of the first semiconductor substrate mirror-polished and the first mirror-polished surface of the high-resistance layer.
A two-layer structure consisting of a base layer of a conductivity type and an emitter layer of a second conductivity type is formed, and the high-resistance base layer side is mirror-polished.
A method for manufacturing a semiconductor device, comprising the step of forming a four-layer thyristor structure by bonding at a temperature of .degree. C. or higher. (2) The base layer of the first semiconductor substrate and the second semiconductor substrate to be bonded.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the lifetime of one of the base layers of the semiconductor substrate is lowered in advance than the other. (3) The base layer of the first semiconductor substrate and the second semiconductor substrate to be bonded.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the lifetime of the base layer of the semiconductor substrate near the bonding surface is lowered in advance. (4) A base substrate with a low lifetime is interposed between the base layer of the first semiconductor substrate and the base layer of the second semiconductor substrate to be bonded. A method of manufacturing the semiconductor device described above. (5) The above method characterized in that a base substrate with a low lifetime and a base substrate with a high lifetime are interposed between the base layer of the first semiconductor substrate and the base layer of the second semiconductor substrate to be bonded. A method for manufacturing a semiconductor device according to claim 1. (6) A method for manufacturing a semiconductor device according to claim 1, characterized in that the region with a low lifetime is formed by radiation irradiation. (7) A method for manufacturing a semiconductor device according to claim 1, characterized in that a base substrate with a short lifetime is manufactured by a rapid cooling method. (8) A mirror-polished surface of a first semiconductor substrate formed with a two-layer structure consisting of an emitter layer of one conductivity type and a high-resistance base layer of the opposite conductivity type, with the high-resistance base layer side mirror-polished; , a two-layer structure consisting of a high-resistance base layer of the second conductivity type and a collector layer of the first conductivity type is formed, and the second semiconductor substrate is mirror-polished with the high-resistance base layer side mirror-polished. A method for manufacturing a semiconductor device, comprising the step of forming a transistor structure by bringing them into close contact and bonding at a temperature of 200° C. or higher. (9) A first semiconductor substrate formed with a two-layer structure consisting of a first conductivity type emitter layer and a high resistance second conductivity type base layer, the high resistance base layer side being mirror polished; The mirror-polished surface of a second semiconductor substrate, which has a two-layer structure consisting of a base layer of a second conductivity type of a resistor and an emitter layer of a second conductivity type, and whose high-resistance base layer side is mirror-polished, is directly polished. A method for manufacturing a semiconductor device, comprising the step of forming a diode structure by bringing them into close contact and bonding at a temperature of 200° C. or higher.