JPS61182107A - Digital controller - Google Patents

Abstract

PURPOSE:To detect early an abnormality of an arithmetic part of a controller by applying the periodical interruptions to an arithmetic processor for execution of a diagnosis instruction consisting of a combination of basic instructions and performing the second diagnosis with another combination of basic instructions if the abnormality is detected. CONSTITUTION:A main processor 10 is usually connected to a system bus 60 connected with a system memory 40, an input device 50a and an output device 50b via a bus switch circuit 25. A diagnosis processor 20 applies the periodical interruptions to the processor 10 for execution of a diagnosis instruction consisting of a combination of basic instructions. If an abnormality is detected, another diagnosis instruction is executed. When a fault is decided also with this second diagnosis, the processor 20 delivers an alarm to outside and at the same time stores the history of the abnormality. Then processor 10 is switched to a back-up processor 15 by the circuit 25. Furthermore the processor 20 is switched to a manual operation mode by a manual setting device 30.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a digital control device, and is particularly suitable for application to a measurement and control system for the safety protection system of a nuclear power plant, which requires early detection of abnormalities. This invention relates to an online diagnostic device for digitally controlled transmission.

[Background of the invention]

In nuclear power generation systems, etc., redundant systems and
For example, a parallel redundant system or a standby redundant system is used. FIG. 6 is a system block diagram of a parallel redundant system. Calculation result 1 of calculation circuits 1 and 2 having exactly the same functions
a and 2a are output to the common output circuit 3. The common output circuit 3 outputs the fail-safe direction of the system out of the two input signals la and 2a to the outside.

FIG. 7 is a block diagram of a standby redundant system, in which arithmetic circuit 1 has a self-diagnosis function and has exactly the same arithmetic function.
, 2, a dual system selection circuit 4 which receives the respective self-diagnosis results and selects the normal system, and an output 4a of the dual system selection circuit 4.
The output switching circuit 5 switches the outputs 1a and 2a of the arithmetic circuits 1 and 2 according to the following. If both systems are normal,
One predetermined arithmetic circuit 1 or 2 is selected.

For example, when arithmetic circuit 1 is operating, an abnormality occurs and arithmetic circuit 2
If the self-diagnosis indicates that the output is normal, the output is switched from 1a to 28. Even if an abnormality occurs while the arithmetic circuit 2 is operating,
This is the opposite.

Incidentally, related devices of this type include, for example, Japanese Patent Application Laid-Open No. 57-3148. Examples include JP-A-58-205203.

However, the above method does not cause malfunctions because abnormalities are observed in the output signal, but it is slow to detect abnormalities because it is viewed macroscopically at the final stage. On the other hand, in systems related to safety protection systems that trip the plant based on the measurement and calculation results of neutron flux, such as the neutron instrumentation system of nuclear power plants, early detection of abnormalities in control equipment and It is desired to reduce downtime (interval period). Therefore, when applying the conventional control system to the measurement and control system related to the safety protection system of a nuclear power plant, there is a drawback that the arithmetic unit in the control device cannot be directly diagnosed and abnormalities cannot be detected early.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital control device equipped with an online diagnostic device that constantly directly diagnoses a processor that processes data using a diagnostic processor.

[Keystone of invention]

The present invention provides a diagnostic device in a digital control device equipped with an arithmetic processing device that processes input data according to predetermined instructions, interrupts the arithmetic processing device at a preset period, and performs basic instruction processing. The arithmetic processing unit is periodically diagnosed by executing various diagnostic commands consisting of a combination of the following and comparing the execution results with the correct values. 1. If the diagnosis result is abnormal, the above-mentioned method is executed depending on the abnormal state of the arithmetic processing unit. The system is configured to execute different combinations of diagnostic commands, and when the re-diagnosis result is also abnormal, this abnormal state is recorded as a history and an abnormality alarm is output.

[Embodiments of the invention]

FIG. 1 is a diagram showing the basic configuration of an embodiment of the present invention.

A main processor 10 that performs normal data processing, a diagnostic processor 20 that diagnoses the main processor 10, an input device 50a and an output device 50b that perform input/output processing of system data, a system memory 40, and a system that connects these. A manual setting device 30 that has the function of manually setting the diagnostic cycle of the bus 60 and the diagnostic processor 1 and manually executing the diagnostic command, and a bus switching circuit 25 that switches to the backup processor 15 when the main processor 10 is abnormal.
It consists of The main processor 10 processes and calculates system data, and the diagnostic processor 20 periodically and automatically diagnoses abnormalities in the main processor. Furthermore, the manual setting device 30 allows one manual setting of the diagnostic cycle and execution of any diagnostic command.

FIG. 2 shows the overall configuration of an embodiment of the present invention.

The main processor 10 notifies the diagnostic processor 20 that the system has started up via a serial interface 105 that is electrically isolated using light (hereinafter referred to as "optical isolation"). starts data processing operation. Upon receiving the fact that the main processor 10 has started up via the optically isolated serial interface 205, the diagnostic processor 20 activates the diagnostic synchronization setting timer 204, which can manually set the diagnostic cycle. After the timer 204 is activated, the timer 204 interrupts the CPU 201 of the first diagnostic processor 20 when a preset time has elapsed. After performing interrupt processing, the CPU 101 of the diagnostic processor 20 starts diagnosing the main processor 10. A diagnosis start signal from the diagnostic processor 20 is converted into an optical signal by an optically isolated serial interface 205 built into the diagnostic processor and transmitted to an optically isolated serial interface 105 built into the main processor. This transmitted diagnosis start signal interrupts the main processor CPUIC)1.

The CPU 101 interrupts the process currently being executed.

Handles interrupts and sets current registers and flags.

The contents of the pointer are saved in the readable and writable memory 102 built into the main processor 10. The memory configuration of this readable and writable memory 102 is
As shown in the figure. The memory 102 is.

An area 1021 for saving the contents of registers, flags, and pointers of the main processor 101, an area 1022 for storing diagnostic instructions transmitted from the first diagnostic processor 20, and an area for storing the diagnostic results executed by the main processor 10 according to the first diagnostic instructions. It consists of 1023.

After the main processor 101 performs interrupt processing, the main processor 101 normally connects the main processor 10 and the system bus 60, and connects the main processor 10 and the system bus 60 to maintain electrical isolation between the main processor 10 and the system bus 60 during diagnostic processing. It is disconnected from system bus 60 by transceiver 107 . After disconnecting the main processor 10 from the system bus 60, the local path transceiver 104 electrically isolates the CPU 10I of the main processor 10 and the local bus 106 from the main processor local bus 106 within the main processor 10. Keep it.

Disconnect the CPU 101 from the main processor local bus 106. The main processor 1 indicates that this separation has been completed.
0 to the diagnostic processor 20.

Upon receiving this signal, the diagnostic processor transfers the diagnostic processing instructions prestored in the built-in read-only memory 203 to the readable and writable memory 102 built into the main processor 10, and serially transfers them to the area 1022 for storing one diagnostic instruction. It is transmitted via the interface 105°205. Serial interface 105 of main processor 10
1 diagnostic instruction is sent from the diagnostic processor 20 to the main processor 1.
After confirming that the data has been transmitted to the main processor 1, the local path transceiver 104 is released from the electrical isolation state and
CPUl0I of 0 and memory 1 where diagnostic instructions are written
02 is connected to the main processor local bus 106. C
The PU 101 executes the diagnostic command written in the memory 1022 according to the process written in the read-only memory 103, and writes the result to the area 1023 in the memory 102 in which the diagnostic results are stored. After running the diagnostic instructions,
Again, local path transceiver 104 is kept in electrical isolation and CPU 101 is disconnected from main processor local bus 104.

The main processor 1o notifies the diagnostic processor 20 that the execution of the diagnostic command has been completed, and upon receiving this signal, the diagnostic processor 20 stores the memory 102 in the main processor 10.
Upon completion of writing of the diagnostic results, the local path transceiver of the main processor 10 is released from the electrically isolated state, and the main processor CPU10I and the main processor local bus are electrically connected. After the connection between the CPU101 and the main processor local bus 106 is completed, the insulation state of the system path transceiver connecting the two main processors 10 and the system bus 60 is released, and the main processor 10 and the system bus 60 are electrically connected. Connect to. When this connection is completed, the interrupt of CPU10I of the main processor 10 is canceled and the register of the memory 102 in the main processor 10 is released.

Read from the flag and pointer save area 1021.

CPUI O1 starts normal operation and input device 50
The signal from a is processed and stored in the memory 40, and is output to the outside from the output bag [50b].

The diagnostic processor 20 has a memory 2 in which diagnostic results are written.
The contents of 02 are compared with the memory 203 which stores diagnostic results expected in advance for one variety of diagnostic commands, and an abnormality in the main processor 10 is determined.

This has been explained above. The relationship between the processing of the main processor and the processing of the diagnostic processor is shown in FIG.

Next, the diagnostic command will be explained.

The basic assembly language instructions that operate a microprocessor include the following.

(1) Data transfer command An instruction to transfer data between registers and between memory and registers.

rMOVE, + instruction, etc. that transfers the contents of specified register r□ to specified register r2.

(2) Arithmetic operation instruction register, which performs addition or subtraction between data in memory and the contents of an accumulator, or adds or subtracts 1 from data in a register or memory. An rADDJ instruction that adds the contents of a register or memory to the contents of an accumulator.

(3) Performs a logical (pool) operation on the contents of the accumulator and the contents of a register or memory in conjunction with the logical operation command status flag.

(4) Branch instruction Unconditional 9 Regardless of the conditional instruction, the normal flow of the program will be changed and the instruction stored at the address specified here will be executed.

(5) Stack/Ilo, CPU control instruction stack and stack pointer are manipulated.

Diagnostic instructions are basically composed of a simple combination of these instructions. For example, arithmetic operation instructions such as A+B, A-B, logical operation instructions such as A+B, A+B, AB, etc., from address A to B.
For example, transferring data to a street address.

Assuming that n of these basic diagnostic instructions are prepared, the processing of the diagnostic processor is to have the main processor periodically execute them one by one according to the flow shown in FIG.
The resulting abnormality diagnosis is performed.

Furthermore, if the diagnostic results obtained by these basic diagnostic commands are abnormal, the same command is executed using other data in the next cycle and re-diagnosis is performed, for example.

If A+B is executed with diagnostic instruction 1, 1 with diagnostic instruction IA, execute C+D.0 With diagnostic instruction IA, even if C+D is executed several times with the same data and an abnormality is determined to be abnormal more than a certain number of times. It's fine, and you can run it several times with different data. If an abnormality is determined in this re-diagnosis, the diagnostic processor enters abnormality processing.

In abnormality processing, an alarm is issued to the outside and the history of the abnormality is stored. Then, the manual setting device 30 switches the diagnostic processor 20 to manual operation, and a person confirms and analyzes the abnormality history. Furthermore, various diagnostic commands can be designed and executed depending on the state of the main processor 10 at this time.

If there is an abnormality, we will notify the outside with an alarm etc.
The path switching circuit 25 makes it possible to switch from the main processor 10 to the backup processor 15 and continue control.

The above is a procedure for one diagnostic process, and the cycle setting of the variable diagnostic cycle timer 204, which performs such diagnostic processing for each interrupt of the variable diagnostic cycle timer 204 built into the diagnostic processor, is directly connected to the diagnostic processor local bus 206. The manual setting device 30 has a function of manually causing the diagnostic processor 20 to execute necessary diagnostic commands.

[Effects of the Invention] According to the present invention, the arithmetic unit of a digital control device is constantly and periodically diagnosed on-line using various commands consisting of a combination of simple basic commands, and when an abnormality appears, it is diagnosed. Further, an online diagnostic device is provided which performs a re-examination depending on the condition, and if it is still determined to be abnormal, stores the abnormality history and outputs an alarm. When an alarm is output, various diagnostic commands can be freely executed to analyze the abnormality, so abnormalities in the calculation section can be detected in detail and early, resulting in preventive maintenance and reduced downtime.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of a digital control device according to the present invention, FIG. 2 is a block diagram showing the configuration of the device shown in FIG. 1 in more detail, and FIG. Figure 4 is a diagram showing the memory configuration of writable memory, Figure 4 is a diagram showing the relationship between the processing of the main processor and the processing of the diagnostic processor, Figure 5 is a flowchart of the processing of the diagnostic processor, and Figure 6 is a diagram of the parallel redundant system. Block Diagram FIG. 7 is a block diagram of the standby redundant system. 1.2... Arithmetic circuit, la, 2a... Output signal, 3
...Common output circuit, 4...Double system selection circuit, 4a.
... Output signal, 5... Output switching circuit, 10... Main processor. 15... Backup processor, 2o... Diagnostic processor, 25... Bus switching circuit, 30... Manual setting device, 40... System memory, 50a... System input device, 50b... System Output device, 60・
...System bus, 101...CPU, 102...
memory. 103... Read-only memory, 104... Local bus transceiver, 105... Serial interface, 106... Main processor local bus, 107...
...System bus transceiver, 201...CPU,
202...Memory, 203...Read-only memory,
204...Diagnostic cycle setting timer, 205...Serial interface, 206...Diagnostic processor local bus.

Claims (1)

[Scope of Claims] 1. In a digital control device equipped with an arithmetic processing unit that performs arithmetic processing on input data according to predetermined instructions, an interrupt is applied to the arithmetic processing unit at a predetermined cycle, and basic commands are executed. The arithmetic processing unit is periodically diagnosed by executing various diagnostic commands consisting of a combination of the above and comparing the execution results with the correct values. If the diagnosis result is abnormal, the above-mentioned method is executed depending on the abnormal state of the arithmetic processing unit. A digital control device comprising: a diagnostic device that executes different combinations of diagnostic commands, records the abnormal state as history when the re-diagnosis result is also abnormal, and outputs an abnormality alarm. 2. The digital control device according to claim 1, wherein the data transmission path between the diagnostic device and the arithmetic processing device is electrically insulated from the original data input/output path. 3. The digital control device according to claim 2, wherein the data transmission path between the diagnostic device and the arithmetic processing device is an optical communication path. 4. A digital control device according to any one of the above claims, characterized in that the digital control device is equipped with a setting device that allows the diagnostic command to be freely rewritten from the outside while the arithmetic processing device is in an online state during arithmetic processing. 5. The digital control device according to claim 4, characterized in that the setting device includes a display section for freely reading out the abnormality history from the outside in an online state. 6. A digital control device according to any one of the above claims, characterized in that there are a plurality of arithmetic processing units, and if one is abnormal, switching to the other arithmetic processing unit is performed by a signal from a diagnostic device. .