JPS61181271A - Line thickening processing circuit - Google Patents

Abstract

PURPOSE:To attain ease of line thickening processing to a drawn picture by providing a drawing picture refresh memory having a half resolution in longitudinal and lateral directions respectively and an operating section applying the line thickening processing in addition to a document refresh memory. CONSTITUTION:When a document input indication or a drawn picture input indication is inputted from an operating device section 12, a control section 11 transfers and stores document information inputted from a document input section 1 or drawn picture coordinate information obtained by sampling drawn picture information inputted from a drawn picture input section 13. When a retrieval display indication for document or drawn picture is inputted from the operating section 12, a document or drawn picture coordinate is read from each storage location of a document file section 2. In case of the document information, it is transferred to a document refresh memory 5 via a buffer memory section 13, while the drawn picture coordinate information is written in a drawn picture refresh memory section 6 after interpolation processing is applied by a drawn picture information decoding section 4 and the corresponding drawn picture information is transferred to an operating section 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Optical "W" and "L" (Industrial Application Field) The present invention provides a refresh memory for use in electronic conference devices and document file devices that electrically store and display high-definition image information. The present invention relates to a thick line processing circuit that electronically enlarges the above image data.

(Prior Art) Conventional electronic conference devices and document file devices that electrically store and display high-definition image information have a configuration that only searches for and displays documents and drawings.

(Problem to be Solved by the Invention) The document is input using a facsimile machine with a resolution of about 8 dots/mm, and the line width of the second character in the document is 2 to 3 dots/m.
Displayed as m.

On the other hand, since the drawing is displayed by connecting the coordinates input from the input tablet with a straight line, if the drawing is displayed on the refresh memory with the same resolution as the document, the line width of the drawing will be thinner than the line width of the document. The problem was that it looked very unnatural.

(Means for Solving the Problems) In order to solve these problems, the present invention provides, in addition to the document refresh memory, a drawing refresh memory with half the vertical and horizontal resolutions, and thick line processing. A calculation unit that performs this is provided so that thick lines can be easily drawn.

Hereinafter, a detailed explanation will be given using the drawings.

(Embodiment) FIG. 1 is a functional block diagram as an embodiment using the thick line processing circuit of the present invention applied to a high-definition image information storage and display device using a superimposed display method.

In the figure, ] is a document input section such as a facsimile machine, 2 is a document file section such as a hard disk that stores input documents, and 3 is a document file section such as a hard disk that stores input documents.
4 is a buffer memory unit that matches the transfer speed with the refresh memory unit 5 to be described later, and 4 is a drawing refresh memory unit that interpolates the drawing coordinate string stored in the document file unit 2 using straight lines and decodes it into drawn image information. , 5 is a document refresh memory unit that stores display image information and outputs a display image signal, 6 is a drawing refresh memory unit that stores drawn image information, and 7 is a bold line for reading drawn image information from the drawing refresh memory unit 6. 8 is a display image signal synthesis unit that superimposes the display image signals from the document refresh memory unit 5 and the calculation unit 7; 9 is a display image signal synthesis unit that outputs the display image signal while performing the conversion process; C
A display section such as RT, 10 is a document refresh memory section 5
．． Drawing refresh memory section 6. A timing control unit for controlling the arithmetic unit 79 and the display image signal synthesis unit 8 and the like to obtain a desired display image; 12 an operating unit for instructing search 9 display of a desired document; A control section 13 controls various parts within the device and issues operational instructions based on instructions, and 13 is a drawing input section such as a tablet using a stylus or the like for inputting drawn images.

FIG. 2 is a conceptual diagram showing the relationship between drawing data in the drawing refresh memory space and display data created by thick line processing corresponding to the document refresh memory space.
(a) is the data in the drawing refresh memory space, (
b) is created data corresponding to the document refresh memory space.

Figure 3 shows the processing in the arithmetic unit, where (a) shows the line memory for drawing information that stores the drawn image information from the refresh memory for drawing, and (b) shows the line memory that stores the created data. show.

FIG. 4 is a functional block diagram showing an example of the configuration of the arithmetic unit, in which 14 is a line memory for two lines of drawing information;
5 is a logic circuit that performs logical operations; 16 is a switch that distributes the display image created by the logic circuit 15 to a line memory for display signals to be described later; 17 is a display that accumulates display image signals and transfers them to the display image signal synthesis section 8 A line memory for four lines of display image signals having a double buffer configuration for two lines of image signals; 18 a switch for selecting and switching the display image signal to the display image signal synthesis section 8; 19 controlling the entire calculation section 7; This is the arithmetic control unit that performs the calculations.

FIG. 5(a) is a logical configuration diagram of the logic circuit 15 in FIG.
b) is the logical formula, A, B, C, D are processing target image information obtained from the drawing information line memory 14, I, I
T, I'll, and IV are display image signals processed by the thick line processing circuit of the present invention.

Next, the present invention will be explained in detail.

(i) When a document input instruction is input from the information input operation unit 12, the control unit 11 controls the document input unit 1 and the document file unit 2, and converts the document information input from the document input unit 1 into a document file. The data is transferred to section 2 and stored. Further, when a drawing input instruction is input from the operating device section 12, the control section 11 controls the drawing input section 13 and the document file section 2, and the drawing input section 13 samples the drawing information input from the drawing input section. The drawing coordinate information obtained is transferred to the document file section 2 and stored therein.

(ji) When a document search and display instruction is input from the document display operation unit 12, the control unit 11 detects the storage location of document information, and subsequently controls the document file unit 2 and buffer memory unit 3, The corresponding document information is read from the storage location of the document file section 2 and transferred to the document refresh memory section 5.

The buffer memory unit 3 controls writing of document information from the document file unit 2 into the refresh memory in accordance with the memory refresh cycle of the document refresh memory unit 5. The document refresh memory section 5 outputs the transferred document information to the display image signal synthesis section 8 as a display image signal.

In the display image signal synthesis section 8, based on the timing control signal from the timing control section 10, the display image signal from the document refresh memory section 5 and the display image signal from the calculation section 7 are logically summed and outputted to the display section 9. do.

(For) When a drawing search display instruction is input from the drawing display operation device section 12, the control section 11 detects the storage location of the drawing information, and subsequently controls the document file section 2, the drawing information decoding section 4, The corresponding drawing coordinate information is read from the detected storage location of the document file section 2 and transferred to the drawing information decoding section 4.

The drawing information decoding section 4 uses the drawing coordinate information from the document file section 2 to perform interpolation processing to connect the coordinates with a straight line, and stores the data in the drawing refresh memory section 6 in accordance with the memory refresh cycle signal from the timing control section 10. Write.

(a) In the drawing refresh memory section 6, the readout signal such as address information from the timing control section 10 causes the
The corresponding drawing information is transferred to the calculation unit 7.

(b) In the calculation section 7, as shown in FIG. 4, the drawing information transferred from the drawing refresh memory section 6 is temporarily stored in the drawing information line memory 14 having a capacity for two lines.

(C) When two lines of drawing information are transferred to the drawing information line memory 14, the 4 bits (A, B, C, D) specified in FIG. 3(a) are input to the logic circuit 15. .

(d) The logic circuit 15 performs calculations according to the logic specified in FIG. Transfer to the location specified in (b).

(e) Repeat (C) and (d) until processing for one line is completed.

After completing the processing for one line, the arithmetic control section 19 controls the switches 16 and 18 to sequentially transfer the display image signals in the double-buffered display image signal line memory 17 to the display image signal synthesis section 8. do. At the same time, the timing control section 10 controls the drawing refresh memory section 6 to transfer drawing information for the next next line to the drawing information line memory 14.

The drawing information line memory 14 discards the data of the older line among the two lines, takes in the transferred new line, and sequentially performs the processing starting from (b).

When the processing for one page is completed, the process returns to the top of the page and sequentially refreshes the data.

Effect of clarity As explained above, the present invention uses, in addition to the document refresh memory, a drawing refresh memory with half the vertical and horizontal resolutions and an arithmetic unit that performs thick line processing, so that thick lines can be easily made. By doing this, in devices that use high-definition image information and drawing using a stylus pen, etc., it is not necessary to set memory with the same capacity as the document refresh memory for drawing, and it is possible to draw on top of the document refresh memory. Compared to the method of superimposing
There are advantages such as being able to avoid the complexity of processing when erasing the entire surface and reducing the drawing and erasing time.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a high-definition image information storage and display device using a superimposed display method as an example using the thick line processing circuit of the present invention, and FIG. 2 is a drawing of a refresh memory space for drawing. A conceptual diagram showing the relationship between data and display data created by thick line processing corresponding to the document refresh memory space. Figure 3 shows the processing in the calculation section, and (a) is from the drawing refresh memory section. drawing information line memory that stores drawing image information;
(b) is an explanatory diagram showing a line memory that stores created data, FIG. 4 is a functional block diagram showing a configuration example of the calculation section, and FIG. 5(a) is a logical configuration diagram of the logic circuit 15 in FIG. 4. , (b) is its logical formula. 1... Standing input unit, 2 - Document file unit, 3 Buffer memory unit, 4... Drawing information decoding unit, 5 Document refresh memory unit, 6... Drawing refresh memory unit, 7 - Arithmetic unit, 8 ...Display image signal synthesis section, 9. Display section, 10. Timing control section,
11... Control unit, 12 - Controller unit, 13 - Drawing input unit, 14... Line memory for drawing information, 15
・ Logic circuit, 16.18... Switch, 17 ・
- Line memory for display image signals, 19... Arithmetic control unit.

Claims (1)

[Scope of Claims] Drawing input means for electrically encoding and inputting drawing information of characters and figures, memory means for storing the input drawing information, and storage capacity of the memory means of 2 in the vertical and horizontal directions.
a display means having twice the display resolution; a line memory means for storing memory output for two lines in display line units;
A means for reading out a total of four pixels of 2×2 continuous in the horizontal and vertical directions from the drawing information stored in the line memory means, and generating four new pixels from the four pixels by a logical operation; The means includes line memory means having a double buffer structure for storing four pixels as display information for two lines, and generates four pixels by a logical operation using the drawing information for two lines read from the memory means, The data read address in the line memory means is increased horizontally pixel by pixel, and
reading pixel data from the line memory means and using the drawing information twice to generate display information with twice the horizontal resolution; By reading the 1-line drawing information of , reusing the previously used 1-line drawing information, and generating 2 new lines of display information from the 2-line drawing information, the vertical and horizontal resolutions are doubled. generating display information having a width of 2 pixels (2 lines) on a display means;
A thick line processing circuit that performs an operation when generating 4 pixel data so that a smooth change is made when displaying the 2×2 4 pixel data array pattern on the display unit.