JPH0421189A - Image memory circuit - Google Patents

Abstract

PURPOSE:To convert image data by a comparatively compact circuit by controlling an image memory circuit so as to input/output data in/from an image memory by sequential access or random access and using the image memory as a lookup table. CONSTITUTION:The image memory 2 and an image IO circuit 3 are controlled in accordance with an instruction mode from a computer 100 and the I/O of a data signal 13 based upon the sequential access of the memory 2 or a data signal based upon its random access is controlled between a picture element data bus selectively connected to the circuit 3 out of buses 8 to 11 and the memory 2. Either one of addresses from a sequential access transfer address circuit 4 based upon an address switching circuit 6 and a random access picture element data selecting circuit 5 is selected. The image memory can be used as a large scale lookup table by the sequential I/O access/random access enabled structure, and at the time of combining plural circuits 16, image data conversion and geometric conversion can be executed by a comparatively compact circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for the purpose of image conversion of a digital image 1 input from an imaging device such as an area sensor and a digital image created by a computer or the like.

[Summary of the invention]

The present invention utilizes the sequential access function and random access function of the image memory to add an image conversion function to the image memory that holds multivalued digital images.

[Conventional technology]

Image conversion in multivalued digital image processing includes conversion of data held by pixel values such as density emphasis 1 inversion, compression, and geometric conversion such as parallel image translation and mirroring, and is a relatively widely used method. It is.

However, in conventional technology, when performing these image conversions at high speed, a lookup system consisting of a single or multiple image memories that hold images and a relatively small capacity memory for the purpose of converting data held by image pixel values is used. Generally, it consisted of an up-table format conversion circuit, a conversion circuit for the purpose of geometric conversion of images, and a high-speed image bus connecting these.

[Problem to be solved by the invention]

However, the conventional technology requires a dedicated circuit for performing each conversion in addition to an image memory for holding the image, and has the disadvantage that the circuit becomes relatively large in size.

Therefore, in order to eliminate such drawbacks, the present invention enables the image memory itself that holds images to also be used as a relatively large-capacity lookup table type memory.
This allows conversion of pixel value data held by an image and geometrical conversion of the image using a relatively small-scale circuit.

[Means to solve the problem]

In order to solve the above problems, the present invention has a configuration that allows input/output from an image memory that holds images to an image bus in either sequential access or random access operation mode, and also enables input/output from an image memory that holds images to an image bus. As an addressing format when accessing data, the configuration allows for both sequential scanning addressing and addressing using a combination of specific signals on the image bus.

[For production]

By configuring as described above, the image memory not only inputs and outputs held digital images to and from the image bus in a sequential scanning manner, but also inputs and outputs the digital images held on the image bus to pixel value data at an arbitrary address specified by a specific combination of signals on the image bus. Random access input/output is possible, and the image memory can be used as a lookup table type memory.

〔Example〕

Specific embodiments of the present invention will be described below based on the drawings.

In FIG. 1, a control circuit 1 controls image transfer and conversion synchronized with the cycle of one frame of video according to instructions from a computer 100 via a bus 15, and also transfers images from an image memory circuit 16 via a bus 15. It performs overall control of the image memory circuit 16, such as controlling operational modes such as reading and writing by sequential access or random access in conversion, or generating clocks, various synchronization signals, and control signals.

The image memory 2 is a memory that holds a multivalued digital image, and in this embodiment, each pixel has a value expressed by 9 bits, and consists of 512 pixels in both the horizontal and vertical directions. The image memory 2 also has a sequential input/output function and a random input/output function for the pixels it owns, and has a sequential access input/output signal 13 and a random access input/output signal 1, respectively.
4, the held pixel value data is input/output. Furthermore, the random access input/output signal 14 of the image memory 2 is connected to the bus 1.
5 to the computer 100, and the computer 100 can randomly access any pixel value data held in the image memory 2.

Next, the image bus 7 is composed of four pixel data buses 8 to 11 and a control signal bus 12, and the pixel data buses 8 to 11 are used between the plurality of image memory circuits 16.
Pixel value data corresponding to four pixels are simultaneously transferred bidirectionally.

The image input/output circuit 3 receives sequential access input/output signals 1 from the image memory 2 under the control of the control circuit 1.
3 and a random access input/output signal 14 to one of four pixel data buses 8 to 11 in the image bus 7.

Transfer address circuit 4 generates sequential input/output start addresses when image memory 2 operates in sequential access mode during image transfer on image bus 7, and sequentially selects appropriate timings under control from control circuit 1. Update this and output it.

During image transfer on the image bus 7, the pixel data selection circuit 5 selects and outputs a specific signal or a combination thereof from the pixel data buses 8 to 11 in the image bus 7 under the control of the control circuit 1.

During image transfer on the image bus 12, the address switching circuit 6 outputs an address signal output from the transfer address circuit 4 when the image memory 2 operates in sequential access mode, and outputs an address signal output from the transfer address circuit 4 when the image memory 2 operates in random access mode. When the computer 100 accesses the image memory 2 through the bus 15, the signal output from the pixel data selection circuit 5 is transmitted to the computer 100 on the bus 15.
The address signal generated by is selected under the control of the control circuit 1 and outputted to the image memory 2 as a memory address signal 17.

The operation of the present image memory circuit will be explained below based on the concave surface.

FIG. 2 schematically shows a digital image transfer operation between two image memory circuits. An image memory circuit 20 in the drawing holds a transfer source digital image, and transfers the held digital image to an image memory circuit 21. Both image memory circuits 20, 21 operate in a sequential access mode, and the digital images held by the image memory circuit 20 are read out pixel by pixel onto the pixel data bus 23 of the image bus 22 in a sequential scanning manner. Image memory circuit 21 synchronously writes pixel data from image memory circuit 20 on pixel data bus 23 into its image memory in a sequential scanning manner.

FIG. 3 schematically shows the image conversion operation in the image memory circuit. The image memory circuit 30.3132 holds the digital image to be converted in its internal image memory;
Each operates in sequential access mode, and the digital image data held by the image memory circuit 30 is transferred to the image bus 3.
The digital image data held by the image memory circuit 31 is transferred to the pixel data bus 36 in the pixel data bus 37 in the pixel data bus 37.
The digital image data held by the image memory circuit 32 is read out in pixel data units in sequential scanning synchronization with the pixel data bus 38. Further, the image memory circuit 33 holds data in which pixel values in the image memory indicate an image conversion format, and operates in a random access mode. In this example, the data at the address of the image memory determined by the combination of pixel data on the pixel data bus 36, 37, 38 is read out and output to the pixel data bus 39. The image memory circuit 34 operates in a sequential access mode and writes data on the pixel data bus 39 into its internal image memory in a sequential scanning manner.

That is, in this example, data constituted by a combination of corresponding pixel data of three digital images held by the image memory circuits 36, 37, and 38 is converted by data indicating the conversion format held by the image memory circuit 33. , will be stored in the image memory circuit 34.

FIG. 4 schematically shows the geometric conversion operation of a digital image between image memory circuits. Image memory circuit 5
0 holds the digital image before conversion in the internal image memory, operates in a sequential access mode, reads out the held digital image in pixel data units in sequential scanning synchronization, and uses the pixel data bus in the image bus 54. 55. The image memory circuits 51 and 52 hold coordinate data of the storage location of the pixel data corresponding to the digital image held by the image memory circuit 50 when the data corresponding to the pixel value in the image memory is geometrically transformed. The memory circuit 51 stores horizontal coordinate data, and the image memory circuit 52 stores vertical coordinate data. The image memory circuit 51
52 operate in a sequential access mode, read out pixel data held in the image memory in a synchronous and sequential scanning manner, and output the pixel data to pixel data buses 55 and 56 in the image bus 54.

Image memory circuit 53 operates in a random access mode and writes pixel data on pixel data bus 55 to an address in the image memory determined by a combination of pixel data on pixel data buses 56 and 57.

That is, in this example, the digital images held by the image memory circuit 50 are sequentially stored in the image memory circuit 53 according to data representing the coordinates held by each corresponding pixel of the image memory circuits 51, 52.

〔Effect of the invention〕

As explained above, the present invention makes it possible to use the image memory itself as a relatively large-capacity Lufukuassobtable-format memory, and also performs conversion of pixel values of image data and geometric conversion of images. These conversions can be performed with a relatively small-scale circuit configuration without providing any circuits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the present invention, Fig. 2 is an explanatory diagram of operations in image transfer, Fig. 3 is an explanatory diagram of operations in converting pixel value data of an image, and Fig. 4 is an illustration of operations in geometric conversion of an image. It is an explanatory diagram.・Control circuit image memory ・Image input/output circuit ・Transfer address circuit ・Pixel data selection circuit ・Address switching circuit Image bus ・Pixel data bus A ・Pixel data bus B ・Pixel data bus C Pixel data bus D Applicant: Seiko Electronic Industries, Ltd. Company agent Patent attorney Keisuke Hayashi 22 image bus diagram

Claims (1)

[Claims] A sequential access input/output unit that represents a grayscale image and holds a digital image in which each pixel has multiple gradations, and that sequentially and continuously inputs and outputs pixel data corresponding to one specified horizontal row of the image. , an image memory having a random access input/output unit that discretely inputs and outputs pixel data at specified addresses, pixel data from the sequential access input/output unit of the image memory, and pixels from the random access input/output unit. an image input/output circuit that inputs and outputs data to an external image bus according to a specified operation mode;
Selects a combination of a transfer address circuit that generates vertical and horizontal image write and read start coordinates for sequential access using the sequential input/output section of the image memory and specified signals in the external image bus. A pixel data selection circuit to be output, a signal generated by the transfer address circuit, a signal output by the pixel data selection circuit, and a signal output from an external computer are selected according to a specified format, and the address of the image memory is selected. An image memory circuit consisting of an address switching circuit that outputs .