JPS6118055A - Abnormality detecting system for access to out-area memory - Google Patents

Abstract

PURPOSE:To detect assuredly the generation of an access abnormality by comparing an access with the information stored previously for detection of the abnormality when each block gives an access to the areas excluding a using area on a common memory. CONSTITUTION:Processors 21-1-21-4 deliver the memory address signals as well as the processor number signals onto a common bus 20 when those processors try to give accesses to a common memory 22. The memory 22 stores the processor number signals and the memory addresses allocated to the processors in correspondence and compares the processor number supplied from the bus 20 with the memory address. When the coincidence is obtained, the data signal on a designated address is read to the bus 20 out of the memory 22 or the data signal delivered onto the bus 20 is written to the memory 22. If no coincidence is obtained from said comparison, an alarm signal is delivered to the bus 20 from the memory 22 to show an access abnormality.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiprocessor system in which a plurality of processors and a shared memory are connected via a common bus, and information is transferred between the processors via the common bus. , it is possible to detect when each processor accesses an area other than the used area in the common memory, and therefore to detect abnormal accesses to memory outside the real area, which can prevent erroneous accesses and improve system reliability. It is about the method.

[Conventional technology]

FIG. 8 shows a multiprocessor system in which a plurality of processors and a common memory are coupled via a common bus, and information is transferred between the valley processors via the common memory. In the same figure, 1-1.1-2゜1-s, °..., 1
-N are processors, and are connected to each other via a common bus 2, and further connected to a common memory 3 via a common bus 2.

FIG. 9 shows a conventional configuration example of the common memory 3 in FIG. 8. In the figure, 10 is a bus, 11 is an address decoder, 12 is a memory element, 13 is an address signal receiver, 14 is a parity check circuit, and 15 is a data signal driver/receiver.

FIG. 1O shows an example of an address map for the common memory. In Figure 10, address AD
DO to ADDI are areas that are commonly permitted to be accessed by each processor.

Also addresses ADD2~ADD3, ADD4~AD
D5, ADiD6~ADD7,・Song・, ADD
(N-1) to ADDN are processors 1-1.1-2.1-11. in FIG. 8, respectively. ......, 1-N
This is an area that is only authorized for access.

An overview of a common memory access method in a conventional multiprocessor system will be explained below based on these figures. For example, when processor 1-2 in FIG. 8 attempts to access common memory 3, processor 1
-2 on the common bus 2, outputs the common memory address corresponding to the area that the processor 1-2 is permitted to access. In the common memory, as shown in FIG. 9, this address signal is received from the bus 10 via the address signal receiver 13, and the address decoder 11 decodes the upper part of the received address and sends the output to the memory element 12. The memory element 12f is selected by applying the signal to the pin 1 select terminal C8.

As a result, when there are a plurality of memory elements constituting the common memory 3 (only the memory element 12 is representatively shown in FIG. 9), the desired memory element can be selected. The lower part of the address signal is used to access the desired address in the selected memory element 12.

On the other hand, depending on the purpose of access (reading or writing), the processor 1-2 provides the memory element 12 via the RD double signal or the WT double signal bus 10, respectively. As a result, at the time of reading, the data at the designated address of the memory element 12 is read out, and the data signal driver/receiver 1
5 to bus lO, and when writing, bus 10
The above data is applied to the memory element 12 via the data signal driver/receiver 15 and written to the designated address.

However, with such a common memory access method, there is a possibility that an unauthorized area may be accessed. For example, if an abnormality occurs in the address signal receiver 13, a memory element other than the memory element to be selected may be selected. On the other hand, a parity check circuit 14 is provided to detect errors in the read data signal, and performs a parity check using the output data and the parity bit given as the lowest part of the address signal. Natte is able to detect data errors, but
For example, if there is an abnormality in the data signal driver/receiver 15 and an even number of bit errors occur in the data, the data abnormality cannot be detected. Therefore, the parity check method has limitations in detecting erroneous accesses.

Further, it is not preferable to provide a parity check circuit for the purpose of preventing erroneous access because it complicates the configuration.

If an access abnormality to the common memory cannot be detected in this way, the operation of the entire multiprocessor system may be hindered. For example, in FIG. 8, processor 1-= is an area that only processor 1-1 is permitted to access (ADD2 to ADD3 in FIG. 10).
), if processor 1-1 reads from that address, the data that should originally be at that address will be changed to the data written by processor 1-2. This will cause a problem in the operation of the system. Also processor 1
-1 reads from a certain address in the area (ADD 4 to ADD 5 in FIG. 10) that is permitted only for processor 1-2 to access, even if processor i-t should originally read the address. Since data different from the original data is read, there is a risk that system operation will be hindered.

Due to these problems, in the conventional configuration as shown in FIG. 9, it is not possible to guarantee the data that is read into the common memory, which inevitably lowers the reliability of the system.

[Problem that the invention seeks to solve]

The present invention provides a multiprocessor system in which a plurality of processors and a common memory are connected via a common bus, and information is transferred between the processors via the common memory, in which each processor has a common memory defined for each processor. This is intended to be able to reliably detect when an access abnormality occurs that involves accessing an area other than the above-mentioned used area.

[Means for solving problems]

The present invention provides a multiprocessor system in which a plurality of processors, a common memory, and a common bus are connected to each other, and information is transferred between each processor via the common memory. outputs the number determined for its own processor along with the memory address when accessing the common memory, and in the common memory, it outputs information on the input memory address and processor number, and the pre-stored processor number and memory usage area for each processor. The information is compared and verified, and if they do not match, an access abnormality of the processor is detected.

[Effect]

According to the present invention, in a multiprocessor system in which a plurality of processors and a common memory are coupled via a common bus and information is transferred between the processors via the common memory, each processor has a When an area other than the used area on the common memory is accessed, it is possible to detect an access abnormality by comparing it with previously stored information. It is possible to guarantee read data and improve system reliability.

〔Example〕

1 to 4 show an embodiment of the present invention, and FIG. 1 is used for data transfer between a valley processor and a common memory in a multiprocessor system consisting of four processors. This figure shows the flow of signals. In the figure, 20 is a common bus, 21-
s, 21-t, 21-s, and 21-4 are processors, respectively, and 22 is a common memory.

When each processor attempts to access the common memory 22, it outputs a processor number signal indicating the number of that processor along with a memory address signal onto the common bus. The common memory 22 stores a processor number and a memory address assigned to that processor in association with each other, and compares the processor number and memory address input from the common bus 20 with the stored value, When they match, the data signal of the designated address is read out from the common memory 22 onto the common bus 20 if the operation instructed by the control signal from the processor is a read. When the specified operation is an alarm, the data signal output on the common bus 20 is written to the common bus 22.

In addition, if the result of comparison and verification does not match, an alarm signal indicating an access abnormality is sent from the common memory 22 to the common bus 2.
Output on 0.

FIG. 2 shows an example of the configuration of a processor in an embodiment of the present invention. In the figure, 31 is a processor number output unit, 32 is a processor number setter, and 33 is a processor number output unit.
is a processor.

In FIG. 2, the processor number setter 32 includes, for example, setting pins for the required number of bits, DIP switches, etc.
The processor number can be set by inserting or not inserting a setting pin or turning a DIP switch on or off depending on the number of bits.

Note that setting the processor number is not limited to this method, and it goes without saying that any other method may be used. The processor number output section 31 reads the processor number set in the processor number setter 32 and outputs processor number signals PNu and PNO onto the common bus 20 when the processor 33 accesses the common memory. At the same time, the processor 33 attempts to access the common memory IJ 17) Address signals A15~
AOO is output, and a control signal RD (when ill is output) or WT (when written) is output on the common bus 20 depending on the purpose of access. When the processor access is abnormal and an alarm signal is output from the common memory, the processor 33 receives this via the common bus 20 and stops the access operation.

FIG. 3 shows an example of the common memory address map and processor number assignment in the multiprocessor system shown in FIG. In the figure, (a) shows an example of an address map, with addresses 0000 to IFFF
is an area that is commonly allowed to be accessed by each processor, and addresses 2000 to 3FFF, 4000 to
5FFF, 6000~7FFF.

8000 to 9FFF are processors 21-1.2, respectively.
1-2.

21-a and 21-4 are the only areas to which access is permitted. (b) shows the allocation of processor numbers,
Processor number 21-1.21-x, 21-s
, 21-4, the processor number signal PNI,
PNOs are assigned as shown.

FIG. 4 shows an example of the configuration of a common memory in an embodiment of the present invention. In the figure, 41 is a decoder;
42 and 43 are AND gates, and 44 is a memory element.

In FIG. 4, processor number signals PNI, PNO and upper memory address signals A15 to A13 are input to a decoder 41 via a common bus 20.

As a result, when the access is normal, that is, when the correspondence between the input processor number and the common memory address matches the correspondence between the pre-stored processor number and the common memory address, the decoder 41 performs the following operations:
A memory select signal is output as a read/write gate signal, and when an access error occurs, the correspondence between the input processor number and the common memory address is changed from the correspondence between the pre-stored processor number and the common memory address. If they do not match, an alarm signal ALM is output □Memory select signal is chip select signal C8
This is applied to the memory element 44 as a.

put it into operation. On the other hand, when writing, the write signal W
When T is read, the read signal RD is output on the common bus 20, and when the read/write gate signal is output, the write signal WT or the read signal RD is output to the memory element 44 via the AND gate 42 or 43. is applied, thereby causing the memory element 44 to receive the lower A of the address signal.
At the address specified by 12 to AO, data on the common bus 20 is written or data at that address is read onto the common bus type.

In the embodiments shown in FIGS. 1 to 4, if there is information on the upper memory address signals A15 to A13 and the processor number signals PNI and PNO, access abnormality can be verified. That is, the decoder 41 in FIG. 4 operates as an access abnormality test circuit, and by inputting the above information to the decoder 41,
An access abnormality test is performed, and if there is an access abnormality as a result, the write signal WT or read signal RD is locked by the read/write gate signal to prohibit these operations, and an alarm signal is output to the common bus 20 to notify the processor. may be notified.

5 and 6 show other embodiments of the present invention. FIG. 5 shows a multiprocessor system consisting of four processors and a common memory, in which the common memory access mode of the processors is An example of access when either the read (RD) mode or the write (WT) mode is predetermined is shown. In the same figure,
Addresses 8000 to 8FFF in the common memory 22 are for the processor 21-t.

21-1 is allowed access to Russia, but processor 21-1 only has WT mode access;
1-1 is allowed only RD mode access.

Also, addresses 9000 to 9F in the common memory 22
The FF is allowed access to the processors 21-s and 21-a, but the processor 21-s is not allowed to access the WT.
Mode access only, the processor 21-4 is permitted only RD mode access.

In a multiprocessor system defined in this way,
Since it is determined whether the common memory area that each processor is permitted to access is in the RD mode or the WT mode, it is possible to simplify the test for access abnormalities of the processors.

FIG. 6 shows an example of the configuration of a common memory corresponding to this case, in which the same parts as in FIG. 4 are designated by the same numbers, and jQ and 45.46 are drivers.

In FIG. 6, the decoder 41 includes processor number signals PNI, PNO and the upper A1 of the memory address signal.
2 is input. As a result, the decoder 41 outputs a memory select signal that puts the memory element 44 into an operating state when access is normal, a WT strobe signal during writing, and an RD strobe signal during reading. As a result, the write signal WT is applied to the memory element 44 via the driver 45 during writing, and the read signal RD is applied to the memory element 44 via the driver 46 during bladder removal.
writes or reads data to/from the common node (20).

In the two embodiments described above, the address of the processor is verified by the decoder 41, but such a decoder is generally constituted by a ROM (read only memory), and the required data is written in advance. This can be achieved by However, the means for verifying such an address is not limited to the ROM, and includes means for registering the address to be used and means for comparing and verifying the registered address with the address output from the processor. Figure 7 shows another configuration example of a device for verifying addresses, in which a setting board is used to register addresses to be used, and a comparator is used for verification. 0 In the same figure, 51 is a setting board, which is made up of setting pins or DIP switches, etc., and is used to set the address of the used area in the common memory by inserting or not inserting a pin, or by not inserting a switch, depending on the number of bits. It can be set by turning it on, off, etc. Reference numeral 52 is a controller which compares the address output from the processor with the address set on the setting board 51 and outputs a memory select signal and an RD strobe signal if the address is read when they match. During writing, a memory select signal and a WT strobe signal are output.If they do not match, neither signal is output.

〔Effect of the invention〕

As explained above, according to the method of the present invention, in a multiprocessor system in which a plurality of processors and a common memory are integrated via a common bus, and information is transferred between each processor via the common memory, each processor However, when access is made to an area other than the used area on the common memory defined for each processor, this can be reliably detected and an access abnormality can be notified. Therefore, data written to or read from the common memory can be guaranteed, and system reliability can be improved.

[Brief explanation of drawings]

1 to 4 show one embodiment of the present invention, FIG. 1 is a diagram showing the flow of signals used for data exchange between each processor and a common memory, and FIG. FIG. 3 is a diagram showing an example of the common memory address map and processor number assignment, and FIG. 4 is a diagram showing an example of the common memory configuration. 5 and 6 show other embodiments of the present invention, FIG. 5 is a diagram showing an example of access to the common memory by each processor, and FIG. 6 is a diagram showing an example of the configuration of the common memory. 7 is a diagram showing another example of the configuration of a device for verifying addresses, FIG. 8 is a diagram showing an example of the configuration of a multiprocessor system, FIG. 9 is a diagram showing an example of the configuration of a conventional common memory, and FIG. FIG. 10 is a diagram showing an example of an address map for the common memory. 1-1.1-11.1-11. ......, 1-N:
processor, 2: common bus, 3: common memory, 10:
Bus, 11 Near address decoder, 12: Memory element, 1
3 Near address signal receiver, 14: Parity check circuit, 15: Data signal driver/receiver, 20: Common bus, 21-1°21-s+, 21-s, 21-<:
Processor, 22: Common memory, 31: Processor number output unit, 32: Processor number setter, 33: Processor, 41: Decoder, 42° 43: AND gate,
44: Memory element, 45.46: Driver, 51: Setting board, 52: Comparator. Figure 6 (α) D Figure 4 Common bus 9th Figure 9 Figure 10 Address

Claims (1)

[Claims] In a multiprocessor system in which a plurality of processors and a common memory are connected via a common bus and information is transferred between each processor via the common bus, a memory usage area in the common memory is allocated to each processor in advance, and each processor When accessing the common memory, a number determined for the own processor is output together with the memory address, and in the common memory, information on the input memory address and processor number, and the pre-stored processor number and memory usage area for each processor are output. 1. A method for testing an abnormality in access to an out-of-area memory, the method comprising: comparing and collating information on the processor and detecting an access abnormality in the processor when the information does not match.