JPS61180480A - Bipolar hetero junction transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar heterojunction transistor consisting of layers forming an emitter, a base and a collector, the heterojunction being an emitter-base junction.

[Conventional technology and problems]

These bipolar
Heterojunction transistor is FR-A-2352404
A heterojunction is formed between AlGaAs and GaAs using the m-■ technique with AlGaAs having a band gap of 2.3 eV.

This epitaxial technique is not only difficult to control, but also extremely expensive.

Furthermore, bipolar transistors whose emitter-base junctions are made of polycrystalline and single-crystalline silicon are known. In this technique, doping with impurities causes diffusion at high temperatures from the polycrystalline layer forming part of the emitter into the monocrystalline base, resulting in an unspecified junction between emitter and base. The explanation for the increase in data is not certain or this point may be in terms of a low diffusion coefficient of fewer carriers in the polycrystalline part of the emitter or the presence of a thin oxide between the polycrystalline and monocrystalline layers or both layers. Explained in terms of combinations.

Another technique in silicon technology for manufacturing bipolar heterojunction transistors is the 5iPs method (e.g. FR-A-
2309981), where the layer forming the emitter is 02-5iHa-N at about 650°C to obtain a phosphorous-doped 5i-SiOz-polycrystalline structure.
Made with zO-PHZ steam. Subsequently, in order to reduce the density of states at the joint surface, the material was heated to 9
Annealed at a temperature of 00℃, then the emitter layer becomes 1
．． It exhibits an energy gap of 5 eV. The disadvantage of this technique is that phosphorus diffuses into the base layer due to the annealing at high temperatures, and the precision of the transition between the energy gap in the emitter layer and the energy gap in the base layer is not well defined. The point is that it disturbs the emitter-base junction defined by . Furthermore, such transistors have a high emitter abrasion value due to the separate SiO□.

[Means for solving problems]

The main object of the present invention is to provide bipolar heterojunction silicon with a high band gap in the emitter, which means a high gain without loading at the heterojunction, which means that it is simple and extremely cheap to manufacture. The goal is to provide transistors.

This transistor is therefore characterized in that the layer forming the emitter essentially consists of a doped and hydrogenated semiconductor material at least partially in amorphous form.

A high current gain is obtained in this application because the carrier injection of a small amount of carriers into the emitter is increased due to the pan-Y gap in the layer of emitter material. or,
Due to the hand gearing of this layer, the inherent carrier concentration M in the emitter is reduced.

This transistor is extremely amenable to high frequency applications and is used in all kinds of high speed digital r
Like c, it can be used with any semiconductor technology such as a differential amplifier or an operational amplifier.

Typical examples of particles from fully amorphous hydrogenated silicon (α-5izH) on microcrystalline silicon (μc-Si) consisting of small crystals embedded in an amorphous matrix with typical average dimensions of 2 to 1100 nm. The target range is particles having an average size of 2 to 1100 nm and a continuous structure of grain boundaries in a partially amorphous state. In both cases the hydrogen content within the material is essential, and the band gap is large or (as is the case with poly-Si with particles larger than 100 nm) the crystalline 5i (c-St) band.・It is equal to the gap. The higher the production or annealing temperature of the silicon, the more the crystals provided in the final polycrystalline silicon are generally recognized as a continuous structure of grains with grain boundaries having typical dimensions of at least 1100 nm. The number and/or size of bodies increases. The resistance value of the layer forming the emitter is approximately between 1 and 1000 Ωcm in the case of a completely amorphous layer, and decreases to 10 −3 Ωcm in the case of μc-Si.

Doped amorphous silicon and hydrogenated silicon are known for the production of solar cells. For example β
US-A- with other requirements other than transistors
See 4457538.

In a preferred embodiment of the invention, typical dimensions range from 2 to
Polycrystalline silicon (μc-3
i) and formed in an amorphous matrix. The higher the manufacturing temperature of silicon, the higher the density of the crystals, and finally a so-called polycrystalline state is obtained without any remaining amorphous silicon, but in general polycrystalline semiconductor materials contain more crystals. have. This polycrystalline emitter has a low resistance value, making the transistor extremely useful as a power transistor at high currents and frequencies.

For the production of solar cells only, e.g. US-A-435
7179 and T, Ichimura's Extended Abs
tracsoo-volume 21, 1980 paper ``α-3i:H films by rDC glow discharge'' and G, Radiuswaran, December 1983 (NY, US) Appl.
Microcrystalline silicon is known from the paper ``Temperature dependence of base material on microcrystals of plasma-deposited boron-doped, hydrogenated silicon alloys'' in IED Physics Report, Volume 23, No. 11. The application example has nothing to do with the transistor according to the invention.

The resistance value of the layer forming the emitter is approximately 1 to 10 Ωcm.
Or, in the case of μc-3i, it becomes 10 −3 Ωcm.

In a preferred embodiment of the transistor according to the invention, the layer forming the emitter has a thickness of 0.5- or less,
This is made possible by the well-defined beterojunction between amorphous silicon and single crystal. This thin base layer results in low base resistance, which is essential for high frequency transistors.

Furthermore, the invention provides a method of manufacturing a transistor according to the invention.

In the known traditional technique for manufacturing the layers forming the emitter of homogeneous junction transistors, phosphorous is heated to about 900°C.
It is either diffused into a single crystal silicon (c-Si) chip or doped by ion implantation.

In order to obtain a high collector current I, the emitter-forming layer must be doped to a high donor density N4, for example 3.1020 atoms/cm3. The value of the base current is approximately 1,1
It is determined by the energy gear of the emitter forming layer in single crystal silicon at eV.

A disadvantage of this known method is that due to the strong doping, the energy gap in the emitter-forming layer decreases to about 0.9 eV, so that the base current increases and the factor β is negatively influenced. Due to the small energy gap, a relatively high small current flows in the emitter. Moreover, it is disadvantageous to choose a base-forming layer thinner than 0.5 - because of the large value of the base resistance and the small value of the voltage drop at the base.

According to the invention, the method comprises applying four layers on the layer forming the base.
The emitter-forming layer is applied by means of a plasma consisting of ionic, radical and neutral parts of the semiconductor material and hydrogen at a temperature of up to 50° C., so that the emitter-forming layer is substantially at least partially doped in an amorphous state. Moreover, it is characterized in that it is made of a hydrogenated semiconductor material.

Since plasma is used, the temperature of the substrate can be kept low (
5450°C), which generates the film-attached particles from the gas phase and thus determines the growth rate, while independently the substrate temperature determines the hydrogen content as explained earlier between the two electrodes. This is because of the practical power of The amorphous layer can also be formed using special (7) LP GVD (low pressure chemical vapor deposition) techniques (HOMOCVD).

It can also be deposited by other techniques known per se, such as PH0T CVD, LASER CVD, etc. and sputtering, etc., but the substrate temperature can always be kept low so that it does not dictate the growth rate, creating a high band gap in the emitter. It will be appreciated that it only determines the content of hydrogen in the resulting coating.

Preferably, hydrogen (H2) is added to the plasma at a relatively high partial pressure so that the layer forming the emitter consists essentially of doped and hydrogenated semiconductor material in microcrystalline form.

By adding H2 to the plasma, the deposition rate can be controlled, while the temperature of the substrate, T, controls the amount of hydrogen in the layer, so that the microcrystals depend on the equilibrium between growth rate and deposition rate. It can be formed by itself in the following dimensions.

〔Example〕

Other features and characteristics of the invention will be described below with reference to the drawings.

npn) Run Sister 1 (first
7 and 8), the emitter layer 2 is provided with an emitter contact 5 consisting of phosphorus-doped and hydrogenated silicon in amorphous or microcrystalline form, and the base contact 7 is provided with monocrystalline silicon. by an acceptor doped base layer 3 consisting of and a collector contact 6
It is formed by a donor-doped collector layer 4 of single-crystal silicon with a . The thickness D (Fig. 8) is, for example, only two to three tenths of the thickness of the lake. The current amplification coefficient β is defined as follows.

μm IP where 18 is the absolute value of the electron flow from the emitter to the collector, I, is the value of the hole current from the base to the emitter, and IC is the value of the collector current. The second = sign applies only when the base recombination value can be ignored and the recombination between amorphous (or microcrystalline) and single crystal materials and at the junction can be ignored.

The emitter layer of the transistor embodying the invention comprises at least one silicon chip 15 comprising a collector layer and a base layer and containing silane iI as a precursor.
! (SiH4) or AsH3 and phosphine (PH3)
, (SiHt) was maintained at a temperature of about 250° C. and equipped with a pressure gauge 9 and a cock 1.
Inlet channel 10 and outlet channel 1 containing 2.13
1 and a removable cover 14. By using an alternating current voltage source with a preset power value or optionally a direct current voltage source 16, the electrode 17. A plasma is generated during 18. The substrate temperature determines the amount of hydrogen remaining within the amorphous silicon emitter layer;
For example, for 150°C, the amount of hydrogen remaining in the membrane is typically 5-10%.

Due to the amount of gaseous mixture, the immersion at high temperatures required for example in the 5IPOS method can be eliminated. Electrode 18 is connected to ground. Electrode 17 is also connected to ground and to a voltage source.

Since plasma is used, temperatures can be kept low. The silicon chips are arranged either vertically (indicated by solid line 15) or horizontally (indicated by dashed line 15'). The layers forming the base and collector are applied by methods known per se.

Ti (0,5 lakes) - AI (1-
) was deposited on the ground silicon and on the layer forming the base. To further improve the contact annealing at 290℃
It is held for 5 minutes. As in the case of the 5IPOS method, high temperature annealing can be omitted since the emitter layer is already hydrogenated during plasma formation.

In order to produce an emitter layer in microcrystalline form, i.e. an amorphous matrix node with very small crystalline regions inside, the method is used in a chamber 8 at a pressure of about 50 mTorr, and a voltage source is applied to the amorphous plasma. - Provided a power value smaller than the value when manufacturing a single emitter layer. The exact pressure value and the exact power value must be determined depending on the dimensions of the chamber.

The transition between the energy gap 19 in the phosphorus-doped N layer and the energy gap 20 in the slightly doped P layer is illustrated in FIG. 3, which also shows the doping profile. The energy gap 19 is, for example, 1.6e
V, and the energy gap 20 is, for example, 1.1e
It is V. The solid line shows the doping profile at the npn junction (emitter-base) of a transistor embodying the invention. The dashed lines 21, 22 represent the doping profile according to known techniques such as the diffusion technique and the S I PO3 method which provides an emitter layer, where due to the high temperature the donor material (phosphorous) can diffuse into the base layer. The dashed line 21 shows, by way of example, the doping profile in a 5 IPOS transistor that is soaked for a short period of time. The dashed line 21 shows, by way of example, the doping profile in the transistor by diffusion technology. Because of the precisely defined emitter-base junction in the transistor embodying the invention, the thickness of the base layer can be selected to be smaller than that of transistors used to date, for example 0.5-, so that the collector Achieving a current I6 and therefore a high β. For a given β value, a low value of the base resistance is thus obtained.

Lines 24, 25, 26, 27, 28, 29, 30, 31 are collectors represented by bolts plotted on the coordinates.
10 μA, 20 μA, respectively, associated with the emitter voltage VC,
8, 30μA, 200μA, 400μA,
The collector current rC at 0 μA (FIG. 4) and mA (FIG. 5) is shown for a transistor employing the present invention using α-3i:H at constant base currents I8 of 600 μA, 800 μA, and 1 mA.

In FIG. 6, the current amplification factor β is plotted perpendicularly to the base-Gammel number.

The base Gummel number is defined as the density per unit area and the diffusion coefficient of the smallest charge carrier within the base layer. Electronic flow! , and thus the β factor is inversely proportional to the base Gummel number. The solid line (FIG. 6) shows the relationship for a bipolar homogeneous junction transistor. Figure 6 shows α-Si
:H shows measurement points on a transistor embodying the invention. Heterojunction transistors have a high base-Gummel number, approximately 5 to 6 times greater than the beta factor, making heterojunction transistors embodying the present invention more effective than conventional bipolar homogeneous junction transistors. It also exhibits a high current amplification factor β at low values of the base-Gammel number.

The bipolar heterojunction transistor of the present invention is 45
Si, which is known per se, together with the gas in the room that exists at 0°C
It will be understood that it can be produced by photodissociation of H.

A bipolar heterojunction transistor according to the invention can be fabricated by chemical vapor deposition (CVD) while the substrate with the base layer is also cooled at about 300°C.

By heating a transistor with an amorphous emitter layer from about 550° C. to about 750° C., a transistor with a microcrystalline emitter layer can be obtained. In FIG. 9, line 42 shows a transistor of α-Si into μc-Si, line 42 shows the resistivity of the material as a function of temperature due to annealing for 20 minutes, and region 31 is amorphous silicon. , region 43 is microcrystalline silicon.

It will be appreciated by those skilled in the art that there are no limitations to the use of the bipolar heterojunction transistor of the present invention. The invention can be used as a power transistor, and for high frequency purposes even sub-micron in analog or digital IC technology.

The combination of low base resistance and high current gain enabled by the present invention provides engineers with a high degree of freedom in designing transistors suitable for high frequency and power applications. Also, due to the high band gap in the emitter, no charge is generated at the junction, so that the transistor according to the invention is also suitable for high frequency purposes.

Applications of such transistors include, for example, computers, main frames ((super)mini), curve tracers, oscilloscopes, operational amplifiers (audio, video, etc.), high speed memories, microwaves, etc.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a bipolar peterojunction npnl-run sister embodying the invention. FIG. 2 is a schematic cross-sectional view of an apparatus for carrying out the method according to the invention. FIG. 3 schematically shows the energy gap transition at the emitter-base junction of the transistor of FIG. FIG. 4 is a graph of a low current value state of an npn transistor embodying the present invention. FIG. 5 is a diagram showing a high current value state of an npn (npn) run sister embodying the present invention. FIG. 6 is a graph of the current amplification factor β of the transistor of FIG. 1 plotted against the base-Gummel number GG. FIG. 7 is a significantly enlarged plan view of the bipolar heterojunction transistor of FIG. FIG. 8 is a sectional view taken along ■-■ in FIG. 7. FIG. 9 is a graph showing the transition from amorphous to μc-Si. 1: npn t-run sister 2: emitter layer 3 near acceptor doped base layer 4: donor doped collector layer 5: emitter contact 6: collector contact 7: base contact 8: chamber 9: pressure gauge 10: inlet channel 11: Exit channel 12. 13: Cock 14: Removable cover 15, 15°: Silicon chip 16: DC voltage source 17. 18: Electrode 19. 20: Energy gap 21. 22 Ni-doping profile 24-26 : Collector current 41: Amorphous silicon 42 Nidoran sister (α-5i, μc-5i) 43
: Microcrystalline silicon ■, Bibase current ■, : Hole current value IN: Absolute value of electron flow ■c: Collector current value VCE: Collector-emitter voltage β: Current amplification coefficient GG Bibase-Gummel number D: Thickness Applicant's agent Kaoru Furuya Takahiko Mizobe Satoshi Furuya FJG, 8 FIG, 9

Claims (1)

[Scope of Claims] 1 A bipolar heterojunction transistor (1) consisting of layers (2, 3, 4) forming an emitter, a base and a collector, respectively, the layers forming an emitter (
A bipolar heterojunction transistor (1) characterized in that 2) consists essentially of a doped and hydrogenated semiconductor material at least partially in amorphous form.
). 2. Bipolar heterojunction transistor (1) according to claim 1, characterized in that the layer (2) forming the emitter consists essentially of phosphorus-doped microcrystalline silicon. 3. A bipolar heterojunction transistor (1) according to claim 1 or 2, characterized in that the layer (3) forming the base has a thickness of 0.5 μm or less. 4. The emitter-forming layer (2) consists of a doped and hydrogenated semiconductor material in an at least partially amorphous state, such that the emitter-forming layer (2) consists of a semiconductor material, hydrogen ions, groups and Bipolar according to claim 1, 2 or 3, characterized in that the layer (3) forming the base is applied at a temperature of up to 450° C. by a plasma consisting of a neutral part. - A method of manufacturing a heterojunction transistor (1). 5 characterized in that hydrogen (H_2) is added to the plasma at a relatively high partial pressure so that the layer (5) forming the emitter essentially consists of a doped and hydrogenated semiconductor material in microcrystalline form. The manufacturing method according to claim 4. 6. The manufacturing method according to claim 4 or 5, wherein the plasma is substantially made of silanes (SiH_4) and phosphine (PH_3). 7. The manufacturing method according to claim 4, 5 or 6, characterized in that the layer forming the base is provided with a thickness of 0.5 μm or less. 8 The layer (2) forming the emitter is formed by chemical vapor deposition (CVD).
), characterized in that the layers (3, 4 each) forming the base and the collector are cooled relative to the hot steam at temperatures up to 450°C, A method for manufacturing the bipolar heterojunction transistor (1) according to items 2 and 3. 9. Manufacturing a bipolar heterojunction transistor (1) according to claim 1, 2 or 3, characterized in that hydrogen (H_2) is added to the plasma at a relatively high partial pressure. Method. 10. Claim 2 or 3, characterized in that the amorphous layer (2) forming the emitter is heated from about 550°C to 750°C so as to become substantially microcrystalline.
A method of manufacturing a bipolar heterojunction transistor as described in . 11. Claims 4 to 10 characterized by a passive cycle before application of the layer (2) forming the emitter
The method described in any of the sections. 12. Process according to any one of claims 6 to 10, characterized by a relatively low pressure of 12 SiH_4. 13 Set the relative partial pressure of SiH_4 to H_2 to 0.1
The method according to claim 13, characterized in that: 14. Claims: A diode using a heterojunction according to each of the above claims.