JPS6118042A - Reference system of instruction address register - Google Patents

Abstract

PURPOSE:To give an allocated absolute address to a program which is under execution by reading an instruction address through an address latch circuit and an address latch circuit. CONSTITUTION:A CPU1 delivers an address to a memory 8 via an address bus 6, and the memory 8 delivers an instruction code via a data bus 7. The CPU1 executes sequentially the instruction code. While an address latch circuit 2 receives an instruction fetch signal from the CPU1 and then latches an instruction adress on the bus 6. At the same time, an address decoder 3 sends a latch address output signal 5 to the circuit 2 while an I/O port input instruction is executed. The circuit 2 receives the signal 5 and delivers the latched instruction address to the bus 7. The CPU1 can give an absolute address allocated to a program during program execution by fetching the instruction address put on the bus 7.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a processing device C equipped with a central processing unit (hereinafter abbreviated as aU) that has instruction code fetch timing as an external output signal; In order for the program itself to be able to refer to the address allocated by the program, C
This relates to a method of referencing an instruction address register that holds a program execution address within a PU.

[Conventional technology]

In a processing device equipped with a CPU, the program itself may need to know the address to which the program is assigned. For example, when performing processing to initialize the contents of a random access memory (hereinafter abbreviated as RAM) that constitutes the main storage device, the program executed by the processing device must not be initialized. Therefore, it is necessary to know the address allocated to the program, and for this reason (the second is C
It is necessary to refer to the instruction address register that holds the program execution address in the PU so that the address can be successively retrieved.

Conventionally, this type of instruction address register reference method has been to indirectly (
= There is a method to obtain the contents of the instruction address register. In this method, after calling a subroutine, the contents of the memory indicated by the stack pointer are read into @CPU. The contents of the memory indicated by the stack pointer match the contents of the instruction address register when returning from the subroutine, so by reading this into @CPU, the CPU can know the contents of the instruction address register. In this way, in the conventional instruction address register referencing method, the contents of the instruction address register are indirectly known from the return address saved in the stack area. Therefore, it takes several steps of execution of the instruction code to obtain the contents of the instruction address register. Requiring C: To become.

[Problem that the invention seeks to solve]

The instruction address register reference method of the present invention is intended to solve the problems of the prior art, and is capable of giving an absolute address assigned to the program itself to the program while the program is being executed. This is what we are trying to do.

[Means for solving problems]

The instruction address register reference method of the present invention is a C
A processing device equipped with a PU is provided with means for latching a signal on an address bus using this external output signal, and means for reading out the address latched by this latch means to the CPU.

[Effect]

According to the instruction address register reference method of the present invention, CP
By latching and reading the signal on the address bus using the fetch timing signal of U, the CPU can read the instruction address, thus giving the program the absolute address assigned to the program during program execution. I can do it.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the instruction address register referencing method of the present invention. In the same figure, 1 is CP
U, 2 is an address latch circuit, 6 is an address decoder,
4 is an instruction fetch signal, 5 is a latch address output signal,
6 is an address bus, 7 is a data bus, and 8 is a memory.

Further, FIG. 2 is a diagram showing the timing of various signals in the instruction fetch cycle in the embodiment shown in FIG. 1.

The CPU 1 outputs an address to the memory 8 via the address bus 6, and the memory 8 outputs an address to the data bus 7 in response.
The CPU 1 outputs instruction codes through the CPU 1 and sequentially executes the instruction codes. Address latch circuit 2 latches the instruction address on address bus 6 when receiving instruction fetch signal 4 output from cpvl. Next, address decoder 3 outputs latch address output signal 5 at the time of I10 port input input command. Address latch circuit 2 outputs the latched instruction address to data bus 7 when a latch address output signal is input manually. CPU1
By taking in the instruction address on the data bus 7, the absolute address assigned to the program can be given to the program while the program is being executed.

According to the present invention, since the absolute address assigned to the program itself can be acquired during the execution of the program by the above procedure (2), it is possible to construct a completely relocatable program including the work area.

〔Effect of the invention〕

As explained above, according to the instruction address register reference method of the present invention, the CPU can read the instruction address via the address latch circuit, so that the CPU can read the absolute address assigned to the program during program execution. can be given to

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the instruction address register referencing method of the present invention, and FIG. 2 is a diagram showing the timing of an instruction write cycle. 1...CPU, 2...Address latch circuit, 3...
・Address decoder, 4...Instruction fetch signal, 5.
...Latch address output signal, 6...Address bus,
7...Data bus, 8...Memory

Claims (1)

[Claims] In a processing device equipped with a central processing unit that is provided with the instruction code fetch timing as an external output signal and retrieves and executes the instruction code on the memory via an address bus and a data bus, the address on the address bus is determined by the external signal. 1. An instruction address register reference system comprising: means for latching the latched address; and means for reading the latched address and providing it to a central processing unit via a data bus.