JPS61179551A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a wiring having low resistance simultaneously while using a high heat-resistant metal as a gate electrode by forming a desired photo-resist pattern, dry-etching a low-resistance metallic material, a dielectric film and a high-resistance high heat-resistant gate material in succession while employing the photo-resist pattern as a mask and shaping the gate electrode and the wiring onto a wafer. CONSTITUTION:A conductive layer 12 for forming a GaAs MESFET is shaped into a desired region in a semi-insulating GaAs substrate 11, and a tungsten silicide 13 having the composition of W5Si3 is applied onto the whole surface of a wafer. A region as a gate electrode and an SiO2 film 14 in the vicinity of the region are formed. Ti-Au are evaporated onto the whole surface in succession. A photo-resist pattern 16 for shaping the gate electrode and a wiring is formed, Ti and Au are etched through an ion milling method and SiO2 and W5Si3 through a reactive ion etching method, and SiO2 is further removed through etching, thus also lifting off Ti-Au on SiO2, then forming the gate electrode 17 and the W5Si3 wiring 18 as a wiring in which the upper section of W5Si3 is coated with Ti-Au having low resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with reduced wiring resistance.

Heat-resistant metals are sometimes used as gate electrode materials for reasons of safety or for the introduction of various self-alignment technologies. The problem with this is that heat-resistant metals generally have a high specific resistance.

Therefore, if the gate material is used as it is as the first layer wiring, the characteristics of a semiconductor device, such as a digital integrated circuit, where the wiring resistance is not extremely high will be impaired. For example, if WsS i is used as the gate material, the specific resistance is about 200 μΩ·flaw, and when considering a wiring having a thickness of 0.5 μm, a width of 2 μm, and a length of 1 ff, the wiring resistance becomes about 2Ω.

According to the inventor's study, the wiring resistance of IH is 200Ω.
Although it is necessary to keep the amount of noise below a certain level, it is understood that it is extremely inconvenient to use the gate material as it is as the first layer wiring material. One possible way to avoid this inconvenience is to layer a low-resistance metal on the heat-resistant gate electrode.
In this case, the low-resistance metal in the upper layer diffuses through the heat-resistant gate metal and reaches the semiconductor surface, severely impairing the reliability of the gate electrode. In order to prevent this, it is necessary not to overlap a low-resistance metal on at least the surface of the gate metal, or to insert a material with a high ability to prevent diffusion, such as a conductive □ body, even if it is overlapped. Based on this idea, conventionally, a method as shown in FIG. 2 has been adopted, that is, a method in which a gate electrode 21 and a wiring 22 are formed separately, and each is connected by a second layer wiring 24 via an interlayer insulating film 23. It has been.

However, with this method, it is necessary to form through-hole contacts, and a certain area on the glabella insulating film is occupied only for connecting the first layer wiring, which gives rise to the freedom of wiring for other signal paths. The disadvantage was that it reduced the It is also conceivable to layer only the wiring portion with a low-resistance metal later, but in this case, since an overlapping margin is required, it is impossible to reduce the actual wiring width.

(Object of the present invention) The present invention has been made in view of the above-mentioned drawbacks in the conventional semiconductor device manufacturing method. An object of the present invention is to provide a completely new manufacturing method for semiconductor devices that can simultaneously realize the following.

(Structure of the Invention) According to the present invention, there are a step of depositing a high heat-resistant gate material over the entire surface of the wafer, a step of covering the gate electrode and its vicinity with a dielectric film, and a step of covering the entire surface with a low-resistance metal material. Gate electrodes and wiring are formed on the wafer by forming a desired photoresist pattern and dry-etching the low-resistance metal material, dielectric film, and high-resistance, high-heat-resistant gate material in sequence using the photoresist pattern as a mask. There is provided a method for manufacturing a semiconductor device characterized by including a step of forming a semiconductor device.

(Example) Next, the present invention will be explained in detail using FIG.

This example takes a method for manufacturing a gallium arsenide (GaAs) integrated circuit as an example, and in this example, a method for manufacturing a gallium arsenide (GaAs) integrated circuit is used.
The explanation will focus on the formation of wiring from the MESFET (MESFET) and its gate electrode.

First, in FIG. 1(2), a conductive layer 12 for forming a GaAs MESFET is formed in a desired region of a semi-insulating GaA substrate 11 by ion implantation or the like. Next, in () of the same figure, a kite s i is applied to the entire surface of the wafer.

Tungsten silicide 13 having a composition of 500 OA is deposited by co-sputtering, for example. Next, C)
In this case, S is applied to the region to be used as the gate electrode and its vicinity.
A film 14 of xO (thickness: 100 OA) is formed. In practice, it is sufficient to deposit SxO on the entire surface and etch away the S10° film in areas other than the desired areas using phosphorography. At this time, the area covered with St is not strictly limited to the area that should become the gate electrode, but is several μm thick.
There is no problem even if the degree is outside that range.

Next, Ti-Au was sequentially applied to the entire surface at 500A and 2000A15.
Deposit (Fig. 1D). Next, a photoresist pattern 16 for forming gate electrodes and wiring is formed.
(see plan view), T I and A u were etched by the ion scilling method, s to, , w, and s l were etched by the reactive ion etching method, and the above-mentioned St.

For example, if you remove it by etching with HF, the TiA on it
As shown in FIG. 1F, the gate electrode 1 is
7 is made of W, S s , and the wiring 18 is made of Wl S l , on which a wiring with low resistance TiAu is formed.

This completes the process according to the present invention. After that, for example, high-dose Sl+ is ion-implanted using the W, Si, or film as a mask, and then annealing is performed to form ten Kn layers on both sides of the silicate electrode 17. Is possible. At this time, since only a highly heat-resistant material is used for the gate electrode, it does not react with %GaAg. In addition, the wiring part is W,
When TiAu is deposited on S s , W may diffuse into S s during annealing, but this does not pose any problem in practice. A portion of the semiconductor device realized through the above steps is shown in a perspective view in FIG. In FIG. 3, 31 and 32 are source and drain electrodes, respectively.

In the above example, the SxO film was removed, but the SxO film was removed.
Since the xO film itself has a strong diffusion inhibiting ability against TlAu K, there is no problem if the film is left as is without being removed. It goes without saying that the low resistance metal is not limited to Ti-Au, and any low resistance materials such as AL, W, and Mo can be used.

Further, as a semiconductor device, it is applicable to a device such as a Si MOS transistor.

(Effects of the Present Invention) According to the present invention, it is possible to realize low resistance and fine wiring regardless of the resistance of the gate electrode material, so that it is possible to manufacture a semiconductor device with good productivity and high performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention! 6A). B), C), D), F) are cross-sectional views, E) are plan views, 2nd
The figure is a sectional view explaining the prior art, and FIG. 3 is a perspective view showing an example of a semiconductor device obtained by the present invention.
GaAs substrate, 12-・Conductive layer, 13-・W, Si
,, 14- SIO, film, 15- TiAu film, 1
6--Photoresist pattern, 17.21-Gate electrode, 18.22--Wiring, 31--Source electrode, 32
-Drain electrode. Ding ``PeT, 7., .1.! 2': In, - Yutang 1 Figure 1

Claims (1)

[Claims] A process of depositing a high heat-resistant gate material on the entire surface of the wafer, a process of covering the area to be used as the gate electrode and its vicinity with a dielectric film, a process of depositing a low-resistance metal on the entire surface, and a process of coating the entire surface of the wafer with a gate electrode. Form a desired photoresist pattern to form wiring, and use it as a mask to selectively remove the low-resistance metal film, dielectric film, and high heat-resistant gate material to form gate electrodes and wiring on the wafer. A method for manufacturing a semiconductor device, characterized in that: