JPS6117890U - Inverter control device - Google Patents
Inverter control deviceInfo
- Publication number
- JPS6117890U JPS6117890U JP10121784U JP10121784U JPS6117890U JP S6117890 U JPS6117890 U JP S6117890U JP 10121784 U JP10121784 U JP 10121784U JP 10121784 U JP10121784 U JP 10121784U JP S6117890 U JPS6117890 U JP S6117890U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- control device
- outputs
- inverter control
- synchronous circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Protection Of Static Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案のインバータ制御装置の一実施例を示
す回路図、第２図は第１図の回路の要部の出力波形図、
第３図は従来例を示す回路図、第４図は第３図の回路の
要部の波形図である。
１１・・・・・・同期回路、１２・・・・・・エッヂ検
出回路、１３・・・・・・タイマ、１４，１５・・・・
・・アンドゲート。Fig. 1 is a circuit diagram showing an embodiment of the inverter control device of this invention, Fig. 2 is an output waveform diagram of the main part of the circuit shown in Fig. 1,
FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a waveform diagram of a main part of the circuit shown in FIG. 11... Synchronous circuit, 12... Edge detection circuit, 13... Timer, 14, 15...
...and gate.
Claims (1)
により交流を出力するインバータにおいて、アーム駆動
信号をクロックパルスに同期させた第１信号とその反転
信号である第２信号を出力する同期回路と、クロツクパ
ルスで駆動され同期回路の出力変化時に所定時間を計時
するタイマと、タイマの出力と同期回路の第１信号を受
けて、上アーム駆動信号を出力する第１のゲート回路と
、上記タイマ出力と同期回路の第２信号とを受けて、第
１信号の立上りよりも早く立ち上り、第１信号の立ち上
りよりもおそく立ち上る下アーム駆動信号を出力する第
２のゲート回路とを備えたことを特徴とするインバータ
の制御装置。an inverter that outputs alternating current by alternately turning on and off upper and lower arm transistors; a timer that is driven by a clock pulse and measures a predetermined time when the output of the synchronous circuit changes; a first gate circuit that receives the output of the timer and the first signal of the synchronous circuit and outputs an upper arm drive signal; and a second gate circuit that receives the second signal of the synchronous circuit and outputs a lower arm drive signal that rises earlier than the rise of the first signal and rises later than the rise of the first signal. Inverter control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10121784U JPS6117890U (en) | 1984-07-03 | 1984-07-03 | Inverter control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10121784U JPS6117890U (en) | 1984-07-03 | 1984-07-03 | Inverter control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6117890U true JPS6117890U (en) | 1986-02-01 |
Family
ID=30660658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10121784U Pending JPS6117890U (en) | 1984-07-03 | 1984-07-03 | Inverter control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6117890U (en) |
-
1984
- 1984-07-03 JP JP10121784U patent/JPS6117890U/en active Pending
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