JPS61176814U - - Google Patents
Info
- Publication number
- JPS61176814U JPS61176814U JP5759185U JP5759185U JPS61176814U JP S61176814 U JPS61176814 U JP S61176814U JP 5759185 U JP5759185 U JP 5759185U JP 5759185 U JP5759185 U JP 5759185U JP S61176814 U JPS61176814 U JP S61176814U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- transistors
- pair
- current
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の交流増幅回路の一実施例を示
す略図、第２図は本考案の交流増幅回路を説明す
るための回路図、第３図は本考案における入力コ
ンデンサに印加される電圧レベル図、第４図は本
考案の交流増幅回路の応用例であるモータの速度
制御回路を示すブロツク系統図、第５図は一般的
な演算増幅回路を示す図、第６図は従来の交流増
幅回路を示す略図、第７図は従来例における入力
コンデンサに印加される電圧レベル図である。
８，９……入力端子、１０……出力端子、１１
……電源ライン、Ｃ２……入力コンデンサ、Ｒ２
……抵抗、Ｓ２……信号源、Ｑ１〜Ｑ５……トラ
ンジスタ。
Figure 1 is a schematic diagram showing an embodiment of the AC amplifier circuit of the present invention, Figure 2 is a circuit diagram for explaining the AC amplifier circuit of the present invention, and Figure 3 is the voltage applied to the input capacitor of the present invention. Figure 4 is a block system diagram showing a motor speed control circuit which is an application example of the AC amplifier circuit of the present invention, Figure 5 is a diagram showing a general operational amplifier circuit, and Figure 6 is a diagram showing a conventional AC amplifier circuit. FIG. 7, which is a schematic diagram showing an amplifier circuit, is a voltage level diagram applied to an input capacitor in a conventional example. 8, 9...Input terminal, 10...Output terminal, 11
...Power line, C2 ...Input capacitor, R2
...Resistor, S2 ...Signal source, Q1 to Q5 ...Transistor.
Claims (1)
カレントミラー回路を有し、この差動増幅回路の
対をなしているトランジスタおよび前記カレント
ミラー回路の対をなしているトランジスタの内、
少なくとも一方のトランジスタをコレクタ分割し
、コレクタ電流の内、所定の電流を接地電位に流
すようにして、入力オフセツト電圧が常に一定極
性になるようにしたことを特徴とする交流増幅回
路。 It has a differential amplifier circuit and a current mirror circuit having a pair of transistors, and among the transistors forming the pair of the differential amplifier circuit and the transistors forming the pair of the current mirror circuit,
An AC amplifier circuit characterized in that at least one of the transistors is divided into a collector and a predetermined current of the collector current is made to flow to a ground potential so that an input offset voltage always has a constant polarity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5759185U JPS61176814U (en) | 1985-04-19 | 1985-04-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5759185U JPS61176814U (en) | 1985-04-19 | 1985-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61176814U true JPS61176814U (en) | 1986-11-05 |
Family
ID=30582264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5759185U Pending JPS61176814U (en) | 1985-04-19 | 1985-04-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61176814U (en) |
-
1985
- 1985-04-19 JP JP5759185U patent/JPS61176814U/ja active Pending
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