JPS61176813U - - Google Patents
Info
- Publication number
- JPS61176813U JPS61176813U JP5758585U JP5758585U JPS61176813U JP S61176813 U JPS61176813 U JP S61176813U JP 5758585 U JP5758585 U JP 5758585U JP 5758585 U JP5758585 U JP 5758585U JP S61176813 U JPS61176813 U JP S61176813U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- pair
- emitter area
- effective emitter
- current mirror
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第1図は本考案の交流増幅回路の一実施例を示
す略図、第2図は本考案の交流増幅回路を説明す
るための回路図、第3図は本考案における入力コ
ンデンサに印加される電圧レベル図、第4図は本
考案の交流増幅回路の応用例であるモータの速度
制御回路を示すブロツク系統図、第5図は一般的
な演算増幅回路を示す図、第6図は従来の交流増
幅回路を示す略図、第7図は従来例における入力
コンデンサに印加される電圧レベル図である。
8,9……入力端子、10……出力端子、11
……電源ライン、C2……入力コンデンサ、R2
……抵抗、S2……信号源、Q1〜Q5……トラ
ンジスタ。
Figure 1 is a schematic diagram showing an embodiment of the AC amplifier circuit of the present invention, Figure 2 is a circuit diagram for explaining the AC amplifier circuit of the present invention, and Figure 3 is the voltage applied to the input capacitor of the present invention. Figure 4 is a block system diagram showing a motor speed control circuit which is an application example of the AC amplifier circuit of the present invention, Figure 5 is a diagram showing a general operational amplifier circuit, and Figure 6 is a diagram showing a conventional AC amplifier circuit. FIG. 7, which is a schematic diagram showing an amplifier circuit, is a voltage level diagram applied to an input capacitor in a conventional example. 8, 9...Input terminal, 10...Output terminal, 11
...Power line, C2 ...Input capacitor, R2
...Resistor, S2 ...Signal source, Q1 to Q5 ...Transistor.
Claims (1)
カレントミラー回路を有し、この差動増幅回路の
対をなしているトランジスタの有効エミツタ面積
比および前記カレントミラー回路の対をなしてい
るトランジスタの有効エミツタ面積比の内、少な
くとも一方の有効エミツタ面積比を所定比以上に
して、入力オフセツト電圧が常に一定極性になる
ようにしたことを特徴とする交流増幅回路。 It has a differential amplifier circuit and a current mirror circuit having a pair of transistors, and the effective emitter area ratio of the transistors forming the pair of the differential amplifier circuit and the effective emitter area of the transistors forming the pair of the current mirror circuit. An AC amplifier circuit characterized in that an effective emitter area ratio of at least one of the ratios is set to be equal to or higher than a predetermined ratio so that an input offset voltage always has a constant polarity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5758585U JPS61176813U (en) | 1985-04-19 | 1985-04-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5758585U JPS61176813U (en) | 1985-04-19 | 1985-04-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61176813U true JPS61176813U (en) | 1986-11-05 |
Family
ID=30582255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5758585U Pending JPS61176813U (en) | 1985-04-19 | 1985-04-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61176813U (en) |
-
1985
- 1985-04-19 JP JP5758585U patent/JPS61176813U/ja active Pending