JPS61174723A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61174723A JPS61174723A JP1780185A JP1780185A JPS61174723A JP S61174723 A JPS61174723 A JP S61174723A JP 1780185 A JP1780185 A JP 1780185A JP 1780185 A JP1780185 A JP 1780185A JP S61174723 A JPS61174723 A JP S61174723A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- metal plating
- etching
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000007747 plating Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 27
- 230000005669 field effect Effects 0.000 claims description 6
- 230000017525 heat dissipation Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 239000010953 base metal Substances 0.000 abstract description 6
- 230000005855 radiation Effects 0.000 abstract description 4
- 230000002787 reinforcement Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000008188 pellet Substances 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 238000003486 chemical etching Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000003014 reinforcing effect Effects 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に関し、特に砒化ガリ
ウム電界効果トランジスタ（ＧａＡｓ−ＦＥＴ） 。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a gallium arsenide field effect transistor (GaAs-FET).
砒化ガリウムマイクロ波モノリシック集積回路などの高
出力電界効果トランジスタの製造方法におけるチップ分
割１岨立て方法の改良に係るものである。The present invention relates to an improvement in the chip division and one-hole fabrication method in the manufacturing method of high-power field effect transistors such as gallium arsenide microwave monolithic integrated circuits.
従来におけるこの種の半導体装置の製造方法につき、こ
−ではマイクロ波帯高出力ＧａＡｓ−ＦＥＴを例にとっ
て述べる。第２図（ａ）ないしくｆ）はこの従来例方法
での準ミリ波帯動作高出力ＧａＡｓ−ＦＥＴにおける放
熱のための裏面ＰＨ９（Ｐｌａｔｅｄ Ｈｅａｔ ５ｉ
ｎｋ）形成工程から、チップ分割９岨立て工程に至るプ
ロセスフロー図である。A conventional method for manufacturing this type of semiconductor device will now be described using a microwave band high output GaAs-FET as an example. Figures 2(a) to 2(f) show the back surface PH9 (Plated Heat 5i) for heat dissipation in a high power GaAs-FET operating in the quasi-millimeter wave band using this conventional method.
nk) is a process flow diagram from the formation process to the chip division 9-editing process.
一般的にこの種の高出力ＧａＡｓ−ＦＥＴにおいては、
表面能動部としての、 ＦＥＴ形成面２からの発生熱
の放熱経路にあたるＧａＡｓ基板１の厚さを薄くするこ
とが、素子自体の熱抵抗Ｒｔｈの低減につながることか
ら、このＧａＡｓ基板１には１０〜５０終■オーダの厚
さ程度の極薄の素材を用いることが多い、そこでまずこ
の極薄ＧａＡ＋基板１に対しては、表面工程完了後に加
えられる熱歪みとか機械的応力などによる割れ、そりな
どを防止するために、 ＦＥＴ形成面２側には補強平板
３をワックスなどで接着させておき、かつ裏面全面には
電解メッキ用の下地金属層４を被着させる（Ｍ図（ａ）
）。Generally, in this type of high-power GaAs-FET,
Since reducing the thickness of the GaAs substrate 1, which serves as a surface active part and is a radiation path for heat generated from the FET formation surface 2, leads to a reduction in the thermal resistance Rth of the element itself, this GaAs substrate 1 has a Ultra-thin materials with a thickness on the order of ~50 mm are often used, so first of all, this ultra-thin GaA+ substrate 1 is protected against cracks and warpage due to thermal strain and mechanical stress applied after the surface process is completed. In order to prevent this, a reinforcing flat plate 3 is adhered to the FET forming surface 2 side with wax or the like, and a base metal layer 4 for electrolytic plating is applied to the entire back surface (Fig. M (a)).
).
ついで前記下地金属層４上には、各チップ毎の表面能動
部を区分して、写真製版技術により額縁状のポジ形レジ
ストパターン６を形成させ（同図（ｂ））たのち、この
レジストパターン６をマスクにして、前記ＦＥＴ形成面
２上に形成される各チップ毎に、電解メッキ法によって
ＰＨＳ金属メッキ層５を選択的に形成させる。こへでこ
の金属メッキ暦５は、その厚さが厚い程、素子自体の熱
抵抗を低減し得るために、通常は５０ル層以上の厚さに
設定されるが、前記レジストパターン６の厚さがせいぜ
い数ＪＬｍ程度であることから、この金属メッキ層５は
、その成長過程で横方向に拡がって形成さ幻、る（同図
（Ｃ））。Next, on the base metal layer 4, a frame-shaped positive resist pattern 6 is formed by photolithography, dividing the surface active part of each chip (FIG. 2(b)). 6 as a mask, a PHS metal plating layer 5 is selectively formed on each chip formed on the FET forming surface 2 by electrolytic plating. This metal plating layer 5 is normally set to a thickness of 50 layers or more because the thicker the metal plating layer 5 is, the more the thermal resistance of the element itself can be reduced. Since the thickness of the metal plating layer 5 is approximately several JLm at most, the metal plating layer 5 is formed to spread laterally during the growth process (FIG. 4(C)).
そして前記金属メッキ層５の形成後、レジストパターン
８を除去し、かつ続いて今度はこの金属メッキ暦５をマ
スクにして、化学エツチングにより下地金属層４を選択
的に除去しく同ＩＮ（ｄ））、さらに続いて化学エツチ
ングによりＧａＡｇ基板ｌ基板子ップ毎に分割されるま
でエツチングするが、このときこのＧａＡｓ基板１に対
するエツチングは、同基板１の横方向にもその厚さとは
Ｃ同程度の量だけ同時に進行し、このようにして各チッ
プ毎の分割がなされる（同図（ｅ））。After forming the metal plating layer 5, the resist pattern 8 is removed, and then, using the metal plating pattern 5 as a mask, the underlying metal layer 4 is selectively removed by chemical etching. ), and then the GaAg substrate 1 is etched by chemical etching until it is divided into sub-board chips. In this way, each chip is divided ((e) in the same figure).
その後、前記の分割されたチップを補強平板３から取外
し、これをその金属メッキ暦５側で放熱用の台座７に半
田付けなどでグイポンディングして取付けると共に、同
チップのＦＥＴ形成面２上の入力および出力パッドと、
外部回路形成基板８上の入力および出力ポンディングエ
リヤ８およびｌＯとを、それぞれに金線、アルミ線など
のポンディングワイヤ１１によりワイヤポンディングし
て組立てるのである（同図（ｆ））。Thereafter, the divided chip is removed from the reinforcing flat plate 3, and attached to the heat dissipation pedestal 7 by soldering or the like on the metal plating plate 5 side, and the FET forming surface 2 of the chip is attached. input and output pads, and
The input and output bonding areas 8 and 10 on the external circuit board 8 are assembled by wire bonding, respectively, using bonding wires 11 such as gold wire or aluminum wire (FIG. 2(f)).
しかしながらこの極薄ＧａＡｓ基板を用いた従来例によ
る高出力ＧａＡｓ−ＦＥＴでは、そのチップ分割２岨立
て工程が前記のようなプロセスフローからなるために、
チップ分割時のＧａＡｓ基板に対するサイドエツチング
のために、ＰＨ５金属メッキ層の巾が、分割される（ｉ
ａＡｓ−Ｆ−ツブの巾よりも張り出した構造となり、こ
の構造により入出力用ポンディングワイヤの長さが、張
り出し長さ分だけ長くなって、ＦＥＴの入出力パッドに
ワイヤによる大きなインダクタンス成分が付加されるこ
とになり、この結果として、ＦＥＴの入出力整合が困難
になるなどのほか、ＦＥＴ増幅器を構成する場合などに
は、広帯域設計が難しくなるなどの問題を生じ、これが
特に３０Ｇｌ（ｚ帯以上の準ミリ波帯における素子の高
周波特性を阻害する主要因の一つになっていた。However, in the conventional high-power GaAs-FET using this ultra-thin GaAs substrate, the chip division and two-layer assembly process consists of the process flow described above.
Due to side etching of the GaAs substrate during chip division, the width of the PH5 metal plating layer is divided (i
aAs-F-It has a structure that overhangs the width of the tube, and due to this structure, the length of the input/output bonding wire becomes longer by the overhang length, and a large inductance component due to the wire is added to the FET input/output pad. As a result, it becomes difficult to match the input and output of the FET, and when constructing a FET amplifier, it becomes difficult to design a wide band. This was one of the main factors that inhibited the high frequency characteristics of the device in the above-mentioned quasi-millimeter wave band.
この発明は従来のこのような製造フロー上の問題点を解
決するためになされたものであって、高周波特性に優れ
た高出力電界効果トランジスタを得ることを目的とする
。The present invention has been made in order to solve these conventional manufacturing flow problems, and aims to provide a high-output field effect transistor with excellent high frequency characteristics.
前記目的を達成するために、この発明に係る半導体装置
の製造方法は、高出力ＧａＡｓ−ＦＥＴなどの製造時に
、金属メッキ層をエツチングマスクとして微細な開口部
を形成させ、この開口部を通してチップ分割させること
により、この分割時に生ずるＰＨ５金属メッキ層の張り
出し量を低減させるようにしたものである。In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention involves forming fine openings using a metal plating layer as an etching mask during manufacturing of high-power GaAs-FETs, etc., and performing chip division through the openings. By doing so, the amount of overhang of the PH5 metal plating layer that occurs during this division is reduced.
従ってこの発明方法においては、半導体基板のチップ分
割工程で生ずる金属メッキ層の張り出し量を効果的に抑
制し得るために、結果として、入出力用ポンディングワ
イヤの長さを十分に短縮でき、コノポンディングワイヤ
によってＦＥＴに付加される入出力直列インダクタンス
を低減し得るのである。Therefore, in the method of this invention, the amount of protrusion of the metal plating layer that occurs during the chip dividing process of the semiconductor substrate can be effectively suppressed, and as a result, the length of the input/output bonding wire can be sufficiently shortened, and the length of the input/output bonding wire can be sufficiently shortened. The input/output series inductance added to the FET by the bonding wire can be reduced.
以下この発明に係る半導体装置の製造方法の一実施例に
つき、第１図（ａ）ないしくｅ）を参照して詳細に説明
する。An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIGS. 1(a) to 1(e).
第１図（ａ）ないしくｅ）はこの実施例方法を工程順に
示したプロセスフロー図であり、この第１図（ａ）ない
しくｅ）実施例方法において、前記ｗ４ｚ図（ａ）ない
しくｆ）従来例方法と同一符号は同一または相当部分を
表わしている。Figure 1 (a) to e) is a process flow diagram showing the method of this example in the order of steps. f) The same reference numerals as in the conventional method represent the same or corresponding parts.
この実施例方法においては、まず前記従来例方法と同様
にして、極薄ＧａＡｓ基板１のＦＥＴ形成面２側に補強
平板３を接着させ、かつ裏面全面に下地金属層４を被着
させた上で、この下地金属層４上に額縁状のポジ形レジ
ストパターンＢを形成させる（同図（ａ））。In this embodiment method, first, in the same manner as in the conventional method, a reinforcing flat plate 3 is adhered to the FET forming surface 2 side of the ultra-thin GaAs substrate 1, and a base metal layer 4 is coated on the entire back surface. Then, a frame-shaped positive resist pattern B is formed on this base metal layer 4 (FIG. 4(a)).
次に前記レジストパターン８をマスクにして、各チップ
対応に電解メッキ法で金属メッキ層５を選択的に形成さ
せるが、このときこれらの各金属メッキ層５の横方向へ
の拡がり量を制御して、隣接層との間のスリット１２の
巾を１０１Ｌ■程度以下に設定させるようにし、続いて
各金属メッキ層５の形成後、矢印にみられるようにチッ
プ全面を照射して（同図（ｂ））、スリット１２下のレ
ジストパターン６のみを露光かつ現像させたのち、この
金属メッキ層５をマスクにして、化学エツチングあるい
はドライエツチングにより、同スリット１２下の下地金
属層４の部分のみを除去して開口部１３を形成させる（
同図（Ｃ））。Next, using the resist pattern 8 as a mask, a metal plating layer 5 is selectively formed on each chip by electrolytic plating. At this time, the amount of horizontal spread of each metal plating layer 5 is controlled. Then, the width of the slit 12 between the adjacent layers is set to about 101 L■ or less, and after forming each metal plating layer 5, the entire surface of the chip is irradiated as shown by the arrows ( b)) After exposing and developing only the resist pattern 6 under the slit 12, using the metal plating layer 5 as a mask, only the portion of the underlying metal layer 4 under the slit 12 is etched by chemical etching or dry etching. to form the opening 13 (
Same figure (C)).
さらに前記下地金属層４に対するスリット１２下の選択
的な開口後、金属メッキ層５をマスクに、この開口部１
３を通して化学エツチングによりＧａＡｓ基板１を各チ
ップ毎に分離されるまでエツチングする。そしてこのと
きＧａＡｓ基板１の分割エツチングは、従来と同様に同
基板１の横方向にも同時に進行するが、このニー２チン
グがスリット１２下の開口部１３を通してなされるため
に、横方向へのサイドエツチング量を著るしく低減でき
て、結果的にはＧａＡｓ基板１に対する金属メッキＲ５
の張り出し量を効果的かつ実質的に抑制し得るのであり
、このようにして各チップ毎の分割がなされる（同図（
ｄ））。Furthermore, after selectively opening the base metal layer 4 below the slit 12, the opening 1 is opened using the metal plating layer 5 as a mask.
3, the GaAs substrate 1 is etched by chemical etching until each chip is separated. At this time, the dividing etching of the GaAs substrate 1 simultaneously proceeds in the lateral direction of the substrate 1, as in the past, but since this kneeling is done through the opening 13 below the slit 12, the etching in the lateral direction also progresses. The amount of side etching can be significantly reduced, and as a result, metal plating R5 on the GaAs substrate 1 can be reduced.
The amount of overhang can be effectively and substantially suppressed, and in this way, each chip is divided (as shown in the same figure).
d)).
そしてその後は、従来例と全く同様にして、分割された
チップを補強平板３から取外し、これをその金属メッキ
層５側で放熱用の台座７に半田付けなどでグイポンディ
ングして取付けると共に、同チップのＦＥＴ形成面２上
の入力および出力パッドと、外部回路形成基板８上の入
力および出力ポンディングエリヤ８および１０とを、そ
れぞれに金線、アルミ線などのポンディングワイヤ１１
によりワイヤポンディングして組立てるのである（ＩＷ
Ｉ図（ｆ））。After that, in exactly the same manner as in the conventional example, the divided chips are removed from the reinforcing flat plate 3, and attached to the heat dissipation pedestal 7 by soldering or the like on the metal plating layer 5 side, and The input and output pads on the FET forming surface 2 of the chip and the input and output bonding areas 8 and 10 on the external circuit forming board 8 are connected to bonding wires 11 such as gold wires and aluminum wires, respectively.
It is assembled by wire bonding (IW
Figure I (f)).
なお、前記実施例方法においては、チップ分割エツチン
グのための開口部を、レジストの選択的な露光、現像と
、化学エツチング、ドライエツチングなどにより形成さ
せるようにしているが、これに代えてその他のマスク層
２例えばシリコン酸化膜、窒化膜などの絶縁膜を用い、
金属メッキ層をエツチングマスクとして、反応性イオン
エツチング（ＲＩＥ）などにより、金属メッキ層間のス
リット下の絶縁膜のみを選択的に除去することで、同様
に微細開口部を形成させることができる。In the method of the above embodiment, the openings for chip division etching are formed by selective exposure and development of the resist, chemical etching, dry etching, etc. However, other methods may be used instead. Mask layer 2: For example, using an insulating film such as a silicon oxide film or a nitride film,
Similarly, fine openings can be formed by selectively removing only the insulating film under the slit between the metal plating layers by reactive ion etching (RIE) or the like using the metal plating layer as an etching mask.
また前記実施例方法では、高出力ＧａＡｓ−ＦＥＴに適
用する場合について述べたが、その他のチップ分割をな
す素子構成９例えば高出力シリコンＦＥＴなどに適用し
ても同様な効果を得られることは勿論である。Furthermore, in the above embodiment method, the case where it is applied to a high-power GaAs-FET has been described, but it goes without saying that the same effect can be obtained even if it is applied to other chip-divided element configurations 9, such as a high-power silicon FET. It is.
以上詳述したようにこの発明方法によれば、高出力電界
効果トランジスタの製造に際し、放熱用金属メッキ暦を
エツチングマスクにして、基板チップ分割のためのエツ
チング用微細開口部を形成させ、この開口部を通してチ
ップ分割させるようにしたから、基板に対する金属メッ
キ層の張り出し量を効果的、かつ実質的に抑制でき、こ
れによって素子の入出力直列インピーダンスを低減し得
られ、このため装置の入出力整合が容易になり、広帯域
設計が可能で、しかも優れた高周波特性の高出力電界効
果トランジスタを提供できるものである。As detailed above, according to the method of the present invention, when manufacturing a high-output field effect transistor, a heat-dissipating metal plating pattern is used as an etching mask to form fine etching openings for dividing the substrate chips. Since the chip is divided through the parts, the amount of overhang of the metal plating layer relative to the substrate can be effectively and substantially suppressed, thereby reducing the input/output series impedance of the device, thereby improving the input/output matching of the device. Accordingly, it is possible to provide a high-output field effect transistor with excellent high-frequency characteristics.
第１図（ａ）ないしくｅ）はこの発明に係る半導体装置
の製造方法の一実施例によるプロセスフロー図であり、
また第２図（ａ）ないしくｆ）は同上従来例方法による
プロセスフロー図でアル。
１・・・・ＧａＡｓ基板（半導体基板）、２・・・・Ｆ
Ｅ丁影形成面能動部）、３・・・・補強平板、４・・・
・下地金層、５・・・・金属メッキ層、６・・・・レジ
ストパターン（マスク層）、７・・・・放熱用の台座、
８・・・・外部回路形成基板、８，１０・・・・入力、
出力ポンディングエリヤ、１１・・・・ポンディングワ
イヤ、１２・・・・スリット、１３・・・・開口部。
代理人 大 岩 増 雄
第１図FIGS. 1(a) to 1(e) are process flow diagrams according to an embodiment of the method for manufacturing a semiconductor device according to the present invention,
Further, FIGS. 2(a) to 2(f) are process flow diagrams according to the conventional method described above. 1...GaAs substrate (semiconductor substrate), 2...F
E-cho shadow forming surface active part), 3... Reinforcement flat plate, 4...
・Base gold layer, 5...Metal plating layer, 6...Resist pattern (mask layer), 7...Pedestal for heat dissipation,
8... External circuit forming board, 8, 10... Input,
Output bonding area, 11... bonding wire, 12... slit, 13... opening. Agent Masuo Oiwa Figure 1
Claims (3)
属メッキ層を形成させた高出力電界効果トランジスタな
どの半導体装置の製造方法であつて、前記半導体基板の
裏面に、各チップ毎の表面能動部を区分する額縁状のマ
スク層を形成させ、かつ前記各チップに対応する金属メ
ッキ層を、隣接層間に微細なスリットを残してそれぞれ
選択的に形成する工程と、前記金属メッキ層をエッチン
グマスクに用い、前記スリット下のマスク層を選択的に
エッチングして開口部を形成する工程と、この開口部を
通して前記半導体基板を各チップ毎に分割する工程とを
含み、チップ分割後の半導体基板に対する金属メッキ層
の張り出し量を低減させたことを特徴とする半導体装置
の製造方法。(1) A method for manufacturing a semiconductor device such as a high-output field effect transistor in which a front surface active part and a back surface metal plating layer for heat dissipation are formed on a semiconductor substrate, wherein the surface of each chip is formed on the back surface of the semiconductor substrate. A step of forming a frame-shaped mask layer for dividing the active part, and selectively forming a metal plating layer corresponding to each chip, leaving fine slits between adjacent layers, and etching the metal plating layer. The method includes a step of selectively etching a mask layer under the slit using a mask to form an opening, and a step of dividing the semiconductor substrate into each chip through the opening. A method for manufacturing a semiconductor device, characterized in that the amount of overhang of a metal plating layer is reduced.
より区分させ、このレジスト層を金属メッキ層のマスク
で露光、現像させてマスク層としたことを特徴とする特
許請求の範囲第１項記載の半導体装置の製造方法。(2) The surface active portion of each chip is divided by a frame-shaped resist layer, and this resist layer is exposed and developed using a mask of a metal plating layer to form a mask layer. A method for manufacturing a semiconductor device according to section 1.
化膜などの絶縁膜により形成させたことを特徴とする特
許請求の範囲第１項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the frame-shaped mask layer is formed of an insulating film such as a silicon oxide film or a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1780185A JPS61174723A (en) | 1985-01-30 | 1985-01-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1780185A JPS61174723A (en) | 1985-01-30 | 1985-01-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174723A true JPS61174723A (en) | 1986-08-06 |
Family
ID=11953819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1780185A Pending JPS61174723A (en) | 1985-01-30 | 1985-01-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174723A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7092890B2 (en) * | 2002-11-27 | 2006-08-15 | Freescale Semiconductor, Inc. | Method for manufacturing thin GaAs die with copper-back metal structures |
-
1985
- 1985-01-30 JP JP1780185A patent/JPS61174723A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7092890B2 (en) * | 2002-11-27 | 2006-08-15 | Freescale Semiconductor, Inc. | Method for manufacturing thin GaAs die with copper-back metal structures |
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